1 /* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19 #include "opt_ah.h" 20 21 #include "ah.h" 22 #include "ah_internal.h" 23 #include "ah_devid.h" 24 25 #include "ah_eeprom_v14.h" 26 27 #include "ar5416/ar5416.h" 28 #include "ar5416/ar5416reg.h" 29 #include "ar5416/ar5416phy.h" 30 31 #include "ar5416/ar5416.ini" 32 33 static void ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, 34 HAL_BOOL power_off); 35 static void ar5416DisablePCIE(struct ath_hal *ah); 36 static void ar5416WriteIni(struct ath_hal *ah, 37 const struct ieee80211_channel *chan); 38 static void ar5416SpurMitigate(struct ath_hal *ah, 39 const struct ieee80211_channel *chan); 40 41 static void 42 ar5416AniSetup(struct ath_hal *ah) 43 { 44 static const struct ar5212AniParams aniparams = { 45 .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 46 .totalSizeDesired = { -55, -55, -55, -55, -62 }, 47 .coarseHigh = { -14, -14, -14, -14, -12 }, 48 .coarseLow = { -64, -64, -64, -64, -70 }, 49 .firpwr = { -78, -78, -78, -78, -80 }, 50 .maxSpurImmunityLevel = 2, 51 .cycPwrThr1 = { 2, 4, 6 }, 52 .maxFirstepLevel = 2, /* levels 0..2 */ 53 .firstep = { 0, 4, 8 }, 54 .ofdmTrigHigh = 500, 55 .ofdmTrigLow = 200, 56 .cckTrigHigh = 200, 57 .cckTrigLow = 100, 58 .rssiThrHigh = 40, 59 .rssiThrLow = 7, 60 .period = 100, 61 }; 62 /* NB: disable ANI noise immmunity for reliable RIFS rx */ 63 AH5416(ah)->ah_ani_function &= ~(1 << HAL_ANI_NOISE_IMMUNITY_LEVEL); 64 ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE); 65 } 66 67 /* 68 * AR5416 doesn't do OLC or temperature compensation. 69 */ 70 static void 71 ar5416olcInit(struct ath_hal *ah) 72 { 73 } 74 75 static void 76 ar5416olcTempCompensation(struct ath_hal *ah) 77 { 78 } 79 80 /* 81 * Attach for an AR5416 part. 82 */ 83 void 84 ar5416InitState(struct ath_hal_5416 *ahp5416, uint16_t devid, HAL_SOFTC sc, 85 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status) 86 { 87 struct ath_hal_5212 *ahp; 88 struct ath_hal *ah; 89 90 ahp = &ahp5416->ah_5212; 91 ar5212InitState(ahp, devid, sc, st, sh, status); 92 ah = &ahp->ah_priv.h; 93 94 /* override 5212 methods for our needs */ 95 ah->ah_magic = AR5416_MAGIC; 96 ah->ah_getRateTable = ar5416GetRateTable; 97 ah->ah_detach = ar5416Detach; 98 99 /* Reset functions */ 100 ah->ah_reset = ar5416Reset; 101 ah->ah_phyDisable = ar5416PhyDisable; 102 ah->ah_disable = ar5416Disable; 103 ah->ah_configPCIE = ar5416ConfigPCIE; 104 ah->ah_disablePCIE = ar5416DisablePCIE; 105 ah->ah_perCalibration = ar5416PerCalibration; 106 ah->ah_perCalibrationN = ar5416PerCalibrationN, 107 ah->ah_resetCalValid = ar5416ResetCalValid, 108 ah->ah_setTxPowerLimit = ar5416SetTxPowerLimit; 109 ah->ah_setTxPower = ar5416SetTransmitPower; 110 ah->ah_setBoardValues = ar5416SetBoardValues; 111 112 /* Transmit functions */ 113 ah->ah_stopTxDma = ar5416StopTxDma; 114 ah->ah_setupTxDesc = ar5416SetupTxDesc; 115 ah->ah_setupXTxDesc = ar5416SetupXTxDesc; 116 ah->ah_fillTxDesc = ar5416FillTxDesc; 117 ah->ah_procTxDesc = ar5416ProcTxDesc; 118 ah->ah_getTxCompletionRates = ar5416GetTxCompletionRates; 119 ah->ah_setupTxQueue = ar5416SetupTxQueue; 120 ah->ah_resetTxQueue = ar5416ResetTxQueue; 121 122 /* Receive Functions */ 123 ah->ah_getRxFilter = ar5416GetRxFilter; 124 ah->ah_setRxFilter = ar5416SetRxFilter; 125 ah->ah_stopDmaReceive = ar5416StopDmaReceive; 126 ah->ah_startPcuReceive = ar5416StartPcuReceive; 127 ah->ah_stopPcuReceive = ar5416StopPcuReceive; 128 ah->ah_setupRxDesc = ar5416SetupRxDesc; 129 ah->ah_procRxDesc = ar5416ProcRxDesc; 130 ah->ah_rxMonitor = ar5416RxMonitor; 131 ah->ah_aniPoll = ar5416AniPoll; 132 ah->ah_procMibEvent = ar5416ProcessMibIntr; 133 134 /* Misc Functions */ 135 ah->ah_getCapability = ar5416GetCapability; 136 ah->ah_setCapability = ar5416SetCapability; 137 ah->ah_getDiagState = ar5416GetDiagState; 138 ah->ah_setLedState = ar5416SetLedState; 139 ah->ah_gpioCfgOutput = ar5416GpioCfgOutput; 140 ah->ah_gpioCfgInput = ar5416GpioCfgInput; 141 ah->ah_gpioGet = ar5416GpioGet; 142 ah->ah_gpioSet = ar5416GpioSet; 143 ah->ah_gpioSetIntr = ar5416GpioSetIntr; 144 ah->ah_getTsf64 = ar5416GetTsf64; 145 ah->ah_resetTsf = ar5416ResetTsf; 146 ah->ah_getRfGain = ar5416GetRfgain; 147 ah->ah_setAntennaSwitch = ar5416SetAntennaSwitch; 148 ah->ah_setDecompMask = ar5416SetDecompMask; 149 ah->ah_setCoverageClass = ar5416SetCoverageClass; 150 ah->ah_setQuiet = ar5416SetQuiet; 151 ah->ah_getMibCycleCounts = ar5416GetMibCycleCounts; 152 153 ah->ah_resetKeyCacheEntry = ar5416ResetKeyCacheEntry; 154 ah->ah_setKeyCacheEntry = ar5416SetKeyCacheEntry; 155 156 /* DFS Functions */ 157 ah->ah_enableDfs = ar5416EnableDfs; 158 ah->ah_getDfsThresh = ar5416GetDfsThresh; 159 ah->ah_getDfsDefaultThresh = ar5416GetDfsDefaultThresh; 160 ah->ah_procRadarEvent = ar5416ProcessRadarEvent; 161 ah->ah_isFastClockEnabled = ar5416IsFastClockEnabled; 162 163 /* Power Management Functions */ 164 ah->ah_setPowerMode = ar5416SetPowerMode; 165 166 /* Beacon Management Functions */ 167 ah->ah_setBeaconTimers = ar5416SetBeaconTimers; 168 ah->ah_beaconInit = ar5416BeaconInit; 169 ah->ah_setStationBeaconTimers = ar5416SetStaBeaconTimers; 170 ah->ah_resetStationBeaconTimers = ar5416ResetStaBeaconTimers; 171 ah->ah_getNextTBTT = ar5416GetNextTBTT; 172 173 /* 802.11n Functions */ 174 ah->ah_chainTxDesc = ar5416ChainTxDesc; 175 ah->ah_setupFirstTxDesc = ar5416SetupFirstTxDesc; 176 ah->ah_setupLastTxDesc = ar5416SetupLastTxDesc; 177 ah->ah_set11nRateScenario = ar5416Set11nRateScenario; 178 ah->ah_set11nAggrFirst = ar5416Set11nAggrFirst; 179 ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle; 180 ah->ah_set11nAggrLast = ar5416Set11nAggrLast; 181 ah->ah_clr11nAggr = ar5416Clr11nAggr; 182 ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration; 183 ah->ah_get11nExtBusy = ar5416Get11nExtBusy; 184 ah->ah_set11nMac2040 = ar5416Set11nMac2040; 185 ah->ah_get11nRxClear = ar5416Get11nRxClear; 186 ah->ah_set11nRxClear = ar5416Set11nRxClear; 187 188 /* Interrupt functions */ 189 ah->ah_isInterruptPending = ar5416IsInterruptPending; 190 ah->ah_getPendingInterrupts = ar5416GetPendingInterrupts; 191 ah->ah_setInterrupts = ar5416SetInterrupts; 192 193 ahp->ah_priv.ah_getWirelessModes= ar5416GetWirelessModes; 194 ahp->ah_priv.ah_eepromRead = ar5416EepromRead; 195 #ifdef AH_SUPPORT_WRITE_EEPROM 196 ahp->ah_priv.ah_eepromWrite = ar5416EepromWrite; 197 #endif 198 ahp->ah_priv.ah_getChipPowerLimits = ar5416GetChipPowerLimits; 199 200 /* Internal ops */ 201 AH5416(ah)->ah_writeIni = ar5416WriteIni; 202 AH5416(ah)->ah_spurMitigate = ar5416SpurMitigate; 203 204 /* Internal baseband ops */ 205 AH5416(ah)->ah_initPLL = ar5416InitPLL; 206 207 /* Internal calibration ops */ 208 AH5416(ah)->ah_cal_initcal = ar5416InitCalHardware; 209 210 /* Internal TX power control related operations */ 211 AH5416(ah)->ah_olcInit = ar5416olcInit; 212 AH5416(ah)->ah_olcTempCompensation = ar5416olcTempCompensation; 213 AH5416(ah)->ah_setPowerCalTable = ar5416SetPowerCalTable; 214 215 /* 216 * Start by setting all Owl devices to 2x2 217 */ 218 AH5416(ah)->ah_rx_chainmask = AR5416_DEFAULT_RXCHAINMASK; 219 AH5416(ah)->ah_tx_chainmask = AR5416_DEFAULT_TXCHAINMASK; 220 221 /* Enable all ANI functions to begin with */ 222 AH5416(ah)->ah_ani_function = 0xffffffff; 223 224 /* Set overridable ANI methods */ 225 AH5212(ah)->ah_aniControl = ar5416AniControl; 226 } 227 228 uint32_t 229 ar5416GetRadioRev(struct ath_hal *ah) 230 { 231 uint32_t val; 232 int i; 233 234 /* Read Radio Chip Rev Extract */ 235 OS_REG_WRITE(ah, AR_PHY(0x36), 0x00007058); 236 for (i = 0; i < 8; i++) 237 OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000); 238 val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; 239 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 240 return ath_hal_reverseBits(val, 8); 241 } 242 243 /* 244 * Attach for an AR5416 part. 245 */ 246 static struct ath_hal * 247 ar5416Attach(uint16_t devid, HAL_SOFTC sc, 248 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 249 HAL_STATUS *status) 250 { 251 struct ath_hal_5416 *ahp5416; 252 struct ath_hal_5212 *ahp; 253 struct ath_hal *ah; 254 uint32_t val; 255 HAL_STATUS ecode; 256 HAL_BOOL rfStatus; 257 258 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 259 __func__, sc, (void*) st, (void*) sh); 260 261 /* NB: memory is returned zero'd */ 262 ahp5416 = ath_hal_malloc(sizeof (struct ath_hal_5416) + 263 /* extra space for Owl 2.1/2.2 WAR */ 264 sizeof(ar5416Addac) 265 ); 266 if (ahp5416 == AH_NULL) { 267 HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 268 "%s: cannot allocate memory for state block\n", __func__); 269 *status = HAL_ENOMEM; 270 return AH_NULL; 271 } 272 ar5416InitState(ahp5416, devid, sc, st, sh, status); 273 ahp = &ahp5416->ah_5212; 274 ah = &ahp->ah_priv.h; 275 276 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { 277 /* reset chip */ 278 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", __func__); 279 ecode = HAL_EIO; 280 goto bad; 281 } 282 283 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 284 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", __func__); 285 ecode = HAL_EIO; 286 goto bad; 287 } 288 /* Read Revisions from Chips before taking out of reset */ 289 val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID; 290 AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S; 291 AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION; 292 AH_PRIVATE(ah)->ah_ispcie = (devid == AR5416_DEVID_PCIE); 293 294 /* setup common ini data; rf backends handle remainder */ 295 HAL_INI_INIT(&ahp->ah_ini_modes, ar5416Modes, 6); 296 HAL_INI_INIT(&ahp->ah_ini_common, ar5416Common, 2); 297 298 HAL_INI_INIT(&AH5416(ah)->ah_ini_bb_rfgain, ar5416BB_RfGain, 3); 299 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank0, ar5416Bank0, 2); 300 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank1, ar5416Bank1, 2); 301 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank2, ar5416Bank2, 2); 302 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank3, ar5416Bank3, 3); 303 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank6, ar5416Bank6, 3); 304 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank7, ar5416Bank7, 2); 305 HAL_INI_INIT(&AH5416(ah)->ah_ini_addac, ar5416Addac, 2); 306 307 if (! IS_5416V2_2(ah)) { /* Owl 2.1/2.0 */ 308 ath_hal_printf(ah, "[ath] Enabling CLKDRV workaround for AR5416 < v2.2\n"); 309 struct ini { 310 uint32_t *data; /* NB: !const */ 311 int rows, cols; 312 }; 313 /* override CLKDRV value */ 314 OS_MEMCPY(&AH5416(ah)[1], ar5416Addac, sizeof(ar5416Addac)); 315 AH5416(ah)->ah_ini_addac.data = (uint32_t *) &AH5416(ah)[1]; 316 HAL_INI_VAL((struct ini *)&AH5416(ah)->ah_ini_addac, 31, 1) = 0; 317 } 318 319 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, ar5416PciePhy, 2); 320 ar5416AttachPCIE(ah); 321 322 ecode = ath_hal_v14EepromAttach(ah); 323 if (ecode != HAL_OK) 324 goto bad; 325 326 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */ 327 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", 328 __func__); 329 ecode = HAL_EIO; 330 goto bad; 331 } 332 333 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 334 335 if (!ar5212ChipTest(ah)) { 336 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 337 __func__); 338 ecode = HAL_ESELFTEST; 339 goto bad; 340 } 341 342 /* 343 * Set correct Baseband to analog shift 344 * setting to access analog chips. 345 */ 346 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 347 348 /* Read Radio Chip Rev Extract */ 349 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah); 350 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 351 case AR_RAD5122_SREV_MAJOR: /* Fowl: 5G/2x2 */ 352 case AR_RAD2122_SREV_MAJOR: /* Fowl: 2+5G/2x2 */ 353 case AR_RAD2133_SREV_MAJOR: /* Fowl: 2G/3x3 */ 354 case AR_RAD5133_SREV_MAJOR: /* Fowl: 2+5G/3x3 */ 355 break; 356 default: 357 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 358 /* 359 * When RF_Silen is used the analog chip is reset. 360 * So when the system boots with radio switch off 361 * the RF chip rev reads back as zero and we need 362 * to use the mac+phy revs to set the radio rev. 363 */ 364 AH_PRIVATE(ah)->ah_analog5GhzRev = 365 AR_RAD5133_SREV_MAJOR; 366 break; 367 } 368 /* NB: silently accept anything in release code per Atheros */ 369 #ifdef AH_DEBUG 370 HALDEBUG(ah, HAL_DEBUG_ANY, 371 "%s: 5G Radio Chip Rev 0x%02X is not supported by " 372 "this driver\n", __func__, 373 AH_PRIVATE(ah)->ah_analog5GhzRev); 374 ecode = HAL_ENOTSUPP; 375 goto bad; 376 #endif 377 } 378 379 /* 380 * Got everything we need now to setup the capabilities. 381 */ 382 if (!ar5416FillCapabilityInfo(ah)) { 383 ecode = HAL_EEREAD; 384 goto bad; 385 } 386 387 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 388 if (ecode != HAL_OK) { 389 HALDEBUG(ah, HAL_DEBUG_ANY, 390 "%s: error getting mac address from EEPROM\n", __func__); 391 goto bad; 392 } 393 /* XXX How about the serial number ? */ 394 /* Read Reg Domain */ 395 AH_PRIVATE(ah)->ah_currentRD = 396 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL); 397 AH_PRIVATE(ah)->ah_currentRDext = 398 ath_hal_eepromGet(ah, AR_EEP_REGDMN_1, AH_NULL); 399 400 /* 401 * ah_miscMode is populated by ar5416FillCapabilityInfo() 402 * starting from griffin. Set here to make sure that 403 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is 404 * placed into hardware. 405 */ 406 if (ahp->ah_miscMode != 0) 407 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode); 408 409 rfStatus = ar2133RfAttach(ah, &ecode); 410 if (!rfStatus) { 411 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 412 __func__, ecode); 413 goto bad; 414 } 415 416 ar5416AniSetup(ah); /* Anti Noise Immunity */ 417 418 AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ; 419 AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ; 420 AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ; 421 AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ; 422 AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ; 423 AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ; 424 425 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist); 426 427 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 428 429 return ah; 430 bad: 431 if (ahp) 432 ar5416Detach((struct ath_hal *) ahp); 433 if (status) 434 *status = ecode; 435 return AH_NULL; 436 } 437 438 void 439 ar5416Detach(struct ath_hal *ah) 440 { 441 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__); 442 443 HALASSERT(ah != AH_NULL); 444 HALASSERT(ah->ah_magic == AR5416_MAGIC); 445 446 /* Make sure that chip is awake before writing to it */ 447 if (! ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 448 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, 449 "%s: failed to wake up chip\n", 450 __func__); 451 452 ar5416AniDetach(ah); 453 ar5212RfDetach(ah); 454 ah->ah_disable(ah); 455 ar5416SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); 456 ath_hal_eepromDetach(ah); 457 ath_hal_free(ah); 458 } 459 460 void 461 ar5416AttachPCIE(struct ath_hal *ah) 462 { 463 if (AH_PRIVATE(ah)->ah_ispcie) 464 ath_hal_configPCIE(ah, AH_FALSE, AH_FALSE); 465 else 466 ath_hal_disablePCIE(ah); 467 } 468 469 static void 470 ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off) 471 { 472 473 /* This is only applicable for AR5418 (AR5416 PCIe) */ 474 if (! AH_PRIVATE(ah)->ah_ispcie) 475 return; 476 477 if (! restore) { 478 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0); 479 OS_DELAY(1000); 480 } 481 482 if (power_off) { /* Power-off */ 483 /* clear bit 19 to disable L1 */ 484 OS_REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 485 } else { /* Power-on */ 486 /* Set default WAR values for Owl */ 487 OS_REG_WRITE(ah, AR_WA, AR_WA_DEFAULT); 488 489 /* set bit 19 to allow forcing of pcie core into L1 state */ 490 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 491 } 492 } 493 494 /* 495 * Disable PCIe PHY if PCIe isn't used. 496 */ 497 static void 498 ar5416DisablePCIE(struct ath_hal *ah) 499 { 500 501 /* PCIe? Don't */ 502 if (AH_PRIVATE(ah)->ah_ispcie) 503 return; 504 505 /* .. Only applicable for AR5416v2 or later */ 506 if (! (AR_SREV_OWL(ah) && AR_SREV_OWL_20_OR_LATER(ah))) 507 return; 508 509 OS_REG_WRITE_BUFFER_ENABLE(ah); 510 511 /* 512 * Disable the PCIe PHY. 513 */ 514 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 515 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 516 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 517 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); 518 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); 519 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); 520 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 521 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 522 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 523 524 /* Load the new settings */ 525 OS_REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 526 527 OS_REG_WRITE_BUFFER_FLUSH(ah); 528 OS_REG_WRITE_BUFFER_DISABLE(ah); 529 } 530 531 static void 532 ar5416WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan) 533 { 534 u_int modesIndex, freqIndex; 535 int regWrites = 0; 536 537 /* Setup the indices for the next set of register array writes */ 538 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */ 539 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 540 freqIndex = 2; 541 if (IEEE80211_IS_CHAN_HT40(chan)) 542 modesIndex = 3; 543 else if (IEEE80211_IS_CHAN_108G(chan)) 544 modesIndex = 5; 545 else 546 modesIndex = 4; 547 } else { 548 freqIndex = 1; 549 if (IEEE80211_IS_CHAN_HT40(chan) || 550 IEEE80211_IS_CHAN_TURBO(chan)) 551 modesIndex = 2; 552 else 553 modesIndex = 1; 554 } 555 556 /* Set correct Baseband to analog shift setting to access analog chips. */ 557 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 558 559 /* 560 * Write addac shifts 561 */ 562 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); 563 564 /* NB: only required for Sowl */ 565 if (AR_SREV_SOWL(ah)) 566 ar5416EepromSetAddac(ah, chan); 567 568 regWrites = ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_addac, 1, 569 regWrites); 570 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 571 572 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, 573 modesIndex, regWrites); 574 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 575 1, regWrites); 576 577 /* XXX updated regWrites? */ 578 AH5212(ah)->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites); 579 } 580 581 /* 582 * Convert to baseband spur frequency given input channel frequency 583 * and compute register settings below. 584 */ 585 586 static void 587 ar5416SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan) 588 { 589 uint16_t freq = ath_hal_gethwchannel(ah, chan); 590 static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, 591 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 }; 592 static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, 593 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 }; 594 static const int inc[4] = { 0, 100, 0, 0 }; 595 596 int bb_spur = AR_NO_SPUR; 597 int bin, cur_bin; 598 int spur_freq_sd; 599 int spur_delta_phase; 600 int denominator; 601 int upper, lower, cur_vit_mask; 602 int tmp, new; 603 int i; 604 605 int8_t mask_m[123]; 606 int8_t mask_p[123]; 607 int8_t mask_amt; 608 int tmp_mask; 609 int cur_bb_spur; 610 HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 611 612 OS_MEMZERO(mask_m, sizeof(mask_m)); 613 OS_MEMZERO(mask_p, sizeof(mask_p)); 614 615 /* 616 * Need to verify range +/- 9.5 for static ht20, otherwise spur 617 * is out-of-band and can be ignored. 618 */ 619 /* XXX ath9k changes */ 620 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { 621 cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz); 622 if (AR_NO_SPUR == cur_bb_spur) 623 break; 624 cur_bb_spur = cur_bb_spur - (freq * 10); 625 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) { 626 bb_spur = cur_bb_spur; 627 break; 628 } 629 } 630 if (AR_NO_SPUR == bb_spur) 631 return; 632 633 bin = bb_spur * 32; 634 635 tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)); 636 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 637 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 638 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 639 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 640 641 OS_REG_WRITE_BUFFER_ENABLE(ah); 642 643 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), new); 644 645 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 646 AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 647 AR_PHY_SPUR_REG_MASK_RATE_SELECT | 648 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 649 SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 650 OS_REG_WRITE(ah, AR_PHY_SPUR_REG, new); 651 /* 652 * Should offset bb_spur by +/- 10 MHz for dynamic 2040 MHz 653 * config, no offset for HT20. 654 * spur_delta_phase = bb_spur/40 * 2**21 for static ht20, 655 * /80 for dyn2040. 656 */ 657 spur_delta_phase = ((bb_spur * 524288) / 100) & 658 AR_PHY_TIMING11_SPUR_DELTA_PHASE; 659 /* 660 * in 11A mode the denominator of spur_freq_sd should be 40 and 661 * it should be 44 in 11G 662 */ 663 denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 440 : 400; 664 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff; 665 666 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 667 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 668 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 669 OS_REG_WRITE(ah, AR_PHY_TIMING11, new); 670 671 672 /* 673 * ============================================ 674 * pilot mask 1 [31:0] = +6..-26, no 0 bin 675 * pilot mask 2 [19:0] = +26..+7 676 * 677 * channel mask 1 [31:0] = +6..-26, no 0 bin 678 * channel mask 2 [19:0] = +26..+7 679 */ 680 //cur_bin = -26; 681 cur_bin = -6000; 682 upper = bin + 100; 683 lower = bin - 100; 684 685 for (i = 0; i < 4; i++) { 686 int pilot_mask = 0; 687 int chan_mask = 0; 688 int bp = 0; 689 for (bp = 0; bp < 30; bp++) { 690 if ((cur_bin > lower) && (cur_bin < upper)) { 691 pilot_mask = pilot_mask | 0x1 << bp; 692 chan_mask = chan_mask | 0x1 << bp; 693 } 694 cur_bin += 100; 695 } 696 cur_bin += inc[i]; 697 OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 698 OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask); 699 } 700 701 /* ================================================= 702 * viterbi mask 1 based on channel magnitude 703 * four levels 0-3 704 * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c) 705 * [1 2 2 1] for -9.6 or [1 2 1] for +16 706 * - enable_mask_ppm, all bins move with freq 707 * 708 * - mask_select, 8 bits for rates (reg 67,0x990c) 709 * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c) 710 * choose which mask to use mask or mask2 711 */ 712 713 /* 714 * viterbi mask 2 2nd set for per data rate puncturing 715 * four levels 0-3 716 * - mask_select, 8 bits for rates (reg 67) 717 * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994) 718 * [1 2 2 1] for -9.6 or [1 2 1] for +16 719 */ 720 cur_vit_mask = 6100; 721 upper = bin + 120; 722 lower = bin - 120; 723 724 for (i = 0; i < 123; i++) { 725 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 726 if ((abs(cur_vit_mask - bin)) < 75) { 727 mask_amt = 1; 728 } else { 729 mask_amt = 0; 730 } 731 if (cur_vit_mask < 0) { 732 mask_m[abs(cur_vit_mask / 100)] = mask_amt; 733 } else { 734 mask_p[cur_vit_mask / 100] = mask_amt; 735 } 736 } 737 cur_vit_mask -= 100; 738 } 739 740 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 741 | (mask_m[48] << 26) | (mask_m[49] << 24) 742 | (mask_m[50] << 22) | (mask_m[51] << 20) 743 | (mask_m[52] << 18) | (mask_m[53] << 16) 744 | (mask_m[54] << 14) | (mask_m[55] << 12) 745 | (mask_m[56] << 10) | (mask_m[57] << 8) 746 | (mask_m[58] << 6) | (mask_m[59] << 4) 747 | (mask_m[60] << 2) | (mask_m[61] << 0); 748 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 749 OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 750 751 tmp_mask = (mask_m[31] << 28) 752 | (mask_m[32] << 26) | (mask_m[33] << 24) 753 | (mask_m[34] << 22) | (mask_m[35] << 20) 754 | (mask_m[36] << 18) | (mask_m[37] << 16) 755 | (mask_m[48] << 14) | (mask_m[39] << 12) 756 | (mask_m[40] << 10) | (mask_m[41] << 8) 757 | (mask_m[42] << 6) | (mask_m[43] << 4) 758 | (mask_m[44] << 2) | (mask_m[45] << 0); 759 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 760 OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 761 762 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 763 | (mask_m[18] << 26) | (mask_m[18] << 24) 764 | (mask_m[20] << 22) | (mask_m[20] << 20) 765 | (mask_m[22] << 18) | (mask_m[22] << 16) 766 | (mask_m[24] << 14) | (mask_m[24] << 12) 767 | (mask_m[25] << 10) | (mask_m[26] << 8) 768 | (mask_m[27] << 6) | (mask_m[28] << 4) 769 | (mask_m[29] << 2) | (mask_m[30] << 0); 770 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 771 OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 772 773 tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28) 774 | (mask_m[ 2] << 26) | (mask_m[ 3] << 24) 775 | (mask_m[ 4] << 22) | (mask_m[ 5] << 20) 776 | (mask_m[ 6] << 18) | (mask_m[ 7] << 16) 777 | (mask_m[ 8] << 14) | (mask_m[ 9] << 12) 778 | (mask_m[10] << 10) | (mask_m[11] << 8) 779 | (mask_m[12] << 6) | (mask_m[13] << 4) 780 | (mask_m[14] << 2) | (mask_m[15] << 0); 781 OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 782 OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 783 784 tmp_mask = (mask_p[15] << 28) 785 | (mask_p[14] << 26) | (mask_p[13] << 24) 786 | (mask_p[12] << 22) | (mask_p[11] << 20) 787 | (mask_p[10] << 18) | (mask_p[ 9] << 16) 788 | (mask_p[ 8] << 14) | (mask_p[ 7] << 12) 789 | (mask_p[ 6] << 10) | (mask_p[ 5] << 8) 790 | (mask_p[ 4] << 6) | (mask_p[ 3] << 4) 791 | (mask_p[ 2] << 2) | (mask_p[ 1] << 0); 792 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 793 OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 794 795 tmp_mask = (mask_p[30] << 28) 796 | (mask_p[29] << 26) | (mask_p[28] << 24) 797 | (mask_p[27] << 22) | (mask_p[26] << 20) 798 | (mask_p[25] << 18) | (mask_p[24] << 16) 799 | (mask_p[23] << 14) | (mask_p[22] << 12) 800 | (mask_p[21] << 10) | (mask_p[20] << 8) 801 | (mask_p[19] << 6) | (mask_p[18] << 4) 802 | (mask_p[17] << 2) | (mask_p[16] << 0); 803 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 804 OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 805 806 tmp_mask = (mask_p[45] << 28) 807 | (mask_p[44] << 26) | (mask_p[43] << 24) 808 | (mask_p[42] << 22) | (mask_p[41] << 20) 809 | (mask_p[40] << 18) | (mask_p[39] << 16) 810 | (mask_p[38] << 14) | (mask_p[37] << 12) 811 | (mask_p[36] << 10) | (mask_p[35] << 8) 812 | (mask_p[34] << 6) | (mask_p[33] << 4) 813 | (mask_p[32] << 2) | (mask_p[31] << 0); 814 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 815 OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 816 817 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 818 | (mask_p[59] << 26) | (mask_p[58] << 24) 819 | (mask_p[57] << 22) | (mask_p[56] << 20) 820 | (mask_p[55] << 18) | (mask_p[54] << 16) 821 | (mask_p[53] << 14) | (mask_p[52] << 12) 822 | (mask_p[51] << 10) | (mask_p[50] << 8) 823 | (mask_p[49] << 6) | (mask_p[48] << 4) 824 | (mask_p[47] << 2) | (mask_p[46] << 0); 825 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 826 OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 827 828 OS_REG_WRITE_BUFFER_FLUSH(ah); 829 OS_REG_WRITE_BUFFER_DISABLE(ah); 830 } 831 832 /* 833 * Fill all software cached or static hardware state information. 834 * Return failure if capabilities are to come from EEPROM and 835 * cannot be read. 836 */ 837 HAL_BOOL 838 ar5416FillCapabilityInfo(struct ath_hal *ah) 839 { 840 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 841 HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 842 uint16_t val; 843 844 /* Construct wireless mode from EEPROM */ 845 pCap->halWirelessModes = 0; 846 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) { 847 pCap->halWirelessModes |= HAL_MODE_11A 848 | HAL_MODE_11NA_HT20 849 | HAL_MODE_11NA_HT40PLUS 850 | HAL_MODE_11NA_HT40MINUS 851 ; 852 } 853 if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE)) { 854 pCap->halWirelessModes |= HAL_MODE_11G 855 | HAL_MODE_11NG_HT20 856 | HAL_MODE_11NG_HT40PLUS 857 | HAL_MODE_11NG_HT40MINUS 858 ; 859 pCap->halWirelessModes |= HAL_MODE_11A 860 | HAL_MODE_11NA_HT20 861 | HAL_MODE_11NA_HT40PLUS 862 | HAL_MODE_11NA_HT40MINUS 863 ; 864 } 865 866 pCap->halLow2GhzChan = 2312; 867 pCap->halHigh2GhzChan = 2732; 868 869 pCap->halLow5GhzChan = 4915; 870 pCap->halHigh5GhzChan = 6100; 871 872 pCap->halCipherCkipSupport = AH_FALSE; 873 pCap->halCipherTkipSupport = AH_TRUE; 874 pCap->halCipherAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 875 876 pCap->halMicCkipSupport = AH_FALSE; 877 pCap->halMicTkipSupport = AH_TRUE; 878 pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 879 /* 880 * Starting with Griffin TX+RX mic keys can be combined 881 * in one key cache slot. 882 */ 883 pCap->halTkipMicTxRxKeySupport = AH_TRUE; 884 pCap->halChanSpreadSupport = AH_TRUE; 885 pCap->halSleepAfterBeaconBroken = AH_TRUE; 886 887 pCap->halCompressSupport = AH_FALSE; 888 pCap->halBurstSupport = AH_TRUE; 889 pCap->halFastFramesSupport = AH_FALSE; /* XXX? */ 890 pCap->halChapTuningSupport = AH_TRUE; 891 pCap->halTurboPrimeSupport = AH_TRUE; 892 893 pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G; 894 895 pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */ 896 pCap->halNumMRRetries = 4; /* Hardware supports 4 MRR */ 897 pCap->halNumTxMaps = 1; /* Single TX ptr per descr */ 898 pCap->halVEOLSupport = AH_TRUE; 899 pCap->halBssIdMaskSupport = AH_TRUE; 900 pCap->halMcastKeySrchSupport = AH_TRUE; /* Works on AR5416 and later */ 901 pCap->halTsfAddSupport = AH_TRUE; 902 pCap->hal4AddrAggrSupport = AH_FALSE; /* Broken in Owl */ 903 904 if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK) 905 pCap->halTotalQueues = val; 906 else 907 pCap->halTotalQueues = HAL_NUM_TX_QUEUES; 908 909 if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK) 910 pCap->halKeyCacheSize = val; 911 else 912 pCap->halKeyCacheSize = AR5416_KEYTABLE_SIZE; 913 914 /* XXX Which chips? */ 915 pCap->halChanHalfRate = AH_TRUE; 916 pCap->halChanQuarterRate = AH_TRUE; 917 918 pCap->halTstampPrecision = 32; 919 pCap->halHwPhyCounterSupport = AH_TRUE; 920 pCap->halIntrMask = HAL_INT_COMMON 921 | HAL_INT_RX 922 | HAL_INT_TX 923 | HAL_INT_FATAL 924 | HAL_INT_BNR 925 | HAL_INT_BMISC 926 | HAL_INT_DTIMSYNC 927 | HAL_INT_TSFOOR 928 | HAL_INT_CST 929 | HAL_INT_GTT 930 ; 931 932 pCap->halFastCCSupport = AH_TRUE; 933 pCap->halNumGpioPins = 14; 934 pCap->halWowSupport = AH_FALSE; 935 pCap->halWowMatchPatternExact = AH_FALSE; 936 pCap->halBtCoexSupport = AH_FALSE; /* XXX need support */ 937 pCap->halAutoSleepSupport = AH_FALSE; 938 pCap->hal4kbSplitTransSupport = AH_TRUE; 939 /* Disable this so Block-ACK works correctly */ 940 pCap->halHasRxSelfLinkedTail = AH_FALSE; 941 #if 0 /* XXX not yet */ 942 pCap->halNumAntCfg2GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_2GHZ); 943 pCap->halNumAntCfg5GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_5GHZ); 944 #endif 945 pCap->halHTSupport = AH_TRUE; 946 pCap->halTxChainMask = ath_hal_eepromGet(ah, AR_EEP_TXMASK, AH_NULL); 947 /* XXX CB71 uses GPIO 0 to indicate 3 rx chains */ 948 pCap->halRxChainMask = ath_hal_eepromGet(ah, AR_EEP_RXMASK, AH_NULL); 949 /* AR5416 may have 3 antennas but is a 2x2 stream device */ 950 pCap->halTxStreams = 2; 951 pCap->halRxStreams = 2; 952 953 /* 954 * If the TX or RX chainmask has less than 2 chains active, 955 * mark it as a 1-stream device for the relevant stream. 956 */ 957 if (owl_get_ntxchains(pCap->halTxChainMask) == 1) 958 pCap->halTxStreams = 1; 959 /* XXX Eww */ 960 if (owl_get_ntxchains(pCap->halRxChainMask) == 1) 961 pCap->halRxStreams = 1; 962 pCap->halRtsAggrLimit = 8*1024; /* Owl 2.0 limit */ 963 pCap->halMbssidAggrSupport = AH_FALSE; /* Broken on Owl */ 964 pCap->halForcePpmSupport = AH_TRUE; 965 pCap->halEnhancedPmSupport = AH_TRUE; 966 pCap->halBssidMatchSupport = AH_TRUE; 967 pCap->halGTTSupport = AH_TRUE; 968 pCap->halCSTSupport = AH_TRUE; 969 pCap->halEnhancedDfsSupport = AH_FALSE; 970 /* Hardware supports 32 bit TSF values in the RX descriptor */ 971 pCap->halHasLongRxDescTsf = AH_TRUE; 972 /* 973 * BB Read WAR: this is only for AR5008/AR9001 NICs 974 * It is also set individually in the AR91xx attach functions. 975 */ 976 if (AR_SREV_OWL(ah)) 977 pCap->halHasBBReadWar = AH_TRUE; 978 979 if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) && 980 ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) { 981 /* NB: enabled by default */ 982 ahpriv->ah_rfkillEnabled = AH_TRUE; 983 pCap->halRfSilentSupport = AH_TRUE; 984 } 985 986 /* 987 * The MAC will mark frames as RXed if there's a descriptor 988 * to write them to. So if it hits a self-linked final descriptor, 989 * it'll keep ACKing frames even though they're being silently 990 * dropped. Thus, this particular feature of the driver can't 991 * be used for 802.11n devices. 992 */ 993 ahpriv->ah_rxornIsFatal = AH_FALSE; 994 995 /* 996 * If it's a PCI NIC, ask the HAL OS layer to serialise 997 * register access, or SMP machines may cause the hardware 998 * to hang. This is applicable to AR5416 and AR9220; I'm not 999 * sure about AR9160 or AR9227. 1000 */ 1001 if (! AH_PRIVATE(ah)->ah_ispcie) 1002 pCap->halSerialiseRegWar = 1; 1003 1004 return AH_TRUE; 1005 } 1006 1007 static const char* 1008 ar5416Probe(uint16_t vendorid, uint16_t devid) 1009 { 1010 if (vendorid == ATHEROS_VENDOR_ID) { 1011 if (devid == AR5416_DEVID_PCI) 1012 return "Atheros 5416"; 1013 if (devid == AR5416_DEVID_PCIE) 1014 return "Atheros 5418"; 1015 } 1016 return AH_NULL; 1017 } 1018 AH_CHIP(AR5416, ar5416Probe, ar5416Attach); 1019