1 /* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19 #include "opt_ah.h" 20 21 #include "ah.h" 22 #include "ah_internal.h" 23 #include "ah_devid.h" 24 25 #include "ah_eeprom_v14.h" 26 27 #include "ar5416/ar5416.h" 28 #include "ar5416/ar5416reg.h" 29 #include "ar5416/ar5416phy.h" 30 31 #include "ar5416/ar5416.ini" 32 33 static void ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, 34 HAL_BOOL power_off); 35 static void ar5416DisablePCIE(struct ath_hal *ah); 36 static void ar5416WriteIni(struct ath_hal *ah, 37 const struct ieee80211_channel *chan); 38 static void ar5416SpurMitigate(struct ath_hal *ah, 39 const struct ieee80211_channel *chan); 40 41 static void 42 ar5416AniSetup(struct ath_hal *ah) 43 { 44 static const struct ar5212AniParams aniparams = { 45 .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 46 .totalSizeDesired = { -55, -55, -55, -55, -62 }, 47 .coarseHigh = { -14, -14, -14, -14, -12 }, 48 .coarseLow = { -64, -64, -64, -64, -70 }, 49 .firpwr = { -78, -78, -78, -78, -80 }, 50 .maxSpurImmunityLevel = 7, 51 .cycPwrThr1 = { 2, 4, 6, 8, 10, 12, 14, 16 }, 52 .maxFirstepLevel = 2, /* levels 0..2 */ 53 .firstep = { 0, 4, 8 }, 54 .ofdmTrigHigh = 500, 55 .ofdmTrigLow = 200, 56 .cckTrigHigh = 200, 57 .cckTrigLow = 100, 58 .rssiThrHigh = 40, 59 .rssiThrLow = 7, 60 .period = 100, 61 }; 62 /* NB: disable ANI noise immmunity for reliable RIFS rx */ 63 AH5416(ah)->ah_ani_function &= ~(1 << HAL_ANI_NOISE_IMMUNITY_LEVEL); 64 ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE); 65 } 66 67 /* 68 * AR5416 doesn't do OLC or temperature compensation. 69 */ 70 static void 71 ar5416olcInit(struct ath_hal *ah) 72 { 73 } 74 75 static void 76 ar5416olcTempCompensation(struct ath_hal *ah) 77 { 78 } 79 80 /* 81 * Attach for an AR5416 part. 82 */ 83 void 84 ar5416InitState(struct ath_hal_5416 *ahp5416, uint16_t devid, HAL_SOFTC sc, 85 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status) 86 { 87 struct ath_hal_5212 *ahp; 88 struct ath_hal *ah; 89 90 ahp = &ahp5416->ah_5212; 91 ar5212InitState(ahp, devid, sc, st, sh, status); 92 ah = &ahp->ah_priv.h; 93 94 /* override 5212 methods for our needs */ 95 ah->ah_magic = AR5416_MAGIC; 96 ah->ah_getRateTable = ar5416GetRateTable; 97 ah->ah_detach = ar5416Detach; 98 99 /* Reset functions */ 100 ah->ah_reset = ar5416Reset; 101 ah->ah_phyDisable = ar5416PhyDisable; 102 ah->ah_disable = ar5416Disable; 103 ah->ah_configPCIE = ar5416ConfigPCIE; 104 ah->ah_disablePCIE = ar5416DisablePCIE; 105 ah->ah_perCalibration = ar5416PerCalibration; 106 ah->ah_perCalibrationN = ar5416PerCalibrationN, 107 ah->ah_resetCalValid = ar5416ResetCalValid, 108 ah->ah_setTxPowerLimit = ar5416SetTxPowerLimit; 109 ah->ah_setTxPower = ar5416SetTransmitPower; 110 ah->ah_setBoardValues = ar5416SetBoardValues; 111 112 /* Transmit functions */ 113 ah->ah_stopTxDma = ar5416StopTxDma; 114 ah->ah_setupTxDesc = ar5416SetupTxDesc; 115 ah->ah_setupXTxDesc = ar5416SetupXTxDesc; 116 ah->ah_fillTxDesc = ar5416FillTxDesc; 117 ah->ah_procTxDesc = ar5416ProcTxDesc; 118 ah->ah_getTxCompletionRates = ar5416GetTxCompletionRates; 119 ah->ah_setupTxQueue = ar5416SetupTxQueue; 120 ah->ah_resetTxQueue = ar5416ResetTxQueue; 121 122 /* Receive Functions */ 123 ah->ah_getRxFilter = ar5416GetRxFilter; 124 ah->ah_setRxFilter = ar5416SetRxFilter; 125 ah->ah_stopDmaReceive = ar5416StopDmaReceive; 126 ah->ah_startPcuReceive = ar5416StartPcuReceive; 127 ah->ah_stopPcuReceive = ar5416StopPcuReceive; 128 ah->ah_setupRxDesc = ar5416SetupRxDesc; 129 ah->ah_procRxDesc = ar5416ProcRxDesc; 130 ah->ah_rxMonitor = ar5416RxMonitor; 131 ah->ah_aniPoll = ar5416AniPoll; 132 ah->ah_procMibEvent = ar5416ProcessMibIntr; 133 134 /* Misc Functions */ 135 ah->ah_getCapability = ar5416GetCapability; 136 ah->ah_setCapability = ar5416SetCapability; 137 ah->ah_getDiagState = ar5416GetDiagState; 138 ah->ah_setLedState = ar5416SetLedState; 139 ah->ah_gpioCfgOutput = ar5416GpioCfgOutput; 140 ah->ah_gpioCfgInput = ar5416GpioCfgInput; 141 ah->ah_gpioGet = ar5416GpioGet; 142 ah->ah_gpioSet = ar5416GpioSet; 143 ah->ah_gpioSetIntr = ar5416GpioSetIntr; 144 ah->ah_getTsf64 = ar5416GetTsf64; 145 ah->ah_setTsf64 = ar5416SetTsf64; 146 ah->ah_resetTsf = ar5416ResetTsf; 147 ah->ah_getRfGain = ar5416GetRfgain; 148 ah->ah_setAntennaSwitch = ar5416SetAntennaSwitch; 149 ah->ah_setDecompMask = ar5416SetDecompMask; 150 ah->ah_setCoverageClass = ar5416SetCoverageClass; 151 ah->ah_setQuiet = ar5416SetQuiet; 152 ah->ah_getMibCycleCounts = ar5416GetMibCycleCounts; 153 154 ah->ah_resetKeyCacheEntry = ar5416ResetKeyCacheEntry; 155 ah->ah_setKeyCacheEntry = ar5416SetKeyCacheEntry; 156 157 /* DFS Functions */ 158 ah->ah_enableDfs = ar5416EnableDfs; 159 ah->ah_getDfsThresh = ar5416GetDfsThresh; 160 ah->ah_getDfsDefaultThresh = ar5416GetDfsDefaultThresh; 161 ah->ah_procRadarEvent = ar5416ProcessRadarEvent; 162 ah->ah_isFastClockEnabled = ar5416IsFastClockEnabled; 163 164 /* Spectral Scan Functions */ 165 ah->ah_spectralConfigure = ar5416ConfigureSpectralScan; 166 ah->ah_spectralGetConfig = ar5416GetSpectralParams; 167 ah->ah_spectralStart = ar5416StartSpectralScan; 168 ah->ah_spectralStop = ar5416StopSpectralScan; 169 ah->ah_spectralIsEnabled = ar5416IsSpectralEnabled; 170 ah->ah_spectralIsActive = ar5416IsSpectralActive; 171 172 /* Power Management Functions */ 173 ah->ah_setPowerMode = ar5416SetPowerMode; 174 175 /* Beacon Management Functions */ 176 ah->ah_setBeaconTimers = ar5416SetBeaconTimers; 177 ah->ah_beaconInit = ar5416BeaconInit; 178 ah->ah_setStationBeaconTimers = ar5416SetStaBeaconTimers; 179 ah->ah_resetStationBeaconTimers = ar5416ResetStaBeaconTimers; 180 ah->ah_getNextTBTT = ar5416GetNextTBTT; 181 182 /* 802.11n Functions */ 183 ah->ah_chainTxDesc = ar5416ChainTxDesc; 184 ah->ah_setupFirstTxDesc = ar5416SetupFirstTxDesc; 185 ah->ah_setupLastTxDesc = ar5416SetupLastTxDesc; 186 ah->ah_set11nRateScenario = ar5416Set11nRateScenario; 187 ah->ah_set11nAggrFirst = ar5416Set11nAggrFirst; 188 ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle; 189 ah->ah_set11nAggrLast = ar5416Set11nAggrLast; 190 ah->ah_clr11nAggr = ar5416Clr11nAggr; 191 ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration; 192 ah->ah_get11nExtBusy = ar5416Get11nExtBusy; 193 ah->ah_set11nMac2040 = ar5416Set11nMac2040; 194 ah->ah_get11nRxClear = ar5416Get11nRxClear; 195 ah->ah_set11nRxClear = ar5416Set11nRxClear; 196 197 /* Interrupt functions */ 198 ah->ah_isInterruptPending = ar5416IsInterruptPending; 199 ah->ah_getPendingInterrupts = ar5416GetPendingInterrupts; 200 ah->ah_setInterrupts = ar5416SetInterrupts; 201 202 /* Bluetooth Coexistence functions */ 203 ah->ah_btCoexSetInfo = ar5416SetBTCoexInfo; 204 ah->ah_btCoexSetConfig = ar5416BTCoexConfig; 205 ah->ah_btCoexSetQcuThresh = ar5416BTCoexSetQcuThresh; 206 ah->ah_btCoexSetWeights = ar5416BTCoexSetWeights; 207 ah->ah_btCoexSetBmissThresh = ar5416BTCoexSetupBmissThresh; 208 ah->ah_btcoexSetParameter = ar5416BTCoexSetParameter; 209 ah->ah_btCoexDisable = ar5416BTCoexDisable; 210 ah->ah_btCoexEnable = ar5416BTCoexEnable; 211 AH5416(ah)->ah_btCoexSetDiversity = ar5416BTCoexAntennaDiversity; 212 213 ahp->ah_priv.ah_getWirelessModes= ar5416GetWirelessModes; 214 ahp->ah_priv.ah_eepromRead = ar5416EepromRead; 215 #ifdef AH_SUPPORT_WRITE_EEPROM 216 ahp->ah_priv.ah_eepromWrite = ar5416EepromWrite; 217 #endif 218 ahp->ah_priv.ah_getChipPowerLimits = ar5416GetChipPowerLimits; 219 220 /* Internal ops */ 221 AH5416(ah)->ah_writeIni = ar5416WriteIni; 222 AH5416(ah)->ah_spurMitigate = ar5416SpurMitigate; 223 224 /* Internal baseband ops */ 225 AH5416(ah)->ah_initPLL = ar5416InitPLL; 226 227 /* Internal calibration ops */ 228 AH5416(ah)->ah_cal_initcal = ar5416InitCalHardware; 229 230 /* Internal TX power control related operations */ 231 AH5416(ah)->ah_olcInit = ar5416olcInit; 232 AH5416(ah)->ah_olcTempCompensation = ar5416olcTempCompensation; 233 AH5416(ah)->ah_setPowerCalTable = ar5416SetPowerCalTable; 234 235 /* 236 * Start by setting all Owl devices to 2x2 237 */ 238 AH5416(ah)->ah_rx_chainmask = AR5416_DEFAULT_RXCHAINMASK; 239 AH5416(ah)->ah_tx_chainmask = AR5416_DEFAULT_TXCHAINMASK; 240 241 /* Enable all ANI functions to begin with */ 242 AH5416(ah)->ah_ani_function = 0xffffffff; 243 244 /* Set overridable ANI methods */ 245 AH5212(ah)->ah_aniControl = ar5416AniControl; 246 } 247 248 uint32_t 249 ar5416GetRadioRev(struct ath_hal *ah) 250 { 251 uint32_t val; 252 int i; 253 254 /* Read Radio Chip Rev Extract */ 255 OS_REG_WRITE(ah, AR_PHY(0x36), 0x00007058); 256 for (i = 0; i < 8; i++) 257 OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000); 258 val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; 259 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 260 return ath_hal_reverseBits(val, 8); 261 } 262 263 /* 264 * Attach for an AR5416 part. 265 */ 266 static struct ath_hal * 267 ar5416Attach(uint16_t devid, HAL_SOFTC sc, 268 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 269 HAL_STATUS *status) 270 { 271 struct ath_hal_5416 *ahp5416; 272 struct ath_hal_5212 *ahp; 273 struct ath_hal *ah; 274 uint32_t val; 275 HAL_STATUS ecode; 276 HAL_BOOL rfStatus; 277 278 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 279 __func__, sc, (void*) st, (void*) sh); 280 281 /* NB: memory is returned zero'd */ 282 ahp5416 = ath_hal_malloc(sizeof (struct ath_hal_5416) + 283 /* extra space for Owl 2.1/2.2 WAR */ 284 sizeof(ar5416Addac) 285 ); 286 if (ahp5416 == AH_NULL) { 287 HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 288 "%s: cannot allocate memory for state block\n", __func__); 289 *status = HAL_ENOMEM; 290 return AH_NULL; 291 } 292 ar5416InitState(ahp5416, devid, sc, st, sh, status); 293 ahp = &ahp5416->ah_5212; 294 ah = &ahp->ah_priv.h; 295 296 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { 297 /* reset chip */ 298 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", __func__); 299 ecode = HAL_EIO; 300 goto bad; 301 } 302 303 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 304 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", __func__); 305 ecode = HAL_EIO; 306 goto bad; 307 } 308 /* Read Revisions from Chips before taking out of reset */ 309 val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID; 310 AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S; 311 AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION; 312 AH_PRIVATE(ah)->ah_ispcie = (devid == AR5416_DEVID_PCIE); 313 314 /* setup common ini data; rf backends handle remainder */ 315 HAL_INI_INIT(&ahp->ah_ini_modes, ar5416Modes, 6); 316 HAL_INI_INIT(&ahp->ah_ini_common, ar5416Common, 2); 317 318 HAL_INI_INIT(&AH5416(ah)->ah_ini_bb_rfgain, ar5416BB_RfGain, 3); 319 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank0, ar5416Bank0, 2); 320 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank1, ar5416Bank1, 2); 321 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank2, ar5416Bank2, 2); 322 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank3, ar5416Bank3, 3); 323 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank6, ar5416Bank6, 3); 324 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank7, ar5416Bank7, 2); 325 HAL_INI_INIT(&AH5416(ah)->ah_ini_addac, ar5416Addac, 2); 326 327 if (! IS_5416V2_2(ah)) { /* Owl 2.1/2.0 */ 328 ath_hal_printf(ah, "[ath] Enabling CLKDRV workaround for AR5416 < v2.2\n"); 329 struct ini { 330 uint32_t *data; /* NB: !const */ 331 int rows, cols; 332 }; 333 /* override CLKDRV value */ 334 OS_MEMCPY(&AH5416(ah)[1], ar5416Addac, sizeof(ar5416Addac)); 335 AH5416(ah)->ah_ini_addac.data = (uint32_t *) &AH5416(ah)[1]; 336 HAL_INI_VAL((struct ini *)&AH5416(ah)->ah_ini_addac, 31, 1) = 0; 337 } 338 339 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, ar5416PciePhy, 2); 340 ar5416AttachPCIE(ah); 341 342 ecode = ath_hal_v14EepromAttach(ah); 343 if (ecode != HAL_OK) 344 goto bad; 345 346 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */ 347 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", 348 __func__); 349 ecode = HAL_EIO; 350 goto bad; 351 } 352 353 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 354 355 if (!ar5212ChipTest(ah)) { 356 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 357 __func__); 358 ecode = HAL_ESELFTEST; 359 goto bad; 360 } 361 362 /* 363 * Set correct Baseband to analog shift 364 * setting to access analog chips. 365 */ 366 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 367 368 /* Read Radio Chip Rev Extract */ 369 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah); 370 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 371 case AR_RAD5122_SREV_MAJOR: /* Fowl: 5G/2x2 */ 372 case AR_RAD2122_SREV_MAJOR: /* Fowl: 2+5G/2x2 */ 373 case AR_RAD2133_SREV_MAJOR: /* Fowl: 2G/3x3 */ 374 case AR_RAD5133_SREV_MAJOR: /* Fowl: 2+5G/3x3 */ 375 break; 376 default: 377 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 378 /* 379 * When RF_Silen is used the analog chip is reset. 380 * So when the system boots with radio switch off 381 * the RF chip rev reads back as zero and we need 382 * to use the mac+phy revs to set the radio rev. 383 */ 384 AH_PRIVATE(ah)->ah_analog5GhzRev = 385 AR_RAD5133_SREV_MAJOR; 386 break; 387 } 388 /* NB: silently accept anything in release code per Atheros */ 389 #ifdef AH_DEBUG 390 HALDEBUG(ah, HAL_DEBUG_ANY, 391 "%s: 5G Radio Chip Rev 0x%02X is not supported by " 392 "this driver\n", __func__, 393 AH_PRIVATE(ah)->ah_analog5GhzRev); 394 ecode = HAL_ENOTSUPP; 395 goto bad; 396 #endif 397 } 398 399 /* 400 * Got everything we need now to setup the capabilities. 401 */ 402 if (!ar5416FillCapabilityInfo(ah)) { 403 ecode = HAL_EEREAD; 404 goto bad; 405 } 406 407 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 408 if (ecode != HAL_OK) { 409 HALDEBUG(ah, HAL_DEBUG_ANY, 410 "%s: error getting mac address from EEPROM\n", __func__); 411 goto bad; 412 } 413 /* XXX How about the serial number ? */ 414 /* Read Reg Domain */ 415 AH_PRIVATE(ah)->ah_currentRD = 416 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL); 417 AH_PRIVATE(ah)->ah_currentRDext = 418 ath_hal_eepromGet(ah, AR_EEP_REGDMN_1, AH_NULL); 419 420 /* 421 * ah_miscMode is populated by ar5416FillCapabilityInfo() 422 * starting from griffin. Set here to make sure that 423 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is 424 * placed into hardware. 425 */ 426 if (ahp->ah_miscMode != 0) 427 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode); 428 429 rfStatus = ar2133RfAttach(ah, &ecode); 430 if (!rfStatus) { 431 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 432 __func__, ecode); 433 goto bad; 434 } 435 436 ar5416AniSetup(ah); /* Anti Noise Immunity */ 437 438 AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ; 439 AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ; 440 AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ; 441 AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ; 442 AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ; 443 AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ; 444 445 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist); 446 447 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 448 449 return ah; 450 bad: 451 if (ahp) 452 ar5416Detach((struct ath_hal *) ahp); 453 if (status) 454 *status = ecode; 455 return AH_NULL; 456 } 457 458 void 459 ar5416Detach(struct ath_hal *ah) 460 { 461 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__); 462 463 HALASSERT(ah != AH_NULL); 464 HALASSERT(ah->ah_magic == AR5416_MAGIC); 465 466 /* Make sure that chip is awake before writing to it */ 467 if (! ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 468 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, 469 "%s: failed to wake up chip\n", 470 __func__); 471 472 ar5416AniDetach(ah); 473 ar5212RfDetach(ah); 474 ah->ah_disable(ah); 475 ar5416SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); 476 ath_hal_eepromDetach(ah); 477 ath_hal_free(ah); 478 } 479 480 void 481 ar5416AttachPCIE(struct ath_hal *ah) 482 { 483 if (AH_PRIVATE(ah)->ah_ispcie) 484 ath_hal_configPCIE(ah, AH_FALSE, AH_FALSE); 485 else 486 ath_hal_disablePCIE(ah); 487 } 488 489 static void 490 ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off) 491 { 492 493 /* This is only applicable for AR5418 (AR5416 PCIe) */ 494 if (! AH_PRIVATE(ah)->ah_ispcie) 495 return; 496 497 if (! restore) { 498 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0); 499 OS_DELAY(1000); 500 } 501 502 if (power_off) { /* Power-off */ 503 /* clear bit 19 to disable L1 */ 504 OS_REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 505 } else { /* Power-on */ 506 /* Set default WAR values for Owl */ 507 OS_REG_WRITE(ah, AR_WA, AR_WA_DEFAULT); 508 509 /* set bit 19 to allow forcing of pcie core into L1 state */ 510 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 511 } 512 } 513 514 /* 515 * Disable PCIe PHY if PCIe isn't used. 516 */ 517 static void 518 ar5416DisablePCIE(struct ath_hal *ah) 519 { 520 521 /* PCIe? Don't */ 522 if (AH_PRIVATE(ah)->ah_ispcie) 523 return; 524 525 /* .. Only applicable for AR5416v2 or later */ 526 if (! (AR_SREV_OWL(ah) && AR_SREV_OWL_20_OR_LATER(ah))) 527 return; 528 529 OS_REG_WRITE_BUFFER_ENABLE(ah); 530 531 /* 532 * Disable the PCIe PHY. 533 */ 534 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 535 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 536 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 537 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); 538 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); 539 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); 540 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 541 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 542 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 543 544 /* Load the new settings */ 545 OS_REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 546 547 OS_REG_WRITE_BUFFER_FLUSH(ah); 548 OS_REG_WRITE_BUFFER_DISABLE(ah); 549 } 550 551 static void 552 ar5416WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan) 553 { 554 u_int modesIndex, freqIndex; 555 int regWrites = 0; 556 557 /* Setup the indices for the next set of register array writes */ 558 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */ 559 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 560 freqIndex = 2; 561 if (IEEE80211_IS_CHAN_HT40(chan)) 562 modesIndex = 3; 563 else if (IEEE80211_IS_CHAN_108G(chan)) 564 modesIndex = 5; 565 else 566 modesIndex = 4; 567 } else { 568 freqIndex = 1; 569 if (IEEE80211_IS_CHAN_HT40(chan) || 570 IEEE80211_IS_CHAN_TURBO(chan)) 571 modesIndex = 2; 572 else 573 modesIndex = 1; 574 } 575 576 /* Set correct Baseband to analog shift setting to access analog chips. */ 577 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 578 579 /* 580 * Write addac shifts 581 */ 582 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); 583 584 /* NB: only required for Sowl */ 585 if (AR_SREV_SOWL(ah)) 586 ar5416EepromSetAddac(ah, chan); 587 588 regWrites = ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_addac, 1, 589 regWrites); 590 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 591 592 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, 593 modesIndex, regWrites); 594 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 595 1, regWrites); 596 597 /* XXX updated regWrites? */ 598 AH5212(ah)->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites); 599 } 600 601 /* 602 * Convert to baseband spur frequency given input channel frequency 603 * and compute register settings below. 604 */ 605 606 static void 607 ar5416SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan) 608 { 609 uint16_t freq = ath_hal_gethwchannel(ah, chan); 610 static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, 611 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 }; 612 static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, 613 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 }; 614 static const int inc[4] = { 0, 100, 0, 0 }; 615 616 int bb_spur = AR_NO_SPUR; 617 int bin, cur_bin; 618 int spur_freq_sd; 619 int spur_delta_phase; 620 int denominator; 621 int upper, lower, cur_vit_mask; 622 int tmp, new; 623 int i; 624 625 int8_t mask_m[123]; 626 int8_t mask_p[123]; 627 int8_t mask_amt; 628 int tmp_mask; 629 int cur_bb_spur; 630 HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 631 632 OS_MEMZERO(mask_m, sizeof(mask_m)); 633 OS_MEMZERO(mask_p, sizeof(mask_p)); 634 635 /* 636 * Need to verify range +/- 9.5 for static ht20, otherwise spur 637 * is out-of-band and can be ignored. 638 */ 639 /* XXX ath9k changes */ 640 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { 641 cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz); 642 if (AR_NO_SPUR == cur_bb_spur) 643 break; 644 cur_bb_spur = cur_bb_spur - (freq * 10); 645 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) { 646 bb_spur = cur_bb_spur; 647 break; 648 } 649 } 650 if (AR_NO_SPUR == bb_spur) 651 return; 652 653 bin = bb_spur * 32; 654 655 tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)); 656 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 657 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 658 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 659 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 660 661 OS_REG_WRITE_BUFFER_ENABLE(ah); 662 663 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), new); 664 665 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 666 AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 667 AR_PHY_SPUR_REG_MASK_RATE_SELECT | 668 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 669 SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 670 OS_REG_WRITE(ah, AR_PHY_SPUR_REG, new); 671 /* 672 * Should offset bb_spur by +/- 10 MHz for dynamic 2040 MHz 673 * config, no offset for HT20. 674 * spur_delta_phase = bb_spur/40 * 2**21 for static ht20, 675 * /80 for dyn2040. 676 */ 677 spur_delta_phase = ((bb_spur * 524288) / 100) & 678 AR_PHY_TIMING11_SPUR_DELTA_PHASE; 679 /* 680 * in 11A mode the denominator of spur_freq_sd should be 40 and 681 * it should be 44 in 11G 682 */ 683 denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 440 : 400; 684 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff; 685 686 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 687 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 688 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 689 OS_REG_WRITE(ah, AR_PHY_TIMING11, new); 690 691 692 /* 693 * ============================================ 694 * pilot mask 1 [31:0] = +6..-26, no 0 bin 695 * pilot mask 2 [19:0] = +26..+7 696 * 697 * channel mask 1 [31:0] = +6..-26, no 0 bin 698 * channel mask 2 [19:0] = +26..+7 699 */ 700 //cur_bin = -26; 701 cur_bin = -6000; 702 upper = bin + 100; 703 lower = bin - 100; 704 705 for (i = 0; i < 4; i++) { 706 int pilot_mask = 0; 707 int chan_mask = 0; 708 int bp = 0; 709 for (bp = 0; bp < 30; bp++) { 710 if ((cur_bin > lower) && (cur_bin < upper)) { 711 pilot_mask = pilot_mask | 0x1 << bp; 712 chan_mask = chan_mask | 0x1 << bp; 713 } 714 cur_bin += 100; 715 } 716 cur_bin += inc[i]; 717 OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 718 OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask); 719 } 720 721 /* ================================================= 722 * viterbi mask 1 based on channel magnitude 723 * four levels 0-3 724 * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c) 725 * [1 2 2 1] for -9.6 or [1 2 1] for +16 726 * - enable_mask_ppm, all bins move with freq 727 * 728 * - mask_select, 8 bits for rates (reg 67,0x990c) 729 * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c) 730 * choose which mask to use mask or mask2 731 */ 732 733 /* 734 * viterbi mask 2 2nd set for per data rate puncturing 735 * four levels 0-3 736 * - mask_select, 8 bits for rates (reg 67) 737 * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994) 738 * [1 2 2 1] for -9.6 or [1 2 1] for +16 739 */ 740 cur_vit_mask = 6100; 741 upper = bin + 120; 742 lower = bin - 120; 743 744 for (i = 0; i < 123; i++) { 745 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 746 if ((abs(cur_vit_mask - bin)) < 75) { 747 mask_amt = 1; 748 } else { 749 mask_amt = 0; 750 } 751 if (cur_vit_mask < 0) { 752 mask_m[abs(cur_vit_mask / 100)] = mask_amt; 753 } else { 754 mask_p[cur_vit_mask / 100] = mask_amt; 755 } 756 } 757 cur_vit_mask -= 100; 758 } 759 760 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 761 | (mask_m[48] << 26) | (mask_m[49] << 24) 762 | (mask_m[50] << 22) | (mask_m[51] << 20) 763 | (mask_m[52] << 18) | (mask_m[53] << 16) 764 | (mask_m[54] << 14) | (mask_m[55] << 12) 765 | (mask_m[56] << 10) | (mask_m[57] << 8) 766 | (mask_m[58] << 6) | (mask_m[59] << 4) 767 | (mask_m[60] << 2) | (mask_m[61] << 0); 768 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 769 OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 770 771 tmp_mask = (mask_m[31] << 28) 772 | (mask_m[32] << 26) | (mask_m[33] << 24) 773 | (mask_m[34] << 22) | (mask_m[35] << 20) 774 | (mask_m[36] << 18) | (mask_m[37] << 16) 775 | (mask_m[48] << 14) | (mask_m[39] << 12) 776 | (mask_m[40] << 10) | (mask_m[41] << 8) 777 | (mask_m[42] << 6) | (mask_m[43] << 4) 778 | (mask_m[44] << 2) | (mask_m[45] << 0); 779 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 780 OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 781 782 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 783 | (mask_m[18] << 26) | (mask_m[18] << 24) 784 | (mask_m[20] << 22) | (mask_m[20] << 20) 785 | (mask_m[22] << 18) | (mask_m[22] << 16) 786 | (mask_m[24] << 14) | (mask_m[24] << 12) 787 | (mask_m[25] << 10) | (mask_m[26] << 8) 788 | (mask_m[27] << 6) | (mask_m[28] << 4) 789 | (mask_m[29] << 2) | (mask_m[30] << 0); 790 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 791 OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 792 793 tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28) 794 | (mask_m[ 2] << 26) | (mask_m[ 3] << 24) 795 | (mask_m[ 4] << 22) | (mask_m[ 5] << 20) 796 | (mask_m[ 6] << 18) | (mask_m[ 7] << 16) 797 | (mask_m[ 8] << 14) | (mask_m[ 9] << 12) 798 | (mask_m[10] << 10) | (mask_m[11] << 8) 799 | (mask_m[12] << 6) | (mask_m[13] << 4) 800 | (mask_m[14] << 2) | (mask_m[15] << 0); 801 OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 802 OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 803 804 tmp_mask = (mask_p[15] << 28) 805 | (mask_p[14] << 26) | (mask_p[13] << 24) 806 | (mask_p[12] << 22) | (mask_p[11] << 20) 807 | (mask_p[10] << 18) | (mask_p[ 9] << 16) 808 | (mask_p[ 8] << 14) | (mask_p[ 7] << 12) 809 | (mask_p[ 6] << 10) | (mask_p[ 5] << 8) 810 | (mask_p[ 4] << 6) | (mask_p[ 3] << 4) 811 | (mask_p[ 2] << 2) | (mask_p[ 1] << 0); 812 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 813 OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 814 815 tmp_mask = (mask_p[30] << 28) 816 | (mask_p[29] << 26) | (mask_p[28] << 24) 817 | (mask_p[27] << 22) | (mask_p[26] << 20) 818 | (mask_p[25] << 18) | (mask_p[24] << 16) 819 | (mask_p[23] << 14) | (mask_p[22] << 12) 820 | (mask_p[21] << 10) | (mask_p[20] << 8) 821 | (mask_p[19] << 6) | (mask_p[18] << 4) 822 | (mask_p[17] << 2) | (mask_p[16] << 0); 823 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 824 OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 825 826 tmp_mask = (mask_p[45] << 28) 827 | (mask_p[44] << 26) | (mask_p[43] << 24) 828 | (mask_p[42] << 22) | (mask_p[41] << 20) 829 | (mask_p[40] << 18) | (mask_p[39] << 16) 830 | (mask_p[38] << 14) | (mask_p[37] << 12) 831 | (mask_p[36] << 10) | (mask_p[35] << 8) 832 | (mask_p[34] << 6) | (mask_p[33] << 4) 833 | (mask_p[32] << 2) | (mask_p[31] << 0); 834 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 835 OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 836 837 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 838 | (mask_p[59] << 26) | (mask_p[58] << 24) 839 | (mask_p[57] << 22) | (mask_p[56] << 20) 840 | (mask_p[55] << 18) | (mask_p[54] << 16) 841 | (mask_p[53] << 14) | (mask_p[52] << 12) 842 | (mask_p[51] << 10) | (mask_p[50] << 8) 843 | (mask_p[49] << 6) | (mask_p[48] << 4) 844 | (mask_p[47] << 2) | (mask_p[46] << 0); 845 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 846 OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 847 848 OS_REG_WRITE_BUFFER_FLUSH(ah); 849 OS_REG_WRITE_BUFFER_DISABLE(ah); 850 } 851 852 /* 853 * Fill all software cached or static hardware state information. 854 * Return failure if capabilities are to come from EEPROM and 855 * cannot be read. 856 */ 857 HAL_BOOL 858 ar5416FillCapabilityInfo(struct ath_hal *ah) 859 { 860 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 861 HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 862 uint16_t val; 863 864 /* Construct wireless mode from EEPROM */ 865 pCap->halWirelessModes = 0; 866 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) { 867 pCap->halWirelessModes |= HAL_MODE_11A 868 | HAL_MODE_11NA_HT20 869 | HAL_MODE_11NA_HT40PLUS 870 | HAL_MODE_11NA_HT40MINUS 871 ; 872 } 873 if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE)) { 874 pCap->halWirelessModes |= HAL_MODE_11G 875 | HAL_MODE_11NG_HT20 876 | HAL_MODE_11NG_HT40PLUS 877 | HAL_MODE_11NG_HT40MINUS 878 ; 879 pCap->halWirelessModes |= HAL_MODE_11A 880 | HAL_MODE_11NA_HT20 881 | HAL_MODE_11NA_HT40PLUS 882 | HAL_MODE_11NA_HT40MINUS 883 ; 884 } 885 886 pCap->halLow2GhzChan = 2312; 887 pCap->halHigh2GhzChan = 2732; 888 889 pCap->halLow5GhzChan = 4915; 890 pCap->halHigh5GhzChan = 6100; 891 892 pCap->halCipherCkipSupport = AH_FALSE; 893 pCap->halCipherTkipSupport = AH_TRUE; 894 pCap->halCipherAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 895 896 pCap->halMicCkipSupport = AH_FALSE; 897 pCap->halMicTkipSupport = AH_TRUE; 898 pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 899 /* 900 * Starting with Griffin TX+RX mic keys can be combined 901 * in one key cache slot. 902 */ 903 pCap->halTkipMicTxRxKeySupport = AH_TRUE; 904 pCap->halChanSpreadSupport = AH_TRUE; 905 pCap->halSleepAfterBeaconBroken = AH_TRUE; 906 907 pCap->halCompressSupport = AH_FALSE; 908 pCap->halBurstSupport = AH_TRUE; 909 /* 910 * This is disabled for now; the net80211 layer needs to be 911 * taught when it is and isn't appropriate to enable FF processing 912 * with 802.11n NICs (it tries to enable both A-MPDU and 913 * fast frames, with very tragic crash-y results.) 914 */ 915 pCap->halFastFramesSupport = AH_FALSE; 916 pCap->halChapTuningSupport = AH_TRUE; 917 pCap->halTurboPrimeSupport = AH_TRUE; 918 919 pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G; 920 921 pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */ 922 pCap->halNumMRRetries = 4; /* Hardware supports 4 MRR */ 923 pCap->halNumTxMaps = 1; /* Single TX ptr per descr */ 924 pCap->halVEOLSupport = AH_TRUE; 925 pCap->halBssIdMaskSupport = AH_TRUE; 926 pCap->halMcastKeySrchSupport = AH_TRUE; /* Works on AR5416 and later */ 927 pCap->halTsfAddSupport = AH_TRUE; 928 pCap->hal4AddrAggrSupport = AH_FALSE; /* Broken in Owl */ 929 pCap->halSpectralScanSupport = AH_FALSE; /* AR9280 and later */ 930 931 if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK) 932 pCap->halTotalQueues = val; 933 else 934 pCap->halTotalQueues = HAL_NUM_TX_QUEUES; 935 936 if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK) 937 pCap->halKeyCacheSize = val; 938 else 939 pCap->halKeyCacheSize = AR5416_KEYTABLE_SIZE; 940 941 /* XXX Which chips? */ 942 pCap->halChanHalfRate = AH_TRUE; 943 pCap->halChanQuarterRate = AH_TRUE; 944 945 pCap->halTstampPrecision = 32; 946 pCap->halHwPhyCounterSupport = AH_TRUE; 947 pCap->halIntrMask = HAL_INT_COMMON 948 | HAL_INT_RX 949 | HAL_INT_TX 950 | HAL_INT_FATAL 951 | HAL_INT_BNR 952 | HAL_INT_BMISC 953 | HAL_INT_DTIMSYNC 954 | HAL_INT_TSFOOR 955 | HAL_INT_CST 956 | HAL_INT_GTT 957 ; 958 959 pCap->halFastCCSupport = AH_TRUE; 960 pCap->halNumGpioPins = 14; 961 pCap->halWowSupport = AH_FALSE; 962 pCap->halWowMatchPatternExact = AH_FALSE; 963 pCap->halBtCoexSupport = AH_FALSE; /* XXX need support */ 964 pCap->halAutoSleepSupport = AH_FALSE; 965 pCap->hal4kbSplitTransSupport = AH_TRUE; 966 /* Disable this so Block-ACK works correctly */ 967 pCap->halHasRxSelfLinkedTail = AH_FALSE; 968 #if 0 /* XXX not yet */ 969 pCap->halNumAntCfg2GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_2GHZ); 970 pCap->halNumAntCfg5GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_5GHZ); 971 #endif 972 pCap->halHTSupport = AH_TRUE; 973 pCap->halTxChainMask = ath_hal_eepromGet(ah, AR_EEP_TXMASK, AH_NULL); 974 /* XXX CB71 uses GPIO 0 to indicate 3 rx chains */ 975 pCap->halRxChainMask = ath_hal_eepromGet(ah, AR_EEP_RXMASK, AH_NULL); 976 /* AR5416 may have 3 antennas but is a 2x2 stream device */ 977 pCap->halTxStreams = 2; 978 pCap->halRxStreams = 2; 979 980 /* 981 * If the TX or RX chainmask has less than 2 chains active, 982 * mark it as a 1-stream device for the relevant stream. 983 */ 984 if (owl_get_ntxchains(pCap->halTxChainMask) == 1) 985 pCap->halTxStreams = 1; 986 /* XXX Eww */ 987 if (owl_get_ntxchains(pCap->halRxChainMask) == 1) 988 pCap->halRxStreams = 1; 989 pCap->halRtsAggrLimit = 8*1024; /* Owl 2.0 limit */ 990 pCap->halMbssidAggrSupport = AH_FALSE; /* Broken on Owl */ 991 pCap->halForcePpmSupport = AH_TRUE; 992 pCap->halEnhancedPmSupport = AH_TRUE; 993 pCap->halBssidMatchSupport = AH_TRUE; 994 pCap->halGTTSupport = AH_TRUE; 995 pCap->halCSTSupport = AH_TRUE; 996 pCap->halEnhancedDfsSupport = AH_FALSE; 997 /* Hardware supports 32 bit TSF values in the RX descriptor */ 998 pCap->halHasLongRxDescTsf = AH_TRUE; 999 /* 1000 * BB Read WAR: this is only for AR5008/AR9001 NICs 1001 * It is also set individually in the AR91xx attach functions. 1002 */ 1003 if (AR_SREV_OWL(ah)) 1004 pCap->halHasBBReadWar = AH_TRUE; 1005 1006 if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) && 1007 ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) { 1008 /* NB: enabled by default */ 1009 ahpriv->ah_rfkillEnabled = AH_TRUE; 1010 pCap->halRfSilentSupport = AH_TRUE; 1011 } 1012 1013 /* 1014 * The MAC will mark frames as RXed if there's a descriptor 1015 * to write them to. So if it hits a self-linked final descriptor, 1016 * it'll keep ACKing frames even though they're being silently 1017 * dropped. Thus, this particular feature of the driver can't 1018 * be used for 802.11n devices. 1019 */ 1020 ahpriv->ah_rxornIsFatal = AH_FALSE; 1021 1022 /* 1023 * If it's a PCI NIC, ask the HAL OS layer to serialise 1024 * register access, or SMP machines may cause the hardware 1025 * to hang. This is applicable to AR5416 and AR9220; I'm not 1026 * sure about AR9160 or AR9227. 1027 */ 1028 if (! AH_PRIVATE(ah)->ah_ispcie) 1029 pCap->halSerialiseRegWar = 1; 1030 1031 return AH_TRUE; 1032 } 1033 1034 static const char* 1035 ar5416Probe(uint16_t vendorid, uint16_t devid) 1036 { 1037 if (vendorid == ATHEROS_VENDOR_ID) { 1038 if (devid == AR5416_DEVID_PCI) 1039 return "Atheros 5416"; 1040 if (devid == AR5416_DEVID_PCIE) 1041 return "Atheros 5418"; 1042 } 1043 return AH_NULL; 1044 } 1045 AH_CHIP(AR5416, ar5416Probe, ar5416Attach); 1046