1 /* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19 #include "opt_ah.h" 20 21 #include "ah.h" 22 #include "ah_internal.h" 23 #include "ah_devid.h" 24 25 #include "ah_eeprom_v14.h" 26 27 #include "ar5416/ar5416.h" 28 #include "ar5416/ar5416reg.h" 29 #include "ar5416/ar5416phy.h" 30 31 #include "ar5416/ar5416.ini" 32 33 static void ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore); 34 static void ar5416WriteIni(struct ath_hal *ah, 35 const struct ieee80211_channel *chan); 36 static void ar5416SpurMitigate(struct ath_hal *ah, 37 const struct ieee80211_channel *chan); 38 39 static void 40 ar5416AniSetup(struct ath_hal *ah) 41 { 42 static const struct ar5212AniParams aniparams = { 43 .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 44 .totalSizeDesired = { -55, -55, -55, -55, -62 }, 45 .coarseHigh = { -14, -14, -14, -14, -12 }, 46 .coarseLow = { -64, -64, -64, -64, -70 }, 47 .firpwr = { -78, -78, -78, -78, -80 }, 48 .maxSpurImmunityLevel = 2, 49 .cycPwrThr1 = { 2, 4, 6 }, 50 .maxFirstepLevel = 2, /* levels 0..2 */ 51 .firstep = { 0, 4, 8 }, 52 .ofdmTrigHigh = 500, 53 .ofdmTrigLow = 200, 54 .cckTrigHigh = 200, 55 .cckTrigLow = 100, 56 .rssiThrHigh = 40, 57 .rssiThrLow = 7, 58 .period = 100, 59 }; 60 /* NB: disable ANI noise immmunity for reliable RIFS rx */ 61 AH5416(ah)->ah_ani_function &= ~(1 << HAL_ANI_NOISE_IMMUNITY_LEVEL); 62 ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE); 63 } 64 65 /* 66 * AR5416 doesn't do OLC or temperature compensation. 67 */ 68 static void 69 ar5416olcInit(struct ath_hal *ah) 70 { 71 } 72 73 static void 74 ar5416olcTempCompensation(struct ath_hal *ah) 75 { 76 } 77 78 /* 79 * Attach for an AR5416 part. 80 */ 81 void 82 ar5416InitState(struct ath_hal_5416 *ahp5416, uint16_t devid, HAL_SOFTC sc, 83 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status) 84 { 85 struct ath_hal_5212 *ahp; 86 struct ath_hal *ah; 87 88 ahp = &ahp5416->ah_5212; 89 ar5212InitState(ahp, devid, sc, st, sh, status); 90 ah = &ahp->ah_priv.h; 91 92 /* override 5212 methods for our needs */ 93 ah->ah_magic = AR5416_MAGIC; 94 ah->ah_getRateTable = ar5416GetRateTable; 95 ah->ah_detach = ar5416Detach; 96 97 /* Reset functions */ 98 ah->ah_reset = ar5416Reset; 99 ah->ah_phyDisable = ar5416PhyDisable; 100 ah->ah_disable = ar5416Disable; 101 ah->ah_configPCIE = ar5416ConfigPCIE; 102 ah->ah_perCalibration = ar5416PerCalibration; 103 ah->ah_perCalibrationN = ar5416PerCalibrationN, 104 ah->ah_resetCalValid = ar5416ResetCalValid, 105 ah->ah_setTxPowerLimit = ar5416SetTxPowerLimit; 106 ah->ah_setTxPower = ar5416SetTransmitPower; 107 ah->ah_setBoardValues = ar5416SetBoardValues; 108 109 /* Transmit functions */ 110 ah->ah_stopTxDma = ar5416StopTxDma; 111 ah->ah_setupTxDesc = ar5416SetupTxDesc; 112 ah->ah_setupXTxDesc = ar5416SetupXTxDesc; 113 ah->ah_fillTxDesc = ar5416FillTxDesc; 114 ah->ah_procTxDesc = ar5416ProcTxDesc; 115 ah->ah_getTxCompletionRates = ar5416GetTxCompletionRates; 116 ah->ah_setupTxQueue = ar5416SetupTxQueue; 117 ah->ah_resetTxQueue = ar5416ResetTxQueue; 118 119 /* Receive Functions */ 120 ah->ah_getRxFilter = ar5416GetRxFilter; 121 ah->ah_setRxFilter = ar5416SetRxFilter; 122 ah->ah_stopDmaReceive = ar5416StopDmaReceive; 123 ah->ah_startPcuReceive = ar5416StartPcuReceive; 124 ah->ah_stopPcuReceive = ar5416StopPcuReceive; 125 ah->ah_setupRxDesc = ar5416SetupRxDesc; 126 ah->ah_procRxDesc = ar5416ProcRxDesc; 127 ah->ah_rxMonitor = ar5416RxMonitor; 128 ah->ah_aniPoll = ar5416AniPoll; 129 ah->ah_procMibEvent = ar5416ProcessMibIntr; 130 131 /* Misc Functions */ 132 ah->ah_getCapability = ar5416GetCapability; 133 ah->ah_setCapability = ar5416SetCapability; 134 ah->ah_getDiagState = ar5416GetDiagState; 135 ah->ah_setLedState = ar5416SetLedState; 136 ah->ah_gpioCfgOutput = ar5416GpioCfgOutput; 137 ah->ah_gpioCfgInput = ar5416GpioCfgInput; 138 ah->ah_gpioGet = ar5416GpioGet; 139 ah->ah_gpioSet = ar5416GpioSet; 140 ah->ah_gpioSetIntr = ar5416GpioSetIntr; 141 ah->ah_getTsf64 = ar5416GetTsf64; 142 ah->ah_resetTsf = ar5416ResetTsf; 143 ah->ah_getRfGain = ar5416GetRfgain; 144 ah->ah_setAntennaSwitch = ar5416SetAntennaSwitch; 145 ah->ah_setDecompMask = ar5416SetDecompMask; 146 ah->ah_setCoverageClass = ar5416SetCoverageClass; 147 ah->ah_setQuiet = ar5416SetQuiet; 148 149 ah->ah_resetKeyCacheEntry = ar5416ResetKeyCacheEntry; 150 ah->ah_setKeyCacheEntry = ar5416SetKeyCacheEntry; 151 152 /* DFS Functions */ 153 ah->ah_enableDfs = ar5416EnableDfs; 154 ah->ah_getDfsThresh = ar5416GetDfsThresh; 155 ah->ah_procRadarEvent = ar5416ProcessRadarEvent; 156 ah->ah_isFastClockEnabled = ar5416IsFastClockEnabled; 157 158 /* Power Management Functions */ 159 ah->ah_setPowerMode = ar5416SetPowerMode; 160 161 /* Beacon Management Functions */ 162 ah->ah_setBeaconTimers = ar5416SetBeaconTimers; 163 ah->ah_beaconInit = ar5416BeaconInit; 164 ah->ah_setStationBeaconTimers = ar5416SetStaBeaconTimers; 165 ah->ah_resetStationBeaconTimers = ar5416ResetStaBeaconTimers; 166 ah->ah_getNextTBTT = ar5416GetNextTBTT; 167 168 /* 802.11n Functions */ 169 ah->ah_chainTxDesc = ar5416ChainTxDesc; 170 ah->ah_setupFirstTxDesc = ar5416SetupFirstTxDesc; 171 ah->ah_setupLastTxDesc = ar5416SetupLastTxDesc; 172 ah->ah_set11nRateScenario = ar5416Set11nRateScenario; 173 ah->ah_set11nAggrFirst = ar5416Set11nAggrFirst; 174 ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle; 175 ah->ah_set11nAggrLast = ar5416Set11nAggrLast; 176 ah->ah_clr11nAggr = ar5416Clr11nAggr; 177 ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration; 178 ah->ah_get11nExtBusy = ar5416Get11nExtBusy; 179 ah->ah_set11nMac2040 = ar5416Set11nMac2040; 180 ah->ah_get11nRxClear = ar5416Get11nRxClear; 181 ah->ah_set11nRxClear = ar5416Set11nRxClear; 182 183 /* Interrupt functions */ 184 ah->ah_isInterruptPending = ar5416IsInterruptPending; 185 ah->ah_getPendingInterrupts = ar5416GetPendingInterrupts; 186 ah->ah_setInterrupts = ar5416SetInterrupts; 187 188 ahp->ah_priv.ah_getWirelessModes= ar5416GetWirelessModes; 189 ahp->ah_priv.ah_eepromRead = ar5416EepromRead; 190 #ifdef AH_SUPPORT_WRITE_EEPROM 191 ahp->ah_priv.ah_eepromWrite = ar5416EepromWrite; 192 #endif 193 ahp->ah_priv.ah_getChipPowerLimits = ar5416GetChipPowerLimits; 194 195 /* Internal ops */ 196 AH5416(ah)->ah_writeIni = ar5416WriteIni; 197 AH5416(ah)->ah_spurMitigate = ar5416SpurMitigate; 198 199 /* Internal baseband ops */ 200 AH5416(ah)->ah_initPLL = ar5416InitPLL; 201 202 /* Internal calibration ops */ 203 AH5416(ah)->ah_cal_initcal = ar5416InitCalHardware; 204 205 /* Internal TX power control related operations */ 206 AH5416(ah)->ah_olcInit = ar5416olcInit; 207 AH5416(ah)->ah_olcTempCompensation = ar5416olcTempCompensation; 208 AH5416(ah)->ah_setPowerCalTable = ar5416SetPowerCalTable; 209 210 /* 211 * Start by setting all Owl devices to 2x2 212 */ 213 AH5416(ah)->ah_rx_chainmask = AR5416_DEFAULT_RXCHAINMASK; 214 AH5416(ah)->ah_tx_chainmask = AR5416_DEFAULT_TXCHAINMASK; 215 216 /* Enable all ANI functions to begin with */ 217 AH5416(ah)->ah_ani_function = 0xffffffff; 218 219 /* Set overridable ANI methods */ 220 AH5212(ah)->ah_aniControl = ar5416AniControl; 221 } 222 223 uint32_t 224 ar5416GetRadioRev(struct ath_hal *ah) 225 { 226 uint32_t val; 227 int i; 228 229 /* Read Radio Chip Rev Extract */ 230 OS_REG_WRITE(ah, AR_PHY(0x36), 0x00007058); 231 for (i = 0; i < 8; i++) 232 OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000); 233 val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; 234 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 235 return ath_hal_reverseBits(val, 8); 236 } 237 238 /* 239 * Attach for an AR5416 part. 240 */ 241 static struct ath_hal * 242 ar5416Attach(uint16_t devid, HAL_SOFTC sc, 243 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 244 HAL_STATUS *status) 245 { 246 struct ath_hal_5416 *ahp5416; 247 struct ath_hal_5212 *ahp; 248 struct ath_hal *ah; 249 uint32_t val; 250 HAL_STATUS ecode; 251 HAL_BOOL rfStatus; 252 253 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 254 __func__, sc, (void*) st, (void*) sh); 255 256 /* NB: memory is returned zero'd */ 257 ahp5416 = ath_hal_malloc(sizeof (struct ath_hal_5416) + 258 /* extra space for Owl 2.1/2.2 WAR */ 259 sizeof(ar5416Addac) 260 ); 261 if (ahp5416 == AH_NULL) { 262 HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 263 "%s: cannot allocate memory for state block\n", __func__); 264 *status = HAL_ENOMEM; 265 return AH_NULL; 266 } 267 ar5416InitState(ahp5416, devid, sc, st, sh, status); 268 ahp = &ahp5416->ah_5212; 269 ah = &ahp->ah_priv.h; 270 271 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { 272 /* reset chip */ 273 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", __func__); 274 ecode = HAL_EIO; 275 goto bad; 276 } 277 278 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 279 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", __func__); 280 ecode = HAL_EIO; 281 goto bad; 282 } 283 /* Read Revisions from Chips before taking out of reset */ 284 val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID; 285 AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S; 286 AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION; 287 AH_PRIVATE(ah)->ah_ispcie = (devid == AR5416_DEVID_PCIE); 288 289 /* setup common ini data; rf backends handle remainder */ 290 HAL_INI_INIT(&ahp->ah_ini_modes, ar5416Modes, 6); 291 HAL_INI_INIT(&ahp->ah_ini_common, ar5416Common, 2); 292 293 HAL_INI_INIT(&AH5416(ah)->ah_ini_bb_rfgain, ar5416BB_RfGain, 3); 294 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank0, ar5416Bank0, 2); 295 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank1, ar5416Bank1, 2); 296 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank2, ar5416Bank2, 2); 297 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank3, ar5416Bank3, 3); 298 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank6, ar5416Bank6, 3); 299 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank7, ar5416Bank7, 2); 300 HAL_INI_INIT(&AH5416(ah)->ah_ini_addac, ar5416Addac, 2); 301 302 if (! IS_5416V2_2(ah)) { /* Owl 2.1/2.0 */ 303 ath_hal_printf(ah, "[ath] Enabling CLKDRV workaround for AR5416 < v2.2\n"); 304 struct ini { 305 uint32_t *data; /* NB: !const */ 306 int rows, cols; 307 }; 308 /* override CLKDRV value */ 309 OS_MEMCPY(&AH5416(ah)[1], ar5416Addac, sizeof(ar5416Addac)); 310 AH5416(ah)->ah_ini_addac.data = (uint32_t *) &AH5416(ah)[1]; 311 HAL_INI_VAL((struct ini *)&AH5416(ah)->ah_ini_addac, 31, 1) = 0; 312 } 313 314 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, ar5416PciePhy, 2); 315 ar5416AttachPCIE(ah); 316 317 ecode = ath_hal_v14EepromAttach(ah); 318 if (ecode != HAL_OK) 319 goto bad; 320 321 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */ 322 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", 323 __func__); 324 ecode = HAL_EIO; 325 goto bad; 326 } 327 328 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 329 330 if (!ar5212ChipTest(ah)) { 331 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 332 __func__); 333 ecode = HAL_ESELFTEST; 334 goto bad; 335 } 336 337 /* 338 * Set correct Baseband to analog shift 339 * setting to access analog chips. 340 */ 341 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 342 343 /* Read Radio Chip Rev Extract */ 344 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah); 345 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 346 case AR_RAD5122_SREV_MAJOR: /* Fowl: 5G/2x2 */ 347 case AR_RAD2122_SREV_MAJOR: /* Fowl: 2+5G/2x2 */ 348 case AR_RAD2133_SREV_MAJOR: /* Fowl: 2G/3x3 */ 349 case AR_RAD5133_SREV_MAJOR: /* Fowl: 2+5G/3x3 */ 350 break; 351 default: 352 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 353 /* 354 * When RF_Silen is used the analog chip is reset. 355 * So when the system boots with radio switch off 356 * the RF chip rev reads back as zero and we need 357 * to use the mac+phy revs to set the radio rev. 358 */ 359 AH_PRIVATE(ah)->ah_analog5GhzRev = 360 AR_RAD5133_SREV_MAJOR; 361 break; 362 } 363 /* NB: silently accept anything in release code per Atheros */ 364 #ifdef AH_DEBUG 365 HALDEBUG(ah, HAL_DEBUG_ANY, 366 "%s: 5G Radio Chip Rev 0x%02X is not supported by " 367 "this driver\n", __func__, 368 AH_PRIVATE(ah)->ah_analog5GhzRev); 369 ecode = HAL_ENOTSUPP; 370 goto bad; 371 #endif 372 } 373 374 /* 375 * Got everything we need now to setup the capabilities. 376 */ 377 if (!ar5416FillCapabilityInfo(ah)) { 378 ecode = HAL_EEREAD; 379 goto bad; 380 } 381 382 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 383 if (ecode != HAL_OK) { 384 HALDEBUG(ah, HAL_DEBUG_ANY, 385 "%s: error getting mac address from EEPROM\n", __func__); 386 goto bad; 387 } 388 /* XXX How about the serial number ? */ 389 /* Read Reg Domain */ 390 AH_PRIVATE(ah)->ah_currentRD = 391 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL); 392 AH_PRIVATE(ah)->ah_currentRDext = 393 ath_hal_eepromGet(ah, AR_EEP_REGDMN_1, AH_NULL); 394 395 /* 396 * ah_miscMode is populated by ar5416FillCapabilityInfo() 397 * starting from griffin. Set here to make sure that 398 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is 399 * placed into hardware. 400 */ 401 if (ahp->ah_miscMode != 0) 402 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode); 403 404 rfStatus = ar2133RfAttach(ah, &ecode); 405 if (!rfStatus) { 406 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 407 __func__, ecode); 408 goto bad; 409 } 410 411 ar5416AniSetup(ah); /* Anti Noise Immunity */ 412 413 AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ; 414 AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ; 415 AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ; 416 AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ; 417 AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ; 418 AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ; 419 420 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist); 421 422 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 423 424 return ah; 425 bad: 426 if (ahp) 427 ar5416Detach((struct ath_hal *) ahp); 428 if (status) 429 *status = ecode; 430 return AH_NULL; 431 } 432 433 void 434 ar5416Detach(struct ath_hal *ah) 435 { 436 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__); 437 438 HALASSERT(ah != AH_NULL); 439 HALASSERT(ah->ah_magic == AR5416_MAGIC); 440 441 /* Make sure that chip is awake before writing to it */ 442 if (! ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 443 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, 444 "%s: failed to wake up chip\n", 445 __func__); 446 447 ar5416AniDetach(ah); 448 ar5212RfDetach(ah); 449 ah->ah_disable(ah); 450 ar5416SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); 451 ath_hal_eepromDetach(ah); 452 ath_hal_free(ah); 453 } 454 455 void 456 ar5416AttachPCIE(struct ath_hal *ah) 457 { 458 if (AH_PRIVATE(ah)->ah_ispcie) 459 ath_hal_configPCIE(ah, AH_FALSE); 460 else 461 ath_hal_disablePCIE(ah); 462 } 463 464 static void 465 ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore) 466 { 467 if (AH_PRIVATE(ah)->ah_ispcie && !restore) { 468 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0); 469 OS_DELAY(1000); 470 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 471 OS_REG_WRITE(ah, AR_WA, AR_WA_DEFAULT); 472 } 473 } 474 475 static void 476 ar5416WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan) 477 { 478 u_int modesIndex, freqIndex; 479 int regWrites = 0; 480 481 /* Setup the indices for the next set of register array writes */ 482 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */ 483 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 484 freqIndex = 2; 485 if (IEEE80211_IS_CHAN_HT40(chan)) 486 modesIndex = 3; 487 else if (IEEE80211_IS_CHAN_108G(chan)) 488 modesIndex = 5; 489 else 490 modesIndex = 4; 491 } else { 492 freqIndex = 1; 493 if (IEEE80211_IS_CHAN_HT40(chan) || 494 IEEE80211_IS_CHAN_TURBO(chan)) 495 modesIndex = 2; 496 else 497 modesIndex = 1; 498 } 499 500 /* Set correct Baseband to analog shift setting to access analog chips. */ 501 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 502 503 /* 504 * Write addac shifts 505 */ 506 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); 507 508 /* NB: only required for Sowl */ 509 if (AR_SREV_SOWL(ah)) 510 ar5416EepromSetAddac(ah, chan); 511 512 regWrites = ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_addac, 1, 513 regWrites); 514 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 515 516 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, 517 modesIndex, regWrites); 518 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 519 1, regWrites); 520 521 /* XXX updated regWrites? */ 522 AH5212(ah)->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites); 523 } 524 525 /* 526 * Convert to baseband spur frequency given input channel frequency 527 * and compute register settings below. 528 */ 529 530 static void 531 ar5416SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan) 532 { 533 uint16_t freq = ath_hal_gethwchannel(ah, chan); 534 static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, 535 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 }; 536 static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, 537 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 }; 538 static const int inc[4] = { 0, 100, 0, 0 }; 539 540 int bb_spur = AR_NO_SPUR; 541 int bin, cur_bin; 542 int spur_freq_sd; 543 int spur_delta_phase; 544 int denominator; 545 int upper, lower, cur_vit_mask; 546 int tmp, new; 547 int i; 548 549 int8_t mask_m[123]; 550 int8_t mask_p[123]; 551 int8_t mask_amt; 552 int tmp_mask; 553 int cur_bb_spur; 554 HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 555 556 OS_MEMZERO(mask_m, sizeof(mask_m)); 557 OS_MEMZERO(mask_p, sizeof(mask_p)); 558 559 /* 560 * Need to verify range +/- 9.5 for static ht20, otherwise spur 561 * is out-of-band and can be ignored. 562 */ 563 /* XXX ath9k changes */ 564 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { 565 cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz); 566 if (AR_NO_SPUR == cur_bb_spur) 567 break; 568 cur_bb_spur = cur_bb_spur - (freq * 10); 569 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) { 570 bb_spur = cur_bb_spur; 571 break; 572 } 573 } 574 if (AR_NO_SPUR == bb_spur) 575 return; 576 577 bin = bb_spur * 32; 578 579 tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)); 580 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 581 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 582 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 583 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 584 585 OS_REG_WRITE_BUFFER_ENABLE(ah); 586 587 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), new); 588 589 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 590 AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 591 AR_PHY_SPUR_REG_MASK_RATE_SELECT | 592 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 593 SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 594 OS_REG_WRITE(ah, AR_PHY_SPUR_REG, new); 595 /* 596 * Should offset bb_spur by +/- 10 MHz for dynamic 2040 MHz 597 * config, no offset for HT20. 598 * spur_delta_phase = bb_spur/40 * 2**21 for static ht20, 599 * /80 for dyn2040. 600 */ 601 spur_delta_phase = ((bb_spur * 524288) / 100) & 602 AR_PHY_TIMING11_SPUR_DELTA_PHASE; 603 /* 604 * in 11A mode the denominator of spur_freq_sd should be 40 and 605 * it should be 44 in 11G 606 */ 607 denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 440 : 400; 608 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff; 609 610 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 611 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 612 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 613 OS_REG_WRITE(ah, AR_PHY_TIMING11, new); 614 615 616 /* 617 * ============================================ 618 * pilot mask 1 [31:0] = +6..-26, no 0 bin 619 * pilot mask 2 [19:0] = +26..+7 620 * 621 * channel mask 1 [31:0] = +6..-26, no 0 bin 622 * channel mask 2 [19:0] = +26..+7 623 */ 624 //cur_bin = -26; 625 cur_bin = -6000; 626 upper = bin + 100; 627 lower = bin - 100; 628 629 for (i = 0; i < 4; i++) { 630 int pilot_mask = 0; 631 int chan_mask = 0; 632 int bp = 0; 633 for (bp = 0; bp < 30; bp++) { 634 if ((cur_bin > lower) && (cur_bin < upper)) { 635 pilot_mask = pilot_mask | 0x1 << bp; 636 chan_mask = chan_mask | 0x1 << bp; 637 } 638 cur_bin += 100; 639 } 640 cur_bin += inc[i]; 641 OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 642 OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask); 643 } 644 645 /* ================================================= 646 * viterbi mask 1 based on channel magnitude 647 * four levels 0-3 648 * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c) 649 * [1 2 2 1] for -9.6 or [1 2 1] for +16 650 * - enable_mask_ppm, all bins move with freq 651 * 652 * - mask_select, 8 bits for rates (reg 67,0x990c) 653 * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c) 654 * choose which mask to use mask or mask2 655 */ 656 657 /* 658 * viterbi mask 2 2nd set for per data rate puncturing 659 * four levels 0-3 660 * - mask_select, 8 bits for rates (reg 67) 661 * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994) 662 * [1 2 2 1] for -9.6 or [1 2 1] for +16 663 */ 664 cur_vit_mask = 6100; 665 upper = bin + 120; 666 lower = bin - 120; 667 668 for (i = 0; i < 123; i++) { 669 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 670 if ((abs(cur_vit_mask - bin)) < 75) { 671 mask_amt = 1; 672 } else { 673 mask_amt = 0; 674 } 675 if (cur_vit_mask < 0) { 676 mask_m[abs(cur_vit_mask / 100)] = mask_amt; 677 } else { 678 mask_p[cur_vit_mask / 100] = mask_amt; 679 } 680 } 681 cur_vit_mask -= 100; 682 } 683 684 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 685 | (mask_m[48] << 26) | (mask_m[49] << 24) 686 | (mask_m[50] << 22) | (mask_m[51] << 20) 687 | (mask_m[52] << 18) | (mask_m[53] << 16) 688 | (mask_m[54] << 14) | (mask_m[55] << 12) 689 | (mask_m[56] << 10) | (mask_m[57] << 8) 690 | (mask_m[58] << 6) | (mask_m[59] << 4) 691 | (mask_m[60] << 2) | (mask_m[61] << 0); 692 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 693 OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 694 695 tmp_mask = (mask_m[31] << 28) 696 | (mask_m[32] << 26) | (mask_m[33] << 24) 697 | (mask_m[34] << 22) | (mask_m[35] << 20) 698 | (mask_m[36] << 18) | (mask_m[37] << 16) 699 | (mask_m[48] << 14) | (mask_m[39] << 12) 700 | (mask_m[40] << 10) | (mask_m[41] << 8) 701 | (mask_m[42] << 6) | (mask_m[43] << 4) 702 | (mask_m[44] << 2) | (mask_m[45] << 0); 703 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 704 OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 705 706 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 707 | (mask_m[18] << 26) | (mask_m[18] << 24) 708 | (mask_m[20] << 22) | (mask_m[20] << 20) 709 | (mask_m[22] << 18) | (mask_m[22] << 16) 710 | (mask_m[24] << 14) | (mask_m[24] << 12) 711 | (mask_m[25] << 10) | (mask_m[26] << 8) 712 | (mask_m[27] << 6) | (mask_m[28] << 4) 713 | (mask_m[29] << 2) | (mask_m[30] << 0); 714 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 715 OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 716 717 tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28) 718 | (mask_m[ 2] << 26) | (mask_m[ 3] << 24) 719 | (mask_m[ 4] << 22) | (mask_m[ 5] << 20) 720 | (mask_m[ 6] << 18) | (mask_m[ 7] << 16) 721 | (mask_m[ 8] << 14) | (mask_m[ 9] << 12) 722 | (mask_m[10] << 10) | (mask_m[11] << 8) 723 | (mask_m[12] << 6) | (mask_m[13] << 4) 724 | (mask_m[14] << 2) | (mask_m[15] << 0); 725 OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 726 OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 727 728 tmp_mask = (mask_p[15] << 28) 729 | (mask_p[14] << 26) | (mask_p[13] << 24) 730 | (mask_p[12] << 22) | (mask_p[11] << 20) 731 | (mask_p[10] << 18) | (mask_p[ 9] << 16) 732 | (mask_p[ 8] << 14) | (mask_p[ 7] << 12) 733 | (mask_p[ 6] << 10) | (mask_p[ 5] << 8) 734 | (mask_p[ 4] << 6) | (mask_p[ 3] << 4) 735 | (mask_p[ 2] << 2) | (mask_p[ 1] << 0); 736 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 737 OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 738 739 tmp_mask = (mask_p[30] << 28) 740 | (mask_p[29] << 26) | (mask_p[28] << 24) 741 | (mask_p[27] << 22) | (mask_p[26] << 20) 742 | (mask_p[25] << 18) | (mask_p[24] << 16) 743 | (mask_p[23] << 14) | (mask_p[22] << 12) 744 | (mask_p[21] << 10) | (mask_p[20] << 8) 745 | (mask_p[19] << 6) | (mask_p[18] << 4) 746 | (mask_p[17] << 2) | (mask_p[16] << 0); 747 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 748 OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 749 750 tmp_mask = (mask_p[45] << 28) 751 | (mask_p[44] << 26) | (mask_p[43] << 24) 752 | (mask_p[42] << 22) | (mask_p[41] << 20) 753 | (mask_p[40] << 18) | (mask_p[39] << 16) 754 | (mask_p[38] << 14) | (mask_p[37] << 12) 755 | (mask_p[36] << 10) | (mask_p[35] << 8) 756 | (mask_p[34] << 6) | (mask_p[33] << 4) 757 | (mask_p[32] << 2) | (mask_p[31] << 0); 758 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 759 OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 760 761 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 762 | (mask_p[59] << 26) | (mask_p[58] << 24) 763 | (mask_p[57] << 22) | (mask_p[56] << 20) 764 | (mask_p[55] << 18) | (mask_p[54] << 16) 765 | (mask_p[53] << 14) | (mask_p[52] << 12) 766 | (mask_p[51] << 10) | (mask_p[50] << 8) 767 | (mask_p[49] << 6) | (mask_p[48] << 4) 768 | (mask_p[47] << 2) | (mask_p[46] << 0); 769 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 770 OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 771 772 OS_REG_WRITE_BUFFER_FLUSH(ah); 773 OS_REG_WRITE_BUFFER_DISABLE(ah); 774 } 775 776 /* 777 * Fill all software cached or static hardware state information. 778 * Return failure if capabilities are to come from EEPROM and 779 * cannot be read. 780 */ 781 HAL_BOOL 782 ar5416FillCapabilityInfo(struct ath_hal *ah) 783 { 784 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 785 HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 786 uint16_t val; 787 788 /* Construct wireless mode from EEPROM */ 789 pCap->halWirelessModes = 0; 790 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) { 791 pCap->halWirelessModes |= HAL_MODE_11A 792 | HAL_MODE_11NA_HT20 793 | HAL_MODE_11NA_HT40PLUS 794 | HAL_MODE_11NA_HT40MINUS 795 ; 796 } 797 if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE)) { 798 pCap->halWirelessModes |= HAL_MODE_11G 799 | HAL_MODE_11NG_HT20 800 | HAL_MODE_11NG_HT40PLUS 801 | HAL_MODE_11NG_HT40MINUS 802 ; 803 pCap->halWirelessModes |= HAL_MODE_11A 804 | HAL_MODE_11NA_HT20 805 | HAL_MODE_11NA_HT40PLUS 806 | HAL_MODE_11NA_HT40MINUS 807 ; 808 } 809 810 pCap->halLow2GhzChan = 2312; 811 pCap->halHigh2GhzChan = 2732; 812 813 pCap->halLow5GhzChan = 4915; 814 pCap->halHigh5GhzChan = 6100; 815 816 pCap->halCipherCkipSupport = AH_FALSE; 817 pCap->halCipherTkipSupport = AH_TRUE; 818 pCap->halCipherAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 819 820 pCap->halMicCkipSupport = AH_FALSE; 821 pCap->halMicTkipSupport = AH_TRUE; 822 pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 823 /* 824 * Starting with Griffin TX+RX mic keys can be combined 825 * in one key cache slot. 826 */ 827 pCap->halTkipMicTxRxKeySupport = AH_TRUE; 828 pCap->halChanSpreadSupport = AH_TRUE; 829 pCap->halSleepAfterBeaconBroken = AH_TRUE; 830 831 pCap->halCompressSupport = AH_FALSE; 832 pCap->halBurstSupport = AH_TRUE; 833 pCap->halFastFramesSupport = AH_FALSE; /* XXX? */ 834 pCap->halChapTuningSupport = AH_TRUE; 835 pCap->halTurboPrimeSupport = AH_TRUE; 836 837 pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G; 838 839 pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */ 840 pCap->halVEOLSupport = AH_TRUE; 841 pCap->halBssIdMaskSupport = AH_TRUE; 842 pCap->halMcastKeySrchSupport = AH_TRUE; /* Works on AR5416 and later */ 843 pCap->halTsfAddSupport = AH_TRUE; 844 pCap->hal4AddrAggrSupport = AH_FALSE; /* Broken in Owl */ 845 846 if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK) 847 pCap->halTotalQueues = val; 848 else 849 pCap->halTotalQueues = HAL_NUM_TX_QUEUES; 850 851 if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK) 852 pCap->halKeyCacheSize = val; 853 else 854 pCap->halKeyCacheSize = AR5416_KEYTABLE_SIZE; 855 856 /* XXX not needed */ 857 pCap->halChanHalfRate = AH_FALSE; /* XXX ? */ 858 pCap->halChanQuarterRate = AH_FALSE; /* XXX ? */ 859 860 pCap->halTstampPrecision = 32; 861 pCap->halHwPhyCounterSupport = AH_TRUE; 862 pCap->halIntrMask = HAL_INT_COMMON 863 | HAL_INT_RX 864 | HAL_INT_TX 865 | HAL_INT_FATAL 866 | HAL_INT_BNR 867 | HAL_INT_BMISC 868 | HAL_INT_DTIMSYNC 869 | HAL_INT_TSFOOR 870 | HAL_INT_CST 871 | HAL_INT_GTT 872 ; 873 874 pCap->halFastCCSupport = AH_TRUE; 875 pCap->halNumGpioPins = 14; 876 pCap->halWowSupport = AH_FALSE; 877 pCap->halWowMatchPatternExact = AH_FALSE; 878 pCap->halBtCoexSupport = AH_FALSE; /* XXX need support */ 879 pCap->halAutoSleepSupport = AH_FALSE; 880 pCap->hal4kbSplitTransSupport = AH_TRUE; 881 /* Disable this so Block-ACK works correctly */ 882 pCap->halHasRxSelfLinkedTail = AH_FALSE; 883 #if 0 /* XXX not yet */ 884 pCap->halNumAntCfg2GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_2GHZ); 885 pCap->halNumAntCfg5GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_5GHZ); 886 #endif 887 pCap->halHTSupport = AH_TRUE; 888 pCap->halTxChainMask = ath_hal_eepromGet(ah, AR_EEP_TXMASK, AH_NULL); 889 /* XXX CB71 uses GPIO 0 to indicate 3 rx chains */ 890 pCap->halRxChainMask = ath_hal_eepromGet(ah, AR_EEP_RXMASK, AH_NULL); 891 /* AR5416 may have 3 antennas but is a 2x2 stream device */ 892 pCap->halTxStreams = 2; 893 pCap->halRxStreams = 2; 894 895 /* 896 * If the TX or RX chainmask has less than 2 chains active, 897 * mark it as a 1-stream device for the relevant stream. 898 */ 899 if (owl_get_ntxchains(pCap->halTxChainMask) == 1) 900 pCap->halTxStreams = 1; 901 /* XXX Eww */ 902 if (owl_get_ntxchains(pCap->halRxChainMask) == 1) 903 pCap->halRxStreams = 1; 904 pCap->halRtsAggrLimit = 8*1024; /* Owl 2.0 limit */ 905 pCap->halMbssidAggrSupport = AH_FALSE; /* Broken on Owl */ 906 pCap->halForcePpmSupport = AH_TRUE; 907 pCap->halEnhancedPmSupport = AH_TRUE; 908 pCap->halBssidMatchSupport = AH_TRUE; 909 pCap->halGTTSupport = AH_TRUE; 910 pCap->halCSTSupport = AH_TRUE; 911 pCap->halEnhancedDfsSupport = AH_FALSE; 912 /* Hardware supports 32 bit TSF values in the RX descriptor */ 913 pCap->halHasLongRxDescTsf = AH_TRUE; 914 /* 915 * BB Read WAR: this is only for AR5008/AR9001 NICs 916 * It is also set individually in the AR91xx attach functions. 917 */ 918 if (AR_SREV_OWL(ah)) 919 pCap->halHasBBReadWar = AH_TRUE; 920 921 if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) && 922 ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) { 923 /* NB: enabled by default */ 924 ahpriv->ah_rfkillEnabled = AH_TRUE; 925 pCap->halRfSilentSupport = AH_TRUE; 926 } 927 928 /* 929 * The MAC will mark frames as RXed if there's a descriptor 930 * to write them to. So if it hits a self-linked final descriptor, 931 * it'll keep ACKing frames even though they're being silently 932 * dropped. Thus, this particular feature of the driver can't 933 * be used for 802.11n devices. 934 */ 935 ahpriv->ah_rxornIsFatal = AH_FALSE; 936 937 /* 938 * If it's a PCI NIC, ask the HAL OS layer to serialise 939 * register access, or SMP machines may cause the hardware 940 * to hang. This is applicable to AR5416 and AR9220; I'm not 941 * sure about AR9160 or AR9227. 942 */ 943 if (! AH_PRIVATE(ah)->ah_ispcie) 944 pCap->halSerialiseRegWar = 1; 945 946 return AH_TRUE; 947 } 948 949 static const char* 950 ar5416Probe(uint16_t vendorid, uint16_t devid) 951 { 952 if (vendorid == ATHEROS_VENDOR_ID) { 953 if (devid == AR5416_DEVID_PCI) 954 return "Atheros 5416"; 955 if (devid == AR5416_DEVID_PCIE) 956 return "Atheros 5418"; 957 } 958 return AH_NULL; 959 } 960 AH_CHIP(AR5416, ar5416Probe, ar5416Attach); 961