1 /* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19 #include "opt_ah.h" 20 21 #include "ah.h" 22 #include "ah_internal.h" 23 #include "ah_devid.h" 24 25 #include "ah_eeprom_v14.h" 26 27 #include "ar5416/ar5416.h" 28 #include "ar5416/ar5416reg.h" 29 #include "ar5416/ar5416phy.h" 30 31 #include "ar5416/ar5416.ini" 32 33 static void ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore); 34 static void ar5416WriteIni(struct ath_hal *ah, 35 const struct ieee80211_channel *chan); 36 static void ar5416SpurMitigate(struct ath_hal *ah, 37 const struct ieee80211_channel *chan); 38 39 static void 40 ar5416AniSetup(struct ath_hal *ah) 41 { 42 static const struct ar5212AniParams aniparams = { 43 .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 44 .totalSizeDesired = { -55, -55, -55, -55, -62 }, 45 .coarseHigh = { -14, -14, -14, -14, -12 }, 46 .coarseLow = { -64, -64, -64, -64, -70 }, 47 .firpwr = { -78, -78, -78, -78, -80 }, 48 .maxSpurImmunityLevel = 2, 49 .cycPwrThr1 = { 2, 4, 6 }, 50 .maxFirstepLevel = 2, /* levels 0..2 */ 51 .firstep = { 0, 4, 8 }, 52 .ofdmTrigHigh = 500, 53 .ofdmTrigLow = 200, 54 .cckTrigHigh = 200, 55 .cckTrigLow = 100, 56 .rssiThrHigh = 40, 57 .rssiThrLow = 7, 58 .period = 100, 59 }; 60 /* NB: disable ANI noise immmunity for reliable RIFS rx */ 61 AH5416(ah)->ah_ani_function &= ~(1 << HAL_ANI_NOISE_IMMUNITY_LEVEL); 62 ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE); 63 } 64 65 /* 66 * AR5416 doesn't do OLC or temperature compensation. 67 */ 68 static void 69 ar5416olcInit(struct ath_hal *ah) 70 { 71 } 72 73 static void 74 ar5416olcTempCompensation(struct ath_hal *ah) 75 { 76 } 77 78 /* 79 * Attach for an AR5416 part. 80 */ 81 void 82 ar5416InitState(struct ath_hal_5416 *ahp5416, uint16_t devid, HAL_SOFTC sc, 83 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status) 84 { 85 struct ath_hal_5212 *ahp; 86 struct ath_hal *ah; 87 88 ahp = &ahp5416->ah_5212; 89 ar5212InitState(ahp, devid, sc, st, sh, status); 90 ah = &ahp->ah_priv.h; 91 92 /* override 5212 methods for our needs */ 93 ah->ah_magic = AR5416_MAGIC; 94 ah->ah_getRateTable = ar5416GetRateTable; 95 ah->ah_detach = ar5416Detach; 96 97 /* Reset functions */ 98 ah->ah_reset = ar5416Reset; 99 ah->ah_phyDisable = ar5416PhyDisable; 100 ah->ah_disable = ar5416Disable; 101 ah->ah_configPCIE = ar5416ConfigPCIE; 102 ah->ah_perCalibration = ar5416PerCalibration; 103 ah->ah_perCalibrationN = ar5416PerCalibrationN, 104 ah->ah_resetCalValid = ar5416ResetCalValid, 105 ah->ah_setTxPowerLimit = ar5416SetTxPowerLimit; 106 ah->ah_setTxPower = ar5416SetTransmitPower; 107 ah->ah_setBoardValues = ar5416SetBoardValues; 108 109 /* Transmit functions */ 110 ah->ah_stopTxDma = ar5416StopTxDma; 111 ah->ah_setupTxDesc = ar5416SetupTxDesc; 112 ah->ah_setupXTxDesc = ar5416SetupXTxDesc; 113 ah->ah_fillTxDesc = ar5416FillTxDesc; 114 ah->ah_procTxDesc = ar5416ProcTxDesc; 115 ah->ah_getTxCompletionRates = ar5416GetTxCompletionRates; 116 ah->ah_setupTxQueue = ar5416SetupTxQueue; 117 ah->ah_resetTxQueue = ar5416ResetTxQueue; 118 119 /* Receive Functions */ 120 ah->ah_getRxFilter = ar5416GetRxFilter; 121 ah->ah_setRxFilter = ar5416SetRxFilter; 122 ah->ah_startPcuReceive = ar5416StartPcuReceive; 123 ah->ah_stopPcuReceive = ar5416StopPcuReceive; 124 ah->ah_setupRxDesc = ar5416SetupRxDesc; 125 ah->ah_procRxDesc = ar5416ProcRxDesc; 126 ah->ah_rxMonitor = ar5416RxMonitor; 127 ah->ah_aniPoll = ar5416AniPoll; 128 ah->ah_procMibEvent = ar5416ProcessMibIntr; 129 130 /* Misc Functions */ 131 ah->ah_getCapability = ar5416GetCapability; 132 ah->ah_setCapability = ar5416SetCapability; 133 ah->ah_getDiagState = ar5416GetDiagState; 134 ah->ah_setLedState = ar5416SetLedState; 135 ah->ah_gpioCfgOutput = ar5416GpioCfgOutput; 136 ah->ah_gpioCfgInput = ar5416GpioCfgInput; 137 ah->ah_gpioGet = ar5416GpioGet; 138 ah->ah_gpioSet = ar5416GpioSet; 139 ah->ah_gpioSetIntr = ar5416GpioSetIntr; 140 ah->ah_getTsf64 = ar5416GetTsf64; 141 ah->ah_resetTsf = ar5416ResetTsf; 142 ah->ah_getRfGain = ar5416GetRfgain; 143 ah->ah_setAntennaSwitch = ar5416SetAntennaSwitch; 144 ah->ah_setDecompMask = ar5416SetDecompMask; 145 ah->ah_setCoverageClass = ar5416SetCoverageClass; 146 ah->ah_setQuiet = ar5416SetQuiet; 147 148 ah->ah_resetKeyCacheEntry = ar5416ResetKeyCacheEntry; 149 ah->ah_setKeyCacheEntry = ar5416SetKeyCacheEntry; 150 151 /* DFS Functions */ 152 ah->ah_enableDfs = ar5416EnableDfs; 153 ah->ah_getDfsThresh = ar5416GetDfsThresh; 154 ah->ah_procRadarEvent = ar5416ProcessRadarEvent; 155 ah->ah_isFastClockEnabled = ar5416IsFastClockEnabled; 156 157 /* Power Management Functions */ 158 ah->ah_setPowerMode = ar5416SetPowerMode; 159 160 /* Beacon Management Functions */ 161 ah->ah_setBeaconTimers = ar5416SetBeaconTimers; 162 ah->ah_beaconInit = ar5416BeaconInit; 163 ah->ah_setStationBeaconTimers = ar5416SetStaBeaconTimers; 164 ah->ah_resetStationBeaconTimers = ar5416ResetStaBeaconTimers; 165 ah->ah_getNextTBTT = ar5416GetNextTBTT; 166 167 /* 802.11n Functions */ 168 ah->ah_chainTxDesc = ar5416ChainTxDesc; 169 ah->ah_setupFirstTxDesc = ar5416SetupFirstTxDesc; 170 ah->ah_setupLastTxDesc = ar5416SetupLastTxDesc; 171 ah->ah_set11nRateScenario = ar5416Set11nRateScenario; 172 ah->ah_set11nAggrFirst = ar5416Set11nAggrFirst; 173 ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle; 174 ah->ah_set11nAggrLast = ar5416Set11nAggrLast; 175 ah->ah_clr11nAggr = ar5416Clr11nAggr; 176 ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration; 177 ah->ah_get11nExtBusy = ar5416Get11nExtBusy; 178 ah->ah_set11nMac2040 = ar5416Set11nMac2040; 179 ah->ah_get11nRxClear = ar5416Get11nRxClear; 180 ah->ah_set11nRxClear = ar5416Set11nRxClear; 181 182 /* Interrupt functions */ 183 ah->ah_isInterruptPending = ar5416IsInterruptPending; 184 ah->ah_getPendingInterrupts = ar5416GetPendingInterrupts; 185 ah->ah_setInterrupts = ar5416SetInterrupts; 186 187 ahp->ah_priv.ah_getWirelessModes= ar5416GetWirelessModes; 188 ahp->ah_priv.ah_eepromRead = ar5416EepromRead; 189 #ifdef AH_SUPPORT_WRITE_EEPROM 190 ahp->ah_priv.ah_eepromWrite = ar5416EepromWrite; 191 #endif 192 ahp->ah_priv.ah_getChipPowerLimits = ar5416GetChipPowerLimits; 193 194 /* Internal ops */ 195 AH5416(ah)->ah_writeIni = ar5416WriteIni; 196 AH5416(ah)->ah_spurMitigate = ar5416SpurMitigate; 197 198 /* Internal baseband ops */ 199 AH5416(ah)->ah_initPLL = ar5416InitPLL; 200 201 /* Internal calibration ops */ 202 AH5416(ah)->ah_cal_initcal = ar5416InitCalHardware; 203 204 /* Internal TX power control related operations */ 205 AH5416(ah)->ah_olcInit = ar5416olcInit; 206 AH5416(ah)->ah_olcTempCompensation = ar5416olcTempCompensation; 207 AH5416(ah)->ah_setPowerCalTable = ar5416SetPowerCalTable; 208 209 /* 210 * Start by setting all Owl devices to 2x2 211 */ 212 AH5416(ah)->ah_rx_chainmask = AR5416_DEFAULT_RXCHAINMASK; 213 AH5416(ah)->ah_tx_chainmask = AR5416_DEFAULT_TXCHAINMASK; 214 215 /* Enable all ANI functions to begin with */ 216 AH5416(ah)->ah_ani_function = 0xffffffff; 217 218 /* Set overridable ANI methods */ 219 AH5212(ah)->ah_aniControl = ar5416AniControl; 220 } 221 222 uint32_t 223 ar5416GetRadioRev(struct ath_hal *ah) 224 { 225 uint32_t val; 226 int i; 227 228 /* Read Radio Chip Rev Extract */ 229 OS_REG_WRITE(ah, AR_PHY(0x36), 0x00007058); 230 for (i = 0; i < 8; i++) 231 OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000); 232 val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; 233 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 234 return ath_hal_reverseBits(val, 8); 235 } 236 237 /* 238 * Attach for an AR5416 part. 239 */ 240 static struct ath_hal * 241 ar5416Attach(uint16_t devid, HAL_SOFTC sc, 242 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 243 HAL_STATUS *status) 244 { 245 struct ath_hal_5416 *ahp5416; 246 struct ath_hal_5212 *ahp; 247 struct ath_hal *ah; 248 uint32_t val; 249 HAL_STATUS ecode; 250 HAL_BOOL rfStatus; 251 252 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 253 __func__, sc, (void*) st, (void*) sh); 254 255 /* NB: memory is returned zero'd */ 256 ahp5416 = ath_hal_malloc(sizeof (struct ath_hal_5416) + 257 /* extra space for Owl 2.1/2.2 WAR */ 258 sizeof(ar5416Addac) 259 ); 260 if (ahp5416 == AH_NULL) { 261 HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 262 "%s: cannot allocate memory for state block\n", __func__); 263 *status = HAL_ENOMEM; 264 return AH_NULL; 265 } 266 ar5416InitState(ahp5416, devid, sc, st, sh, status); 267 ahp = &ahp5416->ah_5212; 268 ah = &ahp->ah_priv.h; 269 270 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { 271 /* reset chip */ 272 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", __func__); 273 ecode = HAL_EIO; 274 goto bad; 275 } 276 277 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 278 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", __func__); 279 ecode = HAL_EIO; 280 goto bad; 281 } 282 /* Read Revisions from Chips before taking out of reset */ 283 val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID; 284 AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S; 285 AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION; 286 AH_PRIVATE(ah)->ah_ispcie = (devid == AR5416_DEVID_PCIE); 287 288 /* setup common ini data; rf backends handle remainder */ 289 HAL_INI_INIT(&ahp->ah_ini_modes, ar5416Modes, 6); 290 HAL_INI_INIT(&ahp->ah_ini_common, ar5416Common, 2); 291 292 HAL_INI_INIT(&AH5416(ah)->ah_ini_bb_rfgain, ar5416BB_RfGain, 3); 293 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank0, ar5416Bank0, 2); 294 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank1, ar5416Bank1, 2); 295 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank2, ar5416Bank2, 2); 296 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank3, ar5416Bank3, 3); 297 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank6, ar5416Bank6, 3); 298 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank7, ar5416Bank7, 2); 299 HAL_INI_INIT(&AH5416(ah)->ah_ini_addac, ar5416Addac, 2); 300 301 if (! IS_5416V2_2(ah)) { /* Owl 2.1/2.0 */ 302 ath_hal_printf(ah, "[ath] Enabling CLKDRV workaround for AR5416 < v2.2\n"); 303 struct ini { 304 uint32_t *data; /* NB: !const */ 305 int rows, cols; 306 }; 307 /* override CLKDRV value */ 308 OS_MEMCPY(&AH5416(ah)[1], ar5416Addac, sizeof(ar5416Addac)); 309 AH5416(ah)->ah_ini_addac.data = (uint32_t *) &AH5416(ah)[1]; 310 HAL_INI_VAL((struct ini *)&AH5416(ah)->ah_ini_addac, 31, 1) = 0; 311 } 312 313 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, ar5416PciePhy, 2); 314 ar5416AttachPCIE(ah); 315 316 ecode = ath_hal_v14EepromAttach(ah); 317 if (ecode != HAL_OK) 318 goto bad; 319 320 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */ 321 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", 322 __func__); 323 ecode = HAL_EIO; 324 goto bad; 325 } 326 327 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 328 329 if (!ar5212ChipTest(ah)) { 330 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 331 __func__); 332 ecode = HAL_ESELFTEST; 333 goto bad; 334 } 335 336 /* 337 * Set correct Baseband to analog shift 338 * setting to access analog chips. 339 */ 340 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 341 342 /* Read Radio Chip Rev Extract */ 343 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah); 344 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 345 case AR_RAD5122_SREV_MAJOR: /* Fowl: 5G/2x2 */ 346 case AR_RAD2122_SREV_MAJOR: /* Fowl: 2+5G/2x2 */ 347 case AR_RAD2133_SREV_MAJOR: /* Fowl: 2G/3x3 */ 348 case AR_RAD5133_SREV_MAJOR: /* Fowl: 2+5G/3x3 */ 349 break; 350 default: 351 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 352 /* 353 * When RF_Silen is used the analog chip is reset. 354 * So when the system boots with radio switch off 355 * the RF chip rev reads back as zero and we need 356 * to use the mac+phy revs to set the radio rev. 357 */ 358 AH_PRIVATE(ah)->ah_analog5GhzRev = 359 AR_RAD5133_SREV_MAJOR; 360 break; 361 } 362 /* NB: silently accept anything in release code per Atheros */ 363 #ifdef AH_DEBUG 364 HALDEBUG(ah, HAL_DEBUG_ANY, 365 "%s: 5G Radio Chip Rev 0x%02X is not supported by " 366 "this driver\n", __func__, 367 AH_PRIVATE(ah)->ah_analog5GhzRev); 368 ecode = HAL_ENOTSUPP; 369 goto bad; 370 #endif 371 } 372 373 /* 374 * Got everything we need now to setup the capabilities. 375 */ 376 if (!ar5416FillCapabilityInfo(ah)) { 377 ecode = HAL_EEREAD; 378 goto bad; 379 } 380 381 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 382 if (ecode != HAL_OK) { 383 HALDEBUG(ah, HAL_DEBUG_ANY, 384 "%s: error getting mac address from EEPROM\n", __func__); 385 goto bad; 386 } 387 /* XXX How about the serial number ? */ 388 /* Read Reg Domain */ 389 AH_PRIVATE(ah)->ah_currentRD = 390 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL); 391 AH_PRIVATE(ah)->ah_currentRDext = 392 ath_hal_eepromGet(ah, AR_EEP_REGDMN_1, AH_NULL); 393 394 /* 395 * ah_miscMode is populated by ar5416FillCapabilityInfo() 396 * starting from griffin. Set here to make sure that 397 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is 398 * placed into hardware. 399 */ 400 if (ahp->ah_miscMode != 0) 401 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode); 402 403 rfStatus = ar2133RfAttach(ah, &ecode); 404 if (!rfStatus) { 405 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 406 __func__, ecode); 407 goto bad; 408 } 409 410 ar5416AniSetup(ah); /* Anti Noise Immunity */ 411 412 AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ; 413 AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ; 414 AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ; 415 AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ; 416 AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ; 417 AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ; 418 419 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist); 420 421 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 422 423 return ah; 424 bad: 425 if (ahp) 426 ar5416Detach((struct ath_hal *) ahp); 427 if (status) 428 *status = ecode; 429 return AH_NULL; 430 } 431 432 void 433 ar5416Detach(struct ath_hal *ah) 434 { 435 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__); 436 437 HALASSERT(ah != AH_NULL); 438 HALASSERT(ah->ah_magic == AR5416_MAGIC); 439 440 /* Make sure that chip is awake before writing to it */ 441 if (! ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 442 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, 443 "%s: failed to wake up chip\n", 444 __func__); 445 446 ar5416AniDetach(ah); 447 ar5212RfDetach(ah); 448 ah->ah_disable(ah); 449 ar5416SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); 450 ath_hal_eepromDetach(ah); 451 ath_hal_free(ah); 452 } 453 454 void 455 ar5416AttachPCIE(struct ath_hal *ah) 456 { 457 if (AH_PRIVATE(ah)->ah_ispcie) 458 ath_hal_configPCIE(ah, AH_FALSE); 459 else 460 ath_hal_disablePCIE(ah); 461 } 462 463 static void 464 ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore) 465 { 466 if (AH_PRIVATE(ah)->ah_ispcie && !restore) { 467 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0); 468 OS_DELAY(1000); 469 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 470 OS_REG_WRITE(ah, AR_WA, AR_WA_DEFAULT); 471 } 472 } 473 474 static void 475 ar5416WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan) 476 { 477 u_int modesIndex, freqIndex; 478 int regWrites = 0; 479 480 /* Setup the indices for the next set of register array writes */ 481 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */ 482 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 483 freqIndex = 2; 484 if (IEEE80211_IS_CHAN_HT40(chan)) 485 modesIndex = 3; 486 else if (IEEE80211_IS_CHAN_108G(chan)) 487 modesIndex = 5; 488 else 489 modesIndex = 4; 490 } else { 491 freqIndex = 1; 492 if (IEEE80211_IS_CHAN_HT40(chan) || 493 IEEE80211_IS_CHAN_TURBO(chan)) 494 modesIndex = 2; 495 else 496 modesIndex = 1; 497 } 498 499 /* Set correct Baseband to analog shift setting to access analog chips. */ 500 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 501 502 /* 503 * Write addac shifts 504 */ 505 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); 506 507 /* NB: only required for Sowl */ 508 if (AR_SREV_SOWL(ah)) 509 ar5416EepromSetAddac(ah, chan); 510 511 regWrites = ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_addac, 1, 512 regWrites); 513 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 514 515 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, 516 modesIndex, regWrites); 517 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 518 1, regWrites); 519 520 /* XXX updated regWrites? */ 521 AH5212(ah)->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites); 522 } 523 524 /* 525 * Convert to baseband spur frequency given input channel frequency 526 * and compute register settings below. 527 */ 528 529 static void 530 ar5416SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan) 531 { 532 uint16_t freq = ath_hal_gethwchannel(ah, chan); 533 static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, 534 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 }; 535 static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, 536 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 }; 537 static const int inc[4] = { 0, 100, 0, 0 }; 538 539 int bb_spur = AR_NO_SPUR; 540 int bin, cur_bin; 541 int spur_freq_sd; 542 int spur_delta_phase; 543 int denominator; 544 int upper, lower, cur_vit_mask; 545 int tmp, new; 546 int i; 547 548 int8_t mask_m[123]; 549 int8_t mask_p[123]; 550 int8_t mask_amt; 551 int tmp_mask; 552 int cur_bb_spur; 553 HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 554 555 OS_MEMZERO(mask_m, sizeof(mask_m)); 556 OS_MEMZERO(mask_p, sizeof(mask_p)); 557 558 /* 559 * Need to verify range +/- 9.5 for static ht20, otherwise spur 560 * is out-of-band and can be ignored. 561 */ 562 /* XXX ath9k changes */ 563 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { 564 cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz); 565 if (AR_NO_SPUR == cur_bb_spur) 566 break; 567 cur_bb_spur = cur_bb_spur - (freq * 10); 568 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) { 569 bb_spur = cur_bb_spur; 570 break; 571 } 572 } 573 if (AR_NO_SPUR == bb_spur) 574 return; 575 576 bin = bb_spur * 32; 577 578 tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)); 579 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 580 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 581 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 582 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 583 584 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), new); 585 586 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 587 AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 588 AR_PHY_SPUR_REG_MASK_RATE_SELECT | 589 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 590 SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 591 OS_REG_WRITE(ah, AR_PHY_SPUR_REG, new); 592 /* 593 * Should offset bb_spur by +/- 10 MHz for dynamic 2040 MHz 594 * config, no offset for HT20. 595 * spur_delta_phase = bb_spur/40 * 2**21 for static ht20, 596 * /80 for dyn2040. 597 */ 598 spur_delta_phase = ((bb_spur * 524288) / 100) & 599 AR_PHY_TIMING11_SPUR_DELTA_PHASE; 600 /* 601 * in 11A mode the denominator of spur_freq_sd should be 40 and 602 * it should be 44 in 11G 603 */ 604 denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 440 : 400; 605 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff; 606 607 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 608 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 609 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 610 OS_REG_WRITE(ah, AR_PHY_TIMING11, new); 611 612 613 /* 614 * ============================================ 615 * pilot mask 1 [31:0] = +6..-26, no 0 bin 616 * pilot mask 2 [19:0] = +26..+7 617 * 618 * channel mask 1 [31:0] = +6..-26, no 0 bin 619 * channel mask 2 [19:0] = +26..+7 620 */ 621 //cur_bin = -26; 622 cur_bin = -6000; 623 upper = bin + 100; 624 lower = bin - 100; 625 626 for (i = 0; i < 4; i++) { 627 int pilot_mask = 0; 628 int chan_mask = 0; 629 int bp = 0; 630 for (bp = 0; bp < 30; bp++) { 631 if ((cur_bin > lower) && (cur_bin < upper)) { 632 pilot_mask = pilot_mask | 0x1 << bp; 633 chan_mask = chan_mask | 0x1 << bp; 634 } 635 cur_bin += 100; 636 } 637 cur_bin += inc[i]; 638 OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 639 OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask); 640 } 641 642 /* ================================================= 643 * viterbi mask 1 based on channel magnitude 644 * four levels 0-3 645 * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c) 646 * [1 2 2 1] for -9.6 or [1 2 1] for +16 647 * - enable_mask_ppm, all bins move with freq 648 * 649 * - mask_select, 8 bits for rates (reg 67,0x990c) 650 * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c) 651 * choose which mask to use mask or mask2 652 */ 653 654 /* 655 * viterbi mask 2 2nd set for per data rate puncturing 656 * four levels 0-3 657 * - mask_select, 8 bits for rates (reg 67) 658 * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994) 659 * [1 2 2 1] for -9.6 or [1 2 1] for +16 660 */ 661 cur_vit_mask = 6100; 662 upper = bin + 120; 663 lower = bin - 120; 664 665 for (i = 0; i < 123; i++) { 666 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 667 if ((abs(cur_vit_mask - bin)) < 75) { 668 mask_amt = 1; 669 } else { 670 mask_amt = 0; 671 } 672 if (cur_vit_mask < 0) { 673 mask_m[abs(cur_vit_mask / 100)] = mask_amt; 674 } else { 675 mask_p[cur_vit_mask / 100] = mask_amt; 676 } 677 } 678 cur_vit_mask -= 100; 679 } 680 681 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 682 | (mask_m[48] << 26) | (mask_m[49] << 24) 683 | (mask_m[50] << 22) | (mask_m[51] << 20) 684 | (mask_m[52] << 18) | (mask_m[53] << 16) 685 | (mask_m[54] << 14) | (mask_m[55] << 12) 686 | (mask_m[56] << 10) | (mask_m[57] << 8) 687 | (mask_m[58] << 6) | (mask_m[59] << 4) 688 | (mask_m[60] << 2) | (mask_m[61] << 0); 689 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 690 OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 691 692 tmp_mask = (mask_m[31] << 28) 693 | (mask_m[32] << 26) | (mask_m[33] << 24) 694 | (mask_m[34] << 22) | (mask_m[35] << 20) 695 | (mask_m[36] << 18) | (mask_m[37] << 16) 696 | (mask_m[48] << 14) | (mask_m[39] << 12) 697 | (mask_m[40] << 10) | (mask_m[41] << 8) 698 | (mask_m[42] << 6) | (mask_m[43] << 4) 699 | (mask_m[44] << 2) | (mask_m[45] << 0); 700 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 701 OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 702 703 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 704 | (mask_m[18] << 26) | (mask_m[18] << 24) 705 | (mask_m[20] << 22) | (mask_m[20] << 20) 706 | (mask_m[22] << 18) | (mask_m[22] << 16) 707 | (mask_m[24] << 14) | (mask_m[24] << 12) 708 | (mask_m[25] << 10) | (mask_m[26] << 8) 709 | (mask_m[27] << 6) | (mask_m[28] << 4) 710 | (mask_m[29] << 2) | (mask_m[30] << 0); 711 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 712 OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 713 714 tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28) 715 | (mask_m[ 2] << 26) | (mask_m[ 3] << 24) 716 | (mask_m[ 4] << 22) | (mask_m[ 5] << 20) 717 | (mask_m[ 6] << 18) | (mask_m[ 7] << 16) 718 | (mask_m[ 8] << 14) | (mask_m[ 9] << 12) 719 | (mask_m[10] << 10) | (mask_m[11] << 8) 720 | (mask_m[12] << 6) | (mask_m[13] << 4) 721 | (mask_m[14] << 2) | (mask_m[15] << 0); 722 OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 723 OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 724 725 tmp_mask = (mask_p[15] << 28) 726 | (mask_p[14] << 26) | (mask_p[13] << 24) 727 | (mask_p[12] << 22) | (mask_p[11] << 20) 728 | (mask_p[10] << 18) | (mask_p[ 9] << 16) 729 | (mask_p[ 8] << 14) | (mask_p[ 7] << 12) 730 | (mask_p[ 6] << 10) | (mask_p[ 5] << 8) 731 | (mask_p[ 4] << 6) | (mask_p[ 3] << 4) 732 | (mask_p[ 2] << 2) | (mask_p[ 1] << 0); 733 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 734 OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 735 736 tmp_mask = (mask_p[30] << 28) 737 | (mask_p[29] << 26) | (mask_p[28] << 24) 738 | (mask_p[27] << 22) | (mask_p[26] << 20) 739 | (mask_p[25] << 18) | (mask_p[24] << 16) 740 | (mask_p[23] << 14) | (mask_p[22] << 12) 741 | (mask_p[21] << 10) | (mask_p[20] << 8) 742 | (mask_p[19] << 6) | (mask_p[18] << 4) 743 | (mask_p[17] << 2) | (mask_p[16] << 0); 744 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 745 OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 746 747 tmp_mask = (mask_p[45] << 28) 748 | (mask_p[44] << 26) | (mask_p[43] << 24) 749 | (mask_p[42] << 22) | (mask_p[41] << 20) 750 | (mask_p[40] << 18) | (mask_p[39] << 16) 751 | (mask_p[38] << 14) | (mask_p[37] << 12) 752 | (mask_p[36] << 10) | (mask_p[35] << 8) 753 | (mask_p[34] << 6) | (mask_p[33] << 4) 754 | (mask_p[32] << 2) | (mask_p[31] << 0); 755 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 756 OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 757 758 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 759 | (mask_p[59] << 26) | (mask_p[58] << 24) 760 | (mask_p[57] << 22) | (mask_p[56] << 20) 761 | (mask_p[55] << 18) | (mask_p[54] << 16) 762 | (mask_p[53] << 14) | (mask_p[52] << 12) 763 | (mask_p[51] << 10) | (mask_p[50] << 8) 764 | (mask_p[49] << 6) | (mask_p[48] << 4) 765 | (mask_p[47] << 2) | (mask_p[46] << 0); 766 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 767 OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 768 } 769 770 /* 771 * Fill all software cached or static hardware state information. 772 * Return failure if capabilities are to come from EEPROM and 773 * cannot be read. 774 */ 775 HAL_BOOL 776 ar5416FillCapabilityInfo(struct ath_hal *ah) 777 { 778 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 779 HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 780 uint16_t val; 781 782 /* Construct wireless mode from EEPROM */ 783 pCap->halWirelessModes = 0; 784 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) { 785 pCap->halWirelessModes |= HAL_MODE_11A 786 | HAL_MODE_11NA_HT20 787 | HAL_MODE_11NA_HT40PLUS 788 | HAL_MODE_11NA_HT40MINUS 789 ; 790 } 791 if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE)) { 792 pCap->halWirelessModes |= HAL_MODE_11G 793 | HAL_MODE_11NG_HT20 794 | HAL_MODE_11NG_HT40PLUS 795 | HAL_MODE_11NG_HT40MINUS 796 ; 797 pCap->halWirelessModes |= HAL_MODE_11A 798 | HAL_MODE_11NA_HT20 799 | HAL_MODE_11NA_HT40PLUS 800 | HAL_MODE_11NA_HT40MINUS 801 ; 802 } 803 804 pCap->halLow2GhzChan = 2312; 805 pCap->halHigh2GhzChan = 2732; 806 807 pCap->halLow5GhzChan = 4915; 808 pCap->halHigh5GhzChan = 6100; 809 810 pCap->halCipherCkipSupport = AH_FALSE; 811 pCap->halCipherTkipSupport = AH_TRUE; 812 pCap->halCipherAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 813 814 pCap->halMicCkipSupport = AH_FALSE; 815 pCap->halMicTkipSupport = AH_TRUE; 816 pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 817 /* 818 * Starting with Griffin TX+RX mic keys can be combined 819 * in one key cache slot. 820 */ 821 pCap->halTkipMicTxRxKeySupport = AH_TRUE; 822 pCap->halChanSpreadSupport = AH_TRUE; 823 pCap->halSleepAfterBeaconBroken = AH_TRUE; 824 825 pCap->halCompressSupport = AH_FALSE; 826 pCap->halBurstSupport = AH_TRUE; 827 pCap->halFastFramesSupport = AH_FALSE; /* XXX? */ 828 pCap->halChapTuningSupport = AH_TRUE; 829 pCap->halTurboPrimeSupport = AH_TRUE; 830 831 pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G; 832 833 pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */ 834 pCap->halVEOLSupport = AH_TRUE; 835 pCap->halBssIdMaskSupport = AH_TRUE; 836 pCap->halMcastKeySrchSupport = AH_TRUE; /* Works on AR5416 and later */ 837 pCap->halTsfAddSupport = AH_TRUE; 838 pCap->hal4AddrAggrSupport = AH_FALSE; /* Broken in Owl */ 839 840 if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK) 841 pCap->halTotalQueues = val; 842 else 843 pCap->halTotalQueues = HAL_NUM_TX_QUEUES; 844 845 if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK) 846 pCap->halKeyCacheSize = val; 847 else 848 pCap->halKeyCacheSize = AR5416_KEYTABLE_SIZE; 849 850 /* XXX not needed */ 851 pCap->halChanHalfRate = AH_FALSE; /* XXX ? */ 852 pCap->halChanQuarterRate = AH_FALSE; /* XXX ? */ 853 854 pCap->halTstampPrecision = 32; 855 pCap->halHwPhyCounterSupport = AH_TRUE; 856 pCap->halIntrMask = HAL_INT_COMMON 857 | HAL_INT_RX 858 | HAL_INT_TX 859 | HAL_INT_FATAL 860 | HAL_INT_BNR 861 | HAL_INT_BMISC 862 | HAL_INT_DTIMSYNC 863 | HAL_INT_TSFOOR 864 | HAL_INT_CST 865 | HAL_INT_GTT 866 ; 867 868 pCap->halFastCCSupport = AH_TRUE; 869 pCap->halNumGpioPins = 14; 870 pCap->halWowSupport = AH_FALSE; 871 pCap->halWowMatchPatternExact = AH_FALSE; 872 pCap->halBtCoexSupport = AH_FALSE; /* XXX need support */ 873 pCap->halAutoSleepSupport = AH_FALSE; 874 pCap->hal4kbSplitTransSupport = AH_TRUE; 875 /* Disable this so Block-ACK works correctly */ 876 pCap->halHasRxSelfLinkedTail = AH_FALSE; 877 #if 0 /* XXX not yet */ 878 pCap->halNumAntCfg2GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_2GHZ); 879 pCap->halNumAntCfg5GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_5GHZ); 880 #endif 881 pCap->halHTSupport = AH_TRUE; 882 pCap->halTxChainMask = ath_hal_eepromGet(ah, AR_EEP_TXMASK, AH_NULL); 883 /* XXX CB71 uses GPIO 0 to indicate 3 rx chains */ 884 pCap->halRxChainMask = ath_hal_eepromGet(ah, AR_EEP_RXMASK, AH_NULL); 885 /* AR5416 may have 3 antennas but is a 2x2 stream device */ 886 pCap->halTxStreams = 2; 887 pCap->halRxStreams = 2; 888 889 /* 890 * If the TX or RX chainmask has less than 2 chains active, 891 * mark it as a 1-stream device for the relevant stream. 892 */ 893 if (owl_get_ntxchains(pCap->halTxChainMask) == 1) 894 pCap->halTxStreams = 1; 895 /* XXX Eww */ 896 if (owl_get_ntxchains(pCap->halRxChainMask) == 1) 897 pCap->halRxStreams = 1; 898 pCap->halRtsAggrLimit = 8*1024; /* Owl 2.0 limit */ 899 pCap->halMbssidAggrSupport = AH_FALSE; /* Broken on Owl */ 900 pCap->halForcePpmSupport = AH_TRUE; 901 pCap->halEnhancedPmSupport = AH_TRUE; 902 pCap->halBssidMatchSupport = AH_TRUE; 903 pCap->halGTTSupport = AH_TRUE; 904 pCap->halCSTSupport = AH_TRUE; 905 pCap->halEnhancedDfsSupport = AH_FALSE; 906 /* Hardware supports 32 bit TSF values in the RX descriptor */ 907 pCap->halHasLongRxDescTsf = AH_TRUE; 908 /* 909 * BB Read WAR: this is only for AR5008/AR9001 NICs 910 * It is also set individually in the AR91xx attach functions. 911 */ 912 if (AR_SREV_OWL(ah)) 913 pCap->halHasBBReadWar = AH_TRUE; 914 915 if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) && 916 ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) { 917 /* NB: enabled by default */ 918 ahpriv->ah_rfkillEnabled = AH_TRUE; 919 pCap->halRfSilentSupport = AH_TRUE; 920 } 921 922 /* 923 * The MAC will mark frames as RXed if there's a descriptor 924 * to write them to. So if it hits a self-linked final descriptor, 925 * it'll keep ACKing frames even though they're being silently 926 * dropped. Thus, this particular feature of the driver can't 927 * be used for 802.11n devices. 928 */ 929 ahpriv->ah_rxornIsFatal = AH_FALSE; 930 931 /* 932 * If it's a PCI NIC, ask the HAL OS layer to serialise 933 * register access, or SMP machines may cause the hardware 934 * to hang. This is applicable to AR5416 and AR9220; I'm not 935 * sure about AR9160 or AR9227. 936 */ 937 if (! AH_PRIVATE(ah)->ah_ispcie) 938 pCap->halSerialiseRegWar = 1; 939 940 return AH_TRUE; 941 } 942 943 static const char* 944 ar5416Probe(uint16_t vendorid, uint16_t devid) 945 { 946 if (vendorid == ATHEROS_VENDOR_ID) { 947 if (devid == AR5416_DEVID_PCI) 948 return "Atheros 5416"; 949 if (devid == AR5416_DEVID_PCIE) 950 return "Atheros 5418"; 951 } 952 return AH_NULL; 953 } 954 AH_CHIP(AR5416, ar5416Probe, ar5416Attach); 955