1 /* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19 #include "opt_ah.h" 20 21 #include "ah.h" 22 #include "ah_internal.h" 23 #include "ah_devid.h" 24 25 #include "ah_eeprom_v14.h" 26 27 #include "ar5416/ar5416.h" 28 #include "ar5416/ar5416reg.h" 29 #include "ar5416/ar5416phy.h" 30 31 #include "ar5416/ar5416.ini" 32 33 static void ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, 34 HAL_BOOL power_off); 35 static void ar5416DisablePCIE(struct ath_hal *ah); 36 static void ar5416WriteIni(struct ath_hal *ah, 37 const struct ieee80211_channel *chan); 38 static void ar5416SpurMitigate(struct ath_hal *ah, 39 const struct ieee80211_channel *chan); 40 41 static void 42 ar5416AniSetup(struct ath_hal *ah) 43 { 44 static const struct ar5212AniParams aniparams = { 45 .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 46 .totalSizeDesired = { -55, -55, -55, -55, -62 }, 47 .coarseHigh = { -14, -14, -14, -14, -12 }, 48 .coarseLow = { -64, -64, -64, -64, -70 }, 49 .firpwr = { -78, -78, -78, -78, -80 }, 50 .maxSpurImmunityLevel = 7, 51 .cycPwrThr1 = { 2, 4, 6, 8, 10, 12, 14, 16 }, 52 .maxFirstepLevel = 2, /* levels 0..2 */ 53 .firstep = { 0, 4, 8 }, 54 .ofdmTrigHigh = 500, 55 .ofdmTrigLow = 200, 56 .cckTrigHigh = 200, 57 .cckTrigLow = 100, 58 .rssiThrHigh = 40, 59 .rssiThrLow = 7, 60 .period = 100, 61 }; 62 /* NB: disable ANI noise immmunity for reliable RIFS rx */ 63 AH5416(ah)->ah_ani_function &= ~(1 << HAL_ANI_NOISE_IMMUNITY_LEVEL); 64 ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE); 65 } 66 67 /* 68 * AR5416 doesn't do OLC or temperature compensation. 69 */ 70 static void 71 ar5416olcInit(struct ath_hal *ah) 72 { 73 } 74 75 static void 76 ar5416olcTempCompensation(struct ath_hal *ah) 77 { 78 } 79 80 /* 81 * Attach for an AR5416 part. 82 */ 83 void 84 ar5416InitState(struct ath_hal_5416 *ahp5416, uint16_t devid, HAL_SOFTC sc, 85 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status) 86 { 87 struct ath_hal_5212 *ahp; 88 struct ath_hal *ah; 89 90 ahp = &ahp5416->ah_5212; 91 ar5212InitState(ahp, devid, sc, st, sh, status); 92 ah = &ahp->ah_priv.h; 93 94 /* override 5212 methods for our needs */ 95 ah->ah_magic = AR5416_MAGIC; 96 ah->ah_getRateTable = ar5416GetRateTable; 97 ah->ah_detach = ar5416Detach; 98 99 /* Reset functions */ 100 ah->ah_reset = ar5416Reset; 101 ah->ah_phyDisable = ar5416PhyDisable; 102 ah->ah_disable = ar5416Disable; 103 ah->ah_configPCIE = ar5416ConfigPCIE; 104 ah->ah_disablePCIE = ar5416DisablePCIE; 105 ah->ah_perCalibration = ar5416PerCalibration; 106 ah->ah_perCalibrationN = ar5416PerCalibrationN, 107 ah->ah_resetCalValid = ar5416ResetCalValid, 108 ah->ah_setTxPowerLimit = ar5416SetTxPowerLimit; 109 ah->ah_setTxPower = ar5416SetTransmitPower; 110 ah->ah_setBoardValues = ar5416SetBoardValues; 111 112 /* Transmit functions */ 113 ah->ah_stopTxDma = ar5416StopTxDma; 114 ah->ah_setupTxDesc = ar5416SetupTxDesc; 115 ah->ah_setupXTxDesc = ar5416SetupXTxDesc; 116 ah->ah_fillTxDesc = ar5416FillTxDesc; 117 ah->ah_procTxDesc = ar5416ProcTxDesc; 118 ah->ah_getTxCompletionRates = ar5416GetTxCompletionRates; 119 ah->ah_setupTxQueue = ar5416SetupTxQueue; 120 ah->ah_resetTxQueue = ar5416ResetTxQueue; 121 122 /* Receive Functions */ 123 ah->ah_getRxFilter = ar5416GetRxFilter; 124 ah->ah_setRxFilter = ar5416SetRxFilter; 125 ah->ah_stopDmaReceive = ar5416StopDmaReceive; 126 ah->ah_startPcuReceive = ar5416StartPcuReceive; 127 ah->ah_stopPcuReceive = ar5416StopPcuReceive; 128 ah->ah_setupRxDesc = ar5416SetupRxDesc; 129 ah->ah_procRxDesc = ar5416ProcRxDesc; 130 ah->ah_rxMonitor = ar5416RxMonitor; 131 ah->ah_aniPoll = ar5416AniPoll; 132 ah->ah_procMibEvent = ar5416ProcessMibIntr; 133 134 /* Misc Functions */ 135 ah->ah_getCapability = ar5416GetCapability; 136 ah->ah_setCapability = ar5416SetCapability; 137 ah->ah_getDiagState = ar5416GetDiagState; 138 ah->ah_setLedState = ar5416SetLedState; 139 ah->ah_gpioCfgOutput = ar5416GpioCfgOutput; 140 ah->ah_gpioCfgInput = ar5416GpioCfgInput; 141 ah->ah_gpioGet = ar5416GpioGet; 142 ah->ah_gpioSet = ar5416GpioSet; 143 ah->ah_gpioSetIntr = ar5416GpioSetIntr; 144 ah->ah_getTsf64 = ar5416GetTsf64; 145 ah->ah_setTsf64 = ar5416SetTsf64; 146 ah->ah_resetTsf = ar5416ResetTsf; 147 ah->ah_getRfGain = ar5416GetRfgain; 148 ah->ah_setAntennaSwitch = ar5416SetAntennaSwitch; 149 ah->ah_setDecompMask = ar5416SetDecompMask; 150 ah->ah_setCoverageClass = ar5416SetCoverageClass; 151 ah->ah_setQuiet = ar5416SetQuiet; 152 ah->ah_getMibCycleCounts = ar5416GetMibCycleCounts; 153 154 ah->ah_resetKeyCacheEntry = ar5416ResetKeyCacheEntry; 155 ah->ah_setKeyCacheEntry = ar5416SetKeyCacheEntry; 156 157 /* DFS Functions */ 158 ah->ah_enableDfs = ar5416EnableDfs; 159 ah->ah_getDfsThresh = ar5416GetDfsThresh; 160 ah->ah_getDfsDefaultThresh = ar5416GetDfsDefaultThresh; 161 ah->ah_procRadarEvent = ar5416ProcessRadarEvent; 162 ah->ah_isFastClockEnabled = ar5416IsFastClockEnabled; 163 164 /* Power Management Functions */ 165 ah->ah_setPowerMode = ar5416SetPowerMode; 166 167 /* Beacon Management Functions */ 168 ah->ah_setBeaconTimers = ar5416SetBeaconTimers; 169 ah->ah_beaconInit = ar5416BeaconInit; 170 ah->ah_setStationBeaconTimers = ar5416SetStaBeaconTimers; 171 ah->ah_resetStationBeaconTimers = ar5416ResetStaBeaconTimers; 172 ah->ah_getNextTBTT = ar5416GetNextTBTT; 173 174 /* 802.11n Functions */ 175 ah->ah_chainTxDesc = ar5416ChainTxDesc; 176 ah->ah_setupFirstTxDesc = ar5416SetupFirstTxDesc; 177 ah->ah_setupLastTxDesc = ar5416SetupLastTxDesc; 178 ah->ah_set11nRateScenario = ar5416Set11nRateScenario; 179 ah->ah_set11nAggrFirst = ar5416Set11nAggrFirst; 180 ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle; 181 ah->ah_set11nAggrLast = ar5416Set11nAggrLast; 182 ah->ah_clr11nAggr = ar5416Clr11nAggr; 183 ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration; 184 ah->ah_get11nExtBusy = ar5416Get11nExtBusy; 185 ah->ah_set11nMac2040 = ar5416Set11nMac2040; 186 ah->ah_get11nRxClear = ar5416Get11nRxClear; 187 ah->ah_set11nRxClear = ar5416Set11nRxClear; 188 189 /* Interrupt functions */ 190 ah->ah_isInterruptPending = ar5416IsInterruptPending; 191 ah->ah_getPendingInterrupts = ar5416GetPendingInterrupts; 192 ah->ah_setInterrupts = ar5416SetInterrupts; 193 194 /* Bluetooth Coexistence functions */ 195 ah->ah_btCoexSetInfo = ar5416SetBTCoexInfo; 196 ah->ah_btCoexSetConfig = ar5416BTCoexConfig; 197 ah->ah_btCoexSetQcuThresh = ar5416BTCoexSetQcuThresh; 198 ah->ah_btCoexSetWeights = ar5416BTCoexSetWeights; 199 ah->ah_btCoexSetBmissThresh = ar5416BTCoexSetupBmissThresh; 200 ah->ah_btcoexSetParameter = ar5416BTCoexSetParameter; 201 ah->ah_btCoexDisable = ar5416BTCoexDisable; 202 ah->ah_btCoexEnable = ar5416BTCoexEnable; 203 AH5416(ah)->ah_btCoexSetDiversity = ar5416BTCoexAntennaDiversity; 204 205 ahp->ah_priv.ah_getWirelessModes= ar5416GetWirelessModes; 206 ahp->ah_priv.ah_eepromRead = ar5416EepromRead; 207 #ifdef AH_SUPPORT_WRITE_EEPROM 208 ahp->ah_priv.ah_eepromWrite = ar5416EepromWrite; 209 #endif 210 ahp->ah_priv.ah_getChipPowerLimits = ar5416GetChipPowerLimits; 211 212 /* Internal ops */ 213 AH5416(ah)->ah_writeIni = ar5416WriteIni; 214 AH5416(ah)->ah_spurMitigate = ar5416SpurMitigate; 215 216 /* Internal baseband ops */ 217 AH5416(ah)->ah_initPLL = ar5416InitPLL; 218 219 /* Internal calibration ops */ 220 AH5416(ah)->ah_cal_initcal = ar5416InitCalHardware; 221 222 /* Internal TX power control related operations */ 223 AH5416(ah)->ah_olcInit = ar5416olcInit; 224 AH5416(ah)->ah_olcTempCompensation = ar5416olcTempCompensation; 225 AH5416(ah)->ah_setPowerCalTable = ar5416SetPowerCalTable; 226 227 /* 228 * Start by setting all Owl devices to 2x2 229 */ 230 AH5416(ah)->ah_rx_chainmask = AR5416_DEFAULT_RXCHAINMASK; 231 AH5416(ah)->ah_tx_chainmask = AR5416_DEFAULT_TXCHAINMASK; 232 233 /* Enable all ANI functions to begin with */ 234 AH5416(ah)->ah_ani_function = 0xffffffff; 235 236 /* Set overridable ANI methods */ 237 AH5212(ah)->ah_aniControl = ar5416AniControl; 238 } 239 240 uint32_t 241 ar5416GetRadioRev(struct ath_hal *ah) 242 { 243 uint32_t val; 244 int i; 245 246 /* Read Radio Chip Rev Extract */ 247 OS_REG_WRITE(ah, AR_PHY(0x36), 0x00007058); 248 for (i = 0; i < 8; i++) 249 OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000); 250 val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; 251 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 252 return ath_hal_reverseBits(val, 8); 253 } 254 255 /* 256 * Attach for an AR5416 part. 257 */ 258 static struct ath_hal * 259 ar5416Attach(uint16_t devid, HAL_SOFTC sc, 260 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 261 HAL_STATUS *status) 262 { 263 struct ath_hal_5416 *ahp5416; 264 struct ath_hal_5212 *ahp; 265 struct ath_hal *ah; 266 uint32_t val; 267 HAL_STATUS ecode; 268 HAL_BOOL rfStatus; 269 270 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 271 __func__, sc, (void*) st, (void*) sh); 272 273 /* NB: memory is returned zero'd */ 274 ahp5416 = ath_hal_malloc(sizeof (struct ath_hal_5416) + 275 /* extra space for Owl 2.1/2.2 WAR */ 276 sizeof(ar5416Addac) 277 ); 278 if (ahp5416 == AH_NULL) { 279 HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 280 "%s: cannot allocate memory for state block\n", __func__); 281 *status = HAL_ENOMEM; 282 return AH_NULL; 283 } 284 ar5416InitState(ahp5416, devid, sc, st, sh, status); 285 ahp = &ahp5416->ah_5212; 286 ah = &ahp->ah_priv.h; 287 288 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { 289 /* reset chip */ 290 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", __func__); 291 ecode = HAL_EIO; 292 goto bad; 293 } 294 295 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 296 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", __func__); 297 ecode = HAL_EIO; 298 goto bad; 299 } 300 /* Read Revisions from Chips before taking out of reset */ 301 val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID; 302 AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S; 303 AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION; 304 AH_PRIVATE(ah)->ah_ispcie = (devid == AR5416_DEVID_PCIE); 305 306 /* setup common ini data; rf backends handle remainder */ 307 HAL_INI_INIT(&ahp->ah_ini_modes, ar5416Modes, 6); 308 HAL_INI_INIT(&ahp->ah_ini_common, ar5416Common, 2); 309 310 HAL_INI_INIT(&AH5416(ah)->ah_ini_bb_rfgain, ar5416BB_RfGain, 3); 311 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank0, ar5416Bank0, 2); 312 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank1, ar5416Bank1, 2); 313 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank2, ar5416Bank2, 2); 314 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank3, ar5416Bank3, 3); 315 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank6, ar5416Bank6, 3); 316 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank7, ar5416Bank7, 2); 317 HAL_INI_INIT(&AH5416(ah)->ah_ini_addac, ar5416Addac, 2); 318 319 if (! IS_5416V2_2(ah)) { /* Owl 2.1/2.0 */ 320 ath_hal_printf(ah, "[ath] Enabling CLKDRV workaround for AR5416 < v2.2\n"); 321 struct ini { 322 uint32_t *data; /* NB: !const */ 323 int rows, cols; 324 }; 325 /* override CLKDRV value */ 326 OS_MEMCPY(&AH5416(ah)[1], ar5416Addac, sizeof(ar5416Addac)); 327 AH5416(ah)->ah_ini_addac.data = (uint32_t *) &AH5416(ah)[1]; 328 HAL_INI_VAL((struct ini *)&AH5416(ah)->ah_ini_addac, 31, 1) = 0; 329 } 330 331 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, ar5416PciePhy, 2); 332 ar5416AttachPCIE(ah); 333 334 ecode = ath_hal_v14EepromAttach(ah); 335 if (ecode != HAL_OK) 336 goto bad; 337 338 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */ 339 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", 340 __func__); 341 ecode = HAL_EIO; 342 goto bad; 343 } 344 345 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 346 347 if (!ar5212ChipTest(ah)) { 348 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 349 __func__); 350 ecode = HAL_ESELFTEST; 351 goto bad; 352 } 353 354 /* 355 * Set correct Baseband to analog shift 356 * setting to access analog chips. 357 */ 358 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 359 360 /* Read Radio Chip Rev Extract */ 361 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah); 362 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 363 case AR_RAD5122_SREV_MAJOR: /* Fowl: 5G/2x2 */ 364 case AR_RAD2122_SREV_MAJOR: /* Fowl: 2+5G/2x2 */ 365 case AR_RAD2133_SREV_MAJOR: /* Fowl: 2G/3x3 */ 366 case AR_RAD5133_SREV_MAJOR: /* Fowl: 2+5G/3x3 */ 367 break; 368 default: 369 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 370 /* 371 * When RF_Silen is used the analog chip is reset. 372 * So when the system boots with radio switch off 373 * the RF chip rev reads back as zero and we need 374 * to use the mac+phy revs to set the radio rev. 375 */ 376 AH_PRIVATE(ah)->ah_analog5GhzRev = 377 AR_RAD5133_SREV_MAJOR; 378 break; 379 } 380 /* NB: silently accept anything in release code per Atheros */ 381 #ifdef AH_DEBUG 382 HALDEBUG(ah, HAL_DEBUG_ANY, 383 "%s: 5G Radio Chip Rev 0x%02X is not supported by " 384 "this driver\n", __func__, 385 AH_PRIVATE(ah)->ah_analog5GhzRev); 386 ecode = HAL_ENOTSUPP; 387 goto bad; 388 #endif 389 } 390 391 /* 392 * Got everything we need now to setup the capabilities. 393 */ 394 if (!ar5416FillCapabilityInfo(ah)) { 395 ecode = HAL_EEREAD; 396 goto bad; 397 } 398 399 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 400 if (ecode != HAL_OK) { 401 HALDEBUG(ah, HAL_DEBUG_ANY, 402 "%s: error getting mac address from EEPROM\n", __func__); 403 goto bad; 404 } 405 /* XXX How about the serial number ? */ 406 /* Read Reg Domain */ 407 AH_PRIVATE(ah)->ah_currentRD = 408 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL); 409 AH_PRIVATE(ah)->ah_currentRDext = 410 ath_hal_eepromGet(ah, AR_EEP_REGDMN_1, AH_NULL); 411 412 /* 413 * ah_miscMode is populated by ar5416FillCapabilityInfo() 414 * starting from griffin. Set here to make sure that 415 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is 416 * placed into hardware. 417 */ 418 if (ahp->ah_miscMode != 0) 419 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode); 420 421 rfStatus = ar2133RfAttach(ah, &ecode); 422 if (!rfStatus) { 423 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 424 __func__, ecode); 425 goto bad; 426 } 427 428 ar5416AniSetup(ah); /* Anti Noise Immunity */ 429 430 AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ; 431 AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ; 432 AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ; 433 AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ; 434 AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ; 435 AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ; 436 437 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist); 438 439 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 440 441 return ah; 442 bad: 443 if (ahp) 444 ar5416Detach((struct ath_hal *) ahp); 445 if (status) 446 *status = ecode; 447 return AH_NULL; 448 } 449 450 void 451 ar5416Detach(struct ath_hal *ah) 452 { 453 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__); 454 455 HALASSERT(ah != AH_NULL); 456 HALASSERT(ah->ah_magic == AR5416_MAGIC); 457 458 /* Make sure that chip is awake before writing to it */ 459 if (! ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 460 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, 461 "%s: failed to wake up chip\n", 462 __func__); 463 464 ar5416AniDetach(ah); 465 ar5212RfDetach(ah); 466 ah->ah_disable(ah); 467 ar5416SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); 468 ath_hal_eepromDetach(ah); 469 ath_hal_free(ah); 470 } 471 472 void 473 ar5416AttachPCIE(struct ath_hal *ah) 474 { 475 if (AH_PRIVATE(ah)->ah_ispcie) 476 ath_hal_configPCIE(ah, AH_FALSE, AH_FALSE); 477 else 478 ath_hal_disablePCIE(ah); 479 } 480 481 static void 482 ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off) 483 { 484 485 /* This is only applicable for AR5418 (AR5416 PCIe) */ 486 if (! AH_PRIVATE(ah)->ah_ispcie) 487 return; 488 489 if (! restore) { 490 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0); 491 OS_DELAY(1000); 492 } 493 494 if (power_off) { /* Power-off */ 495 /* clear bit 19 to disable L1 */ 496 OS_REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 497 } else { /* Power-on */ 498 /* Set default WAR values for Owl */ 499 OS_REG_WRITE(ah, AR_WA, AR_WA_DEFAULT); 500 501 /* set bit 19 to allow forcing of pcie core into L1 state */ 502 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 503 } 504 } 505 506 /* 507 * Disable PCIe PHY if PCIe isn't used. 508 */ 509 static void 510 ar5416DisablePCIE(struct ath_hal *ah) 511 { 512 513 /* PCIe? Don't */ 514 if (AH_PRIVATE(ah)->ah_ispcie) 515 return; 516 517 /* .. Only applicable for AR5416v2 or later */ 518 if (! (AR_SREV_OWL(ah) && AR_SREV_OWL_20_OR_LATER(ah))) 519 return; 520 521 OS_REG_WRITE_BUFFER_ENABLE(ah); 522 523 /* 524 * Disable the PCIe PHY. 525 */ 526 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 527 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 528 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 529 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); 530 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); 531 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); 532 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 533 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 534 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 535 536 /* Load the new settings */ 537 OS_REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 538 539 OS_REG_WRITE_BUFFER_FLUSH(ah); 540 OS_REG_WRITE_BUFFER_DISABLE(ah); 541 } 542 543 static void 544 ar5416WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan) 545 { 546 u_int modesIndex, freqIndex; 547 int regWrites = 0; 548 549 /* Setup the indices for the next set of register array writes */ 550 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */ 551 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 552 freqIndex = 2; 553 if (IEEE80211_IS_CHAN_HT40(chan)) 554 modesIndex = 3; 555 else if (IEEE80211_IS_CHAN_108G(chan)) 556 modesIndex = 5; 557 else 558 modesIndex = 4; 559 } else { 560 freqIndex = 1; 561 if (IEEE80211_IS_CHAN_HT40(chan) || 562 IEEE80211_IS_CHAN_TURBO(chan)) 563 modesIndex = 2; 564 else 565 modesIndex = 1; 566 } 567 568 /* Set correct Baseband to analog shift setting to access analog chips. */ 569 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 570 571 /* 572 * Write addac shifts 573 */ 574 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); 575 576 /* NB: only required for Sowl */ 577 if (AR_SREV_SOWL(ah)) 578 ar5416EepromSetAddac(ah, chan); 579 580 regWrites = ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_addac, 1, 581 regWrites); 582 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 583 584 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, 585 modesIndex, regWrites); 586 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 587 1, regWrites); 588 589 /* XXX updated regWrites? */ 590 AH5212(ah)->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites); 591 } 592 593 /* 594 * Convert to baseband spur frequency given input channel frequency 595 * and compute register settings below. 596 */ 597 598 static void 599 ar5416SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan) 600 { 601 uint16_t freq = ath_hal_gethwchannel(ah, chan); 602 static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, 603 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 }; 604 static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, 605 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 }; 606 static const int inc[4] = { 0, 100, 0, 0 }; 607 608 int bb_spur = AR_NO_SPUR; 609 int bin, cur_bin; 610 int spur_freq_sd; 611 int spur_delta_phase; 612 int denominator; 613 int upper, lower, cur_vit_mask; 614 int tmp, new; 615 int i; 616 617 int8_t mask_m[123]; 618 int8_t mask_p[123]; 619 int8_t mask_amt; 620 int tmp_mask; 621 int cur_bb_spur; 622 HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 623 624 OS_MEMZERO(mask_m, sizeof(mask_m)); 625 OS_MEMZERO(mask_p, sizeof(mask_p)); 626 627 /* 628 * Need to verify range +/- 9.5 for static ht20, otherwise spur 629 * is out-of-band and can be ignored. 630 */ 631 /* XXX ath9k changes */ 632 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { 633 cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz); 634 if (AR_NO_SPUR == cur_bb_spur) 635 break; 636 cur_bb_spur = cur_bb_spur - (freq * 10); 637 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) { 638 bb_spur = cur_bb_spur; 639 break; 640 } 641 } 642 if (AR_NO_SPUR == bb_spur) 643 return; 644 645 bin = bb_spur * 32; 646 647 tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)); 648 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 649 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 650 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 651 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 652 653 OS_REG_WRITE_BUFFER_ENABLE(ah); 654 655 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), new); 656 657 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 658 AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 659 AR_PHY_SPUR_REG_MASK_RATE_SELECT | 660 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 661 SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 662 OS_REG_WRITE(ah, AR_PHY_SPUR_REG, new); 663 /* 664 * Should offset bb_spur by +/- 10 MHz for dynamic 2040 MHz 665 * config, no offset for HT20. 666 * spur_delta_phase = bb_spur/40 * 2**21 for static ht20, 667 * /80 for dyn2040. 668 */ 669 spur_delta_phase = ((bb_spur * 524288) / 100) & 670 AR_PHY_TIMING11_SPUR_DELTA_PHASE; 671 /* 672 * in 11A mode the denominator of spur_freq_sd should be 40 and 673 * it should be 44 in 11G 674 */ 675 denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 440 : 400; 676 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff; 677 678 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 679 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 680 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 681 OS_REG_WRITE(ah, AR_PHY_TIMING11, new); 682 683 684 /* 685 * ============================================ 686 * pilot mask 1 [31:0] = +6..-26, no 0 bin 687 * pilot mask 2 [19:0] = +26..+7 688 * 689 * channel mask 1 [31:0] = +6..-26, no 0 bin 690 * channel mask 2 [19:0] = +26..+7 691 */ 692 //cur_bin = -26; 693 cur_bin = -6000; 694 upper = bin + 100; 695 lower = bin - 100; 696 697 for (i = 0; i < 4; i++) { 698 int pilot_mask = 0; 699 int chan_mask = 0; 700 int bp = 0; 701 for (bp = 0; bp < 30; bp++) { 702 if ((cur_bin > lower) && (cur_bin < upper)) { 703 pilot_mask = pilot_mask | 0x1 << bp; 704 chan_mask = chan_mask | 0x1 << bp; 705 } 706 cur_bin += 100; 707 } 708 cur_bin += inc[i]; 709 OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 710 OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask); 711 } 712 713 /* ================================================= 714 * viterbi mask 1 based on channel magnitude 715 * four levels 0-3 716 * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c) 717 * [1 2 2 1] for -9.6 or [1 2 1] for +16 718 * - enable_mask_ppm, all bins move with freq 719 * 720 * - mask_select, 8 bits for rates (reg 67,0x990c) 721 * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c) 722 * choose which mask to use mask or mask2 723 */ 724 725 /* 726 * viterbi mask 2 2nd set for per data rate puncturing 727 * four levels 0-3 728 * - mask_select, 8 bits for rates (reg 67) 729 * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994) 730 * [1 2 2 1] for -9.6 or [1 2 1] for +16 731 */ 732 cur_vit_mask = 6100; 733 upper = bin + 120; 734 lower = bin - 120; 735 736 for (i = 0; i < 123; i++) { 737 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 738 if ((abs(cur_vit_mask - bin)) < 75) { 739 mask_amt = 1; 740 } else { 741 mask_amt = 0; 742 } 743 if (cur_vit_mask < 0) { 744 mask_m[abs(cur_vit_mask / 100)] = mask_amt; 745 } else { 746 mask_p[cur_vit_mask / 100] = mask_amt; 747 } 748 } 749 cur_vit_mask -= 100; 750 } 751 752 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 753 | (mask_m[48] << 26) | (mask_m[49] << 24) 754 | (mask_m[50] << 22) | (mask_m[51] << 20) 755 | (mask_m[52] << 18) | (mask_m[53] << 16) 756 | (mask_m[54] << 14) | (mask_m[55] << 12) 757 | (mask_m[56] << 10) | (mask_m[57] << 8) 758 | (mask_m[58] << 6) | (mask_m[59] << 4) 759 | (mask_m[60] << 2) | (mask_m[61] << 0); 760 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 761 OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 762 763 tmp_mask = (mask_m[31] << 28) 764 | (mask_m[32] << 26) | (mask_m[33] << 24) 765 | (mask_m[34] << 22) | (mask_m[35] << 20) 766 | (mask_m[36] << 18) | (mask_m[37] << 16) 767 | (mask_m[48] << 14) | (mask_m[39] << 12) 768 | (mask_m[40] << 10) | (mask_m[41] << 8) 769 | (mask_m[42] << 6) | (mask_m[43] << 4) 770 | (mask_m[44] << 2) | (mask_m[45] << 0); 771 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 772 OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 773 774 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 775 | (mask_m[18] << 26) | (mask_m[18] << 24) 776 | (mask_m[20] << 22) | (mask_m[20] << 20) 777 | (mask_m[22] << 18) | (mask_m[22] << 16) 778 | (mask_m[24] << 14) | (mask_m[24] << 12) 779 | (mask_m[25] << 10) | (mask_m[26] << 8) 780 | (mask_m[27] << 6) | (mask_m[28] << 4) 781 | (mask_m[29] << 2) | (mask_m[30] << 0); 782 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 783 OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 784 785 tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28) 786 | (mask_m[ 2] << 26) | (mask_m[ 3] << 24) 787 | (mask_m[ 4] << 22) | (mask_m[ 5] << 20) 788 | (mask_m[ 6] << 18) | (mask_m[ 7] << 16) 789 | (mask_m[ 8] << 14) | (mask_m[ 9] << 12) 790 | (mask_m[10] << 10) | (mask_m[11] << 8) 791 | (mask_m[12] << 6) | (mask_m[13] << 4) 792 | (mask_m[14] << 2) | (mask_m[15] << 0); 793 OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 794 OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 795 796 tmp_mask = (mask_p[15] << 28) 797 | (mask_p[14] << 26) | (mask_p[13] << 24) 798 | (mask_p[12] << 22) | (mask_p[11] << 20) 799 | (mask_p[10] << 18) | (mask_p[ 9] << 16) 800 | (mask_p[ 8] << 14) | (mask_p[ 7] << 12) 801 | (mask_p[ 6] << 10) | (mask_p[ 5] << 8) 802 | (mask_p[ 4] << 6) | (mask_p[ 3] << 4) 803 | (mask_p[ 2] << 2) | (mask_p[ 1] << 0); 804 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 805 OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 806 807 tmp_mask = (mask_p[30] << 28) 808 | (mask_p[29] << 26) | (mask_p[28] << 24) 809 | (mask_p[27] << 22) | (mask_p[26] << 20) 810 | (mask_p[25] << 18) | (mask_p[24] << 16) 811 | (mask_p[23] << 14) | (mask_p[22] << 12) 812 | (mask_p[21] << 10) | (mask_p[20] << 8) 813 | (mask_p[19] << 6) | (mask_p[18] << 4) 814 | (mask_p[17] << 2) | (mask_p[16] << 0); 815 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 816 OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 817 818 tmp_mask = (mask_p[45] << 28) 819 | (mask_p[44] << 26) | (mask_p[43] << 24) 820 | (mask_p[42] << 22) | (mask_p[41] << 20) 821 | (mask_p[40] << 18) | (mask_p[39] << 16) 822 | (mask_p[38] << 14) | (mask_p[37] << 12) 823 | (mask_p[36] << 10) | (mask_p[35] << 8) 824 | (mask_p[34] << 6) | (mask_p[33] << 4) 825 | (mask_p[32] << 2) | (mask_p[31] << 0); 826 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 827 OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 828 829 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 830 | (mask_p[59] << 26) | (mask_p[58] << 24) 831 | (mask_p[57] << 22) | (mask_p[56] << 20) 832 | (mask_p[55] << 18) | (mask_p[54] << 16) 833 | (mask_p[53] << 14) | (mask_p[52] << 12) 834 | (mask_p[51] << 10) | (mask_p[50] << 8) 835 | (mask_p[49] << 6) | (mask_p[48] << 4) 836 | (mask_p[47] << 2) | (mask_p[46] << 0); 837 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 838 OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 839 840 OS_REG_WRITE_BUFFER_FLUSH(ah); 841 OS_REG_WRITE_BUFFER_DISABLE(ah); 842 } 843 844 /* 845 * Fill all software cached or static hardware state information. 846 * Return failure if capabilities are to come from EEPROM and 847 * cannot be read. 848 */ 849 HAL_BOOL 850 ar5416FillCapabilityInfo(struct ath_hal *ah) 851 { 852 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 853 HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 854 uint16_t val; 855 856 /* Construct wireless mode from EEPROM */ 857 pCap->halWirelessModes = 0; 858 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) { 859 pCap->halWirelessModes |= HAL_MODE_11A 860 | HAL_MODE_11NA_HT20 861 | HAL_MODE_11NA_HT40PLUS 862 | HAL_MODE_11NA_HT40MINUS 863 ; 864 } 865 if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE)) { 866 pCap->halWirelessModes |= HAL_MODE_11G 867 | HAL_MODE_11NG_HT20 868 | HAL_MODE_11NG_HT40PLUS 869 | HAL_MODE_11NG_HT40MINUS 870 ; 871 pCap->halWirelessModes |= HAL_MODE_11A 872 | HAL_MODE_11NA_HT20 873 | HAL_MODE_11NA_HT40PLUS 874 | HAL_MODE_11NA_HT40MINUS 875 ; 876 } 877 878 pCap->halLow2GhzChan = 2312; 879 pCap->halHigh2GhzChan = 2732; 880 881 pCap->halLow5GhzChan = 4915; 882 pCap->halHigh5GhzChan = 6100; 883 884 pCap->halCipherCkipSupport = AH_FALSE; 885 pCap->halCipherTkipSupport = AH_TRUE; 886 pCap->halCipherAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 887 888 pCap->halMicCkipSupport = AH_FALSE; 889 pCap->halMicTkipSupport = AH_TRUE; 890 pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 891 /* 892 * Starting with Griffin TX+RX mic keys can be combined 893 * in one key cache slot. 894 */ 895 pCap->halTkipMicTxRxKeySupport = AH_TRUE; 896 pCap->halChanSpreadSupport = AH_TRUE; 897 pCap->halSleepAfterBeaconBroken = AH_TRUE; 898 899 pCap->halCompressSupport = AH_FALSE; 900 pCap->halBurstSupport = AH_TRUE; 901 /* 902 * This is disabled for now; the net80211 layer needs to be 903 * taught when it is and isn't appropriate to enable FF processing 904 * with 802.11n NICs (it tries to enable both A-MPDU and 905 * fast frames, with very tragic crash-y results.) 906 */ 907 pCap->halFastFramesSupport = AH_FALSE; 908 pCap->halChapTuningSupport = AH_TRUE; 909 pCap->halTurboPrimeSupport = AH_TRUE; 910 911 pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G; 912 913 pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */ 914 pCap->halNumMRRetries = 4; /* Hardware supports 4 MRR */ 915 pCap->halNumTxMaps = 1; /* Single TX ptr per descr */ 916 pCap->halVEOLSupport = AH_TRUE; 917 pCap->halBssIdMaskSupport = AH_TRUE; 918 pCap->halMcastKeySrchSupport = AH_TRUE; /* Works on AR5416 and later */ 919 pCap->halTsfAddSupport = AH_TRUE; 920 pCap->hal4AddrAggrSupport = AH_FALSE; /* Broken in Owl */ 921 922 if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK) 923 pCap->halTotalQueues = val; 924 else 925 pCap->halTotalQueues = HAL_NUM_TX_QUEUES; 926 927 if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK) 928 pCap->halKeyCacheSize = val; 929 else 930 pCap->halKeyCacheSize = AR5416_KEYTABLE_SIZE; 931 932 /* XXX Which chips? */ 933 pCap->halChanHalfRate = AH_TRUE; 934 pCap->halChanQuarterRate = AH_TRUE; 935 936 pCap->halTstampPrecision = 32; 937 pCap->halHwPhyCounterSupport = AH_TRUE; 938 pCap->halIntrMask = HAL_INT_COMMON 939 | HAL_INT_RX 940 | HAL_INT_TX 941 | HAL_INT_FATAL 942 | HAL_INT_BNR 943 | HAL_INT_BMISC 944 | HAL_INT_DTIMSYNC 945 | HAL_INT_TSFOOR 946 | HAL_INT_CST 947 | HAL_INT_GTT 948 ; 949 950 pCap->halFastCCSupport = AH_TRUE; 951 pCap->halNumGpioPins = 14; 952 pCap->halWowSupport = AH_FALSE; 953 pCap->halWowMatchPatternExact = AH_FALSE; 954 pCap->halBtCoexSupport = AH_FALSE; /* XXX need support */ 955 pCap->halAutoSleepSupport = AH_FALSE; 956 pCap->hal4kbSplitTransSupport = AH_TRUE; 957 /* Disable this so Block-ACK works correctly */ 958 pCap->halHasRxSelfLinkedTail = AH_FALSE; 959 #if 0 /* XXX not yet */ 960 pCap->halNumAntCfg2GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_2GHZ); 961 pCap->halNumAntCfg5GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_5GHZ); 962 #endif 963 pCap->halHTSupport = AH_TRUE; 964 pCap->halTxChainMask = ath_hal_eepromGet(ah, AR_EEP_TXMASK, AH_NULL); 965 /* XXX CB71 uses GPIO 0 to indicate 3 rx chains */ 966 pCap->halRxChainMask = ath_hal_eepromGet(ah, AR_EEP_RXMASK, AH_NULL); 967 /* AR5416 may have 3 antennas but is a 2x2 stream device */ 968 pCap->halTxStreams = 2; 969 pCap->halRxStreams = 2; 970 971 /* 972 * If the TX or RX chainmask has less than 2 chains active, 973 * mark it as a 1-stream device for the relevant stream. 974 */ 975 if (owl_get_ntxchains(pCap->halTxChainMask) == 1) 976 pCap->halTxStreams = 1; 977 /* XXX Eww */ 978 if (owl_get_ntxchains(pCap->halRxChainMask) == 1) 979 pCap->halRxStreams = 1; 980 pCap->halRtsAggrLimit = 8*1024; /* Owl 2.0 limit */ 981 pCap->halMbssidAggrSupport = AH_FALSE; /* Broken on Owl */ 982 pCap->halForcePpmSupport = AH_TRUE; 983 pCap->halEnhancedPmSupport = AH_TRUE; 984 pCap->halBssidMatchSupport = AH_TRUE; 985 pCap->halGTTSupport = AH_TRUE; 986 pCap->halCSTSupport = AH_TRUE; 987 pCap->halEnhancedDfsSupport = AH_FALSE; 988 /* Hardware supports 32 bit TSF values in the RX descriptor */ 989 pCap->halHasLongRxDescTsf = AH_TRUE; 990 /* 991 * BB Read WAR: this is only for AR5008/AR9001 NICs 992 * It is also set individually in the AR91xx attach functions. 993 */ 994 if (AR_SREV_OWL(ah)) 995 pCap->halHasBBReadWar = AH_TRUE; 996 997 if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) && 998 ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) { 999 /* NB: enabled by default */ 1000 ahpriv->ah_rfkillEnabled = AH_TRUE; 1001 pCap->halRfSilentSupport = AH_TRUE; 1002 } 1003 1004 /* 1005 * The MAC will mark frames as RXed if there's a descriptor 1006 * to write them to. So if it hits a self-linked final descriptor, 1007 * it'll keep ACKing frames even though they're being silently 1008 * dropped. Thus, this particular feature of the driver can't 1009 * be used for 802.11n devices. 1010 */ 1011 ahpriv->ah_rxornIsFatal = AH_FALSE; 1012 1013 /* 1014 * If it's a PCI NIC, ask the HAL OS layer to serialise 1015 * register access, or SMP machines may cause the hardware 1016 * to hang. This is applicable to AR5416 and AR9220; I'm not 1017 * sure about AR9160 or AR9227. 1018 */ 1019 if (! AH_PRIVATE(ah)->ah_ispcie) 1020 pCap->halSerialiseRegWar = 1; 1021 1022 return AH_TRUE; 1023 } 1024 1025 static const char* 1026 ar5416Probe(uint16_t vendorid, uint16_t devid) 1027 { 1028 if (vendorid == ATHEROS_VENDOR_ID) { 1029 if (devid == AR5416_DEVID_PCI) 1030 return "Atheros 5416"; 1031 if (devid == AR5416_DEVID_PCIE) 1032 return "Atheros 5418"; 1033 } 1034 return AH_NULL; 1035 } 1036 AH_CHIP(AR5416, ar5416Probe, ar5416Attach); 1037