1 /*- 2 * SPDX-License-Identifier: ISC 3 * 4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 5 * Copyright (c) 2002-2008 Atheros Communications, Inc. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 #ifndef _DEV_ATH_AR5312REG_H_ 20 #define _DEV_ATH_AR5312REG_H_ 21 22 #include "ar5212/ar5212reg.h" 23 /* 24 * Definitions for the Atheros 5312 chipset. 25 */ 26 27 /* Register base addresses for modules which are not wmac modules */ 28 /* 531X has a fixed memory map */ 29 30 #define REG_WRITE(_reg,_val) *((volatile uint32_t *)(_reg)) = (_val); 31 #define REG_READ(_reg) *((volatile uint32_t *)(_reg)) 32 /* 33 * PCI-MAC Configuration registers (AR2315+) 34 */ 35 #define AR5315_RSTIMER_BASE 0xb1000000 /* Address for reset/timer registers */ 36 #define AR5315_GPIO_BASE 0xb1000000 /* Address for GPIO registers */ 37 #define AR5315_WLAN0 0xb0000000 38 39 #define AR5315_RESET 0x0004 /* Offset of reset control register */ 40 #define AR5315_SREV 0x0014 /* Offset of reset control register */ 41 #define AR5315_ENDIAN_CTL 0x000c /* offset of the endian control register */ 42 #define AR5315_CONFIG_WLAN 0x00000002 /* WLAN byteswap */ 43 44 #define AR5315_REV_MAJ 0x00f0 45 #define AR5315_REV_MIN 0x000f 46 47 #define AR5315_GPIODIR 0x0098 /* GPIO direction register */ 48 #define AR5315_GPIODO 0x0090 /* GPIO data output access reg */ 49 #define AR5315_GPIODI 0x0088 /* GPIO data input access reg*/ 50 #define AR5315_GPIOINT 0x00a0 /* GPIO interrupt control */ 51 52 #define AR5315_GPIODIR_M(x) (1 << (x)) /* mask for i/o */ 53 #define AR5315_GPIODIR_O(x) (1 << (x)) /* output */ 54 #define AR5315_GPIODIR_I(x) 0 /* input */ 55 56 #define AR5315_GPIOINT_S 0 57 #define AR5315_GPIOINT_M 0x3F 58 #define AR5315_GPIOINTLVL_S 6 59 #define AR5315_GPIOINTLVL_M (3 << AR5315_GPIOINTLVL_S) 60 61 #define AR5315_WREV (-0xefbfe0) /* Revision ID register offset */ 62 #define AR5315_WREV_S 0 /* Shift for WMAC revision info */ 63 #define AR5315_WREV_ID 0x000000FF /* Mask for WMAC revision info */ 64 #define AR5315_WREV_ID_S 4 /* Shift for WMAC Rev ID */ 65 #define AR5315_WREV_REVISION 0x0000000F /* Mask for WMAN Revsion version */ 66 67 #define AR5315_RC_BB0_CRES 0x00000002 /* Cold reset to WMAC0 & WBB0 */ 68 #define AR5315_RC_BB1_CRES 0x00000200 /* Cold reset to WMAC1 & WBB1n */ 69 #define AR5315_RC_WMAC0_RES 0x00000001 /* Warm reset to WMAC 0 */ 70 #define AR5315_RC_WBB0_RES 0x00000002 /* Warm reset to WBB0 */ 71 #define AR5315_RC_WMAC1_RES 0x00020000 /* Warm reset to WMAC1 */ 72 #define AR5315_RC_WBB1_RES 0x00040000 /* Warm reset to WBB */ 73 74 /* 75 * PCI-MAC Configuration registers (AR5312) 76 */ 77 #define AR5312_RSTIMER_BASE 0xbc003000 /* Address for reset/timer registers */ 78 #define AR5312_GPIO_BASE 0xbc002000 /* Address for GPIO registers */ 79 #define AR5312_WLAN0 0xb8000000 80 #define AR5312_WLAN1 0xb8500000 81 82 #define AR5312_RESET 0x0020 /* Offset of reset control register */ 83 #define AR5312_PCICFG 0x00B0 /* MAC/PCI configuration reg (LEDs) */ 84 85 #define AR5312_PCICFG_LEDMODE 0x0000001c /* LED Mode mask */ 86 #define AR5312_PCICFG_LEDMODE_S 2 /* LED Mode shift */ 87 #define AR5312_PCICFG_LEDMOD0 0 /* Blnk prop to Tx and filtered Rx */ 88 #define AR5312_PCICFG_LEDMOD1 1 /* Blnk prop to all Tx and Rx */ 89 #define AR5312_PCICFG_LEDMOD2 2 /* DEBG flash */ 90 #define AR5312_PCICFG_LEDMOD3 3 /* BLNK Randomly */ 91 92 #define AR5312_PCICFG_LEDSEL 0x000000e0 /* LED Throughput select */ 93 #define AR5312_PCICFG_LEDSEL_S 5 94 #define AR5312_PCICFG_LEDSEL0 0 /* See blink rate table on p. 143 */ 95 #define AR5312_PCICFG_LEDSEL1 1 /* of AR5212 data sheet */ 96 #define AR5312_PCICFG_LEDSEL2 2 97 #define AR5312_PCICFG_LEDSEL3 3 98 #define AR5312_PCICFG_LEDSEL4 4 99 #define AR5312_PCICFG_LEDSEL5 5 100 #define AR5312_PCICFG_LEDSEL6 6 101 #define AR5312_PCICFG_LEDSEL7 7 102 103 #define AR5312_PCICFG_LEDSBR 0x00000100 /* Slow blink rate if no 104 activity. 0 = blink @ lowest 105 rate */ 106 107 #undef AR_GPIOCR 108 #undef AR_GPIODO /* Undefine the 5212 defs */ 109 #undef AR_GPIODI 110 111 #define AR5312_GPIOCR 0x0008 /* GPIO Control register */ 112 #define AR5312_GPIODO 0x0000 /* GPIO data output access reg */ 113 #define AR5312_GPIODI 0x0004 /* GPIO data input access reg*/ 114 /* NB: AR5312 uses AR5212 defines for GPIOCR definitions */ 115 116 #define AR5312_WREV 0x0090 /* Revision ID register offset */ 117 #define AR5312_WREV_S 8 /* Shift for WMAC revision info */ 118 #define AR5312_WREV_ID 0x000000FF /* Mask for WMAC revision info */ 119 #define AR5312_WREV_ID_S 4 /* Shift for WMAC Rev ID */ 120 #define AR5312_WREV_REVISION 0x0000000F /* Mask for WMAN Revsion version */ 121 122 #define AR5312_RC_BB0_CRES 0x00000004 /* Cold reset to WMAC0 & WBB0 */ 123 #define AR5312_RC_BB1_CRES 0x00000200 /* Cold reset to WMAC1 & WBB1n */ 124 #define AR5312_RC_WMAC0_RES 0x00002000 /* Warm reset to WMAC 0 */ 125 #define AR5312_RC_WBB0_RES 0x00004000 /* Warm reset to WBB0 */ 126 #define AR5312_RC_WMAC1_RES 0x00020000 /* Warm reset to WMAC1 */ 127 #define AR5312_RC_WBB1_RES 0x00040000 /* Warm reset to WBB */ 128 129 #define AR_RAD2112_SREV_MAJOR 0x40 /* 2112 Major Rev */ 130 131 enum AR5312PowerMode { 132 AR5312_POWER_MODE_FORCE_SLEEP = 0, 133 AR5312_POWER_MODE_FORCE_WAKE = 1, 134 AR5312_POWER_MODE_NORMAL = 2, 135 }; 136 137 #endif /* _DEV_AR5312REG_H_ */ 138