1 /*- 2 * SPDX-License-Identifier: ISC 3 * 4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 5 * Copyright (c) 2002-2008 Atheros Communications, Inc. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 #include "opt_ah.h" 20 21 #ifdef AH_SUPPORT_AR5312 22 23 #include "ah.h" 24 #include "ah_internal.h" 25 #include "ah_devid.h" 26 27 #include "ar5312/ar5312.h" 28 #include "ar5312/ar5312reg.h" 29 #include "ar5312/ar5312phy.h" 30 31 #define AR_NUM_GPIO 6 /* 6 GPIO pins */ 32 #define AR5312_GPIOD_MASK 0x0000002F /* GPIO data reg r/w mask */ 33 34 /* 35 * Configure GPIO Output lines 36 */ 37 HAL_BOOL 38 ar5312GpioCfgOutput(struct ath_hal *ah, uint32_t gpio, HAL_GPIO_MUX_TYPE type) 39 { 40 uint32_t gpioOffset = (AR5312_GPIO_BASE - ((uint32_t) ah->ah_sh)); 41 42 HALASSERT(gpio < AR_NUM_GPIO); 43 44 OS_REG_WRITE(ah, gpioOffset+AR5312_GPIOCR, 45 (OS_REG_READ(ah, gpioOffset+AR5312_GPIOCR) &~ AR_GPIOCR_CR_A(gpio)) 46 | AR_GPIOCR_CR_A(gpio)); 47 48 return AH_TRUE; 49 } 50 51 /* 52 * Configure GPIO Input lines 53 */ 54 HAL_BOOL 55 ar5312GpioCfgInput(struct ath_hal *ah, uint32_t gpio) 56 { 57 uint32_t gpioOffset = (AR5312_GPIO_BASE - ((uint32_t) ah->ah_sh)); 58 59 HALASSERT(gpio < AR_NUM_GPIO); 60 61 OS_REG_WRITE(ah, gpioOffset+AR5312_GPIOCR, 62 (OS_REG_READ(ah, gpioOffset+AR5312_GPIOCR) &~ AR_GPIOCR_CR_A(gpio)) 63 | AR_GPIOCR_CR_N(gpio)); 64 65 return AH_TRUE; 66 } 67 68 /* 69 * Once configured for I/O - set output lines 70 */ 71 HAL_BOOL 72 ar5312GpioSet(struct ath_hal *ah, uint32_t gpio, uint32_t val) 73 { 74 uint32_t reg; 75 uint32_t gpioOffset = (AR5312_GPIO_BASE - ((uint32_t) ah->ah_sh)); 76 77 HALASSERT(gpio < AR_NUM_GPIO); 78 79 reg = OS_REG_READ(ah, gpioOffset+AR5312_GPIODO); 80 reg &= ~(1 << gpio); 81 reg |= (val&1) << gpio; 82 83 OS_REG_WRITE(ah, gpioOffset+AR5312_GPIODO, reg); 84 return AH_TRUE; 85 } 86 87 /* 88 * Once configured for I/O - get input lines 89 */ 90 uint32_t 91 ar5312GpioGet(struct ath_hal *ah, uint32_t gpio) 92 { 93 uint32_t gpioOffset = (AR5312_GPIO_BASE - ((uint32_t) ah->ah_sh)); 94 95 if (gpio < AR_NUM_GPIO) { 96 uint32_t val = OS_REG_READ(ah, gpioOffset+AR5312_GPIODI); 97 val = ((val & AR5312_GPIOD_MASK) >> gpio) & 0x1; 98 return val; 99 } else { 100 return 0xffffffff; 101 } 102 } 103 104 /* 105 * Set the GPIO Interrupt 106 */ 107 void 108 ar5312GpioSetIntr(struct ath_hal *ah, u_int gpio, uint32_t ilevel) 109 { 110 uint32_t val; 111 uint32_t gpioOffset = (AR5312_GPIO_BASE - ((uint32_t) ah->ah_sh)); 112 113 /* XXX bounds check gpio */ 114 val = OS_REG_READ(ah, gpioOffset+AR5312_GPIOCR); 115 val &= ~(AR_GPIOCR_CR_A(gpio) | 116 AR_GPIOCR_INT_MASK | AR_GPIOCR_INT_ENA | AR_GPIOCR_INT_SEL); 117 val |= AR_GPIOCR_CR_N(gpio) | AR_GPIOCR_INT(gpio) | AR_GPIOCR_INT_ENA; 118 if (ilevel) 119 val |= AR_GPIOCR_INT_SELH; /* interrupt on pin high */ 120 else 121 val |= AR_GPIOCR_INT_SELL; /* interrupt on pin low */ 122 123 /* Don't need to change anything for low level interrupt. */ 124 OS_REG_WRITE(ah, gpioOffset+AR5312_GPIOCR, val); 125 126 /* Change the interrupt mask. */ 127 (void) ar5212SetInterrupts(ah, AH5212(ah)->ah_maskReg | HAL_INT_GPIO); 128 } 129 130 #endif /* AH_SUPPORT_AR5312 */ 131