1 /* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19 #ifndef _DEV_ATH_AR5311REG_H_ 20 #define _DEV_ATH_AR5311REG_H_ 21 22 /* 23 * Definitions for the Atheros 5311 chipset. 24 */ 25 #define AR5311_QDCLKGATE 0x005c /* MAC QCU/DCU clock gating control */ 26 #define AR5311_QDCLKGATE_QCU_M 0x0000FFFF /* QCU clock disable */ 27 #define AR5311_QDCLKGATE_DCU_M 0x07FF0000 /* DCU clock disable */ 28 29 #define AR5311_RXCFG_DEF_RX_ANTENNA 0x00000008 /* Default Receive Antenna */ 30 31 /* 32 * NOTE: MAC_5211/MAC_5311 difference 33 * On Oahu the TX latency field has increased from 6 bits to 9 bits. 34 * The RX latency field is unchanged but is shifted over 3 bits. 35 */ 36 #define AR5311_USEC_TX_LAT_M 0x000FC000 /* tx latency (usec) */ 37 #define AR5311_USEC_TX_LAT_S 14 38 #define AR5311_USEC_RX_LAT_M 0x03F00000 /* rx latency (usec) */ 39 #define AR5311_USEC_RX_LAT_S 20 40 41 /* 42 * NOTE: MAC_5211/MAC_5311 difference 43 * On Maui2/Spirit the frame sequence number is controlled per DCU. 44 * On Oahu the frame sequence number is global across all DCUs and 45 * is controlled 46 */ 47 #define AR5311_D_MISC_SEQ_NUM_CONTROL 0x01000000 /* seq num local or global */ 48 #define AR5311_DIAG_USE_ECO 0x00000400 /* "super secret" enable ECO */ 49 50 #endif /* _DEV_ATH_AR5311REG_H_ */ 51