xref: /freebsd/sys/dev/ath/ath_hal/ar5212/ar5311reg.h (revision 0b57cec536236d46e3dba9bd041533462f33dbb7)
1 /*-
2  * SPDX-License-Identifier: ISC
3  *
4  * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5  * Copyright (c) 2002-2008 Atheros Communications, Inc.
6  *
7  * Permission to use, copy, modify, and/or distribute this software for any
8  * purpose with or without fee is hereby granted, provided that the above
9  * copyright notice and this permission notice appear in all copies.
10  *
11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18  *
19  * $FreeBSD$
20  */
21 #ifndef _DEV_ATH_AR5311REG_H_
22 #define _DEV_ATH_AR5311REG_H_
23 
24 /*
25  * Definitions for the Atheros 5311 chipset.
26  */
27 #define	AR5311_QDCLKGATE	0x005c	/* MAC QCU/DCU clock gating control */
28 #define	AR5311_QDCLKGATE_QCU_M	0x0000FFFF /* QCU clock disable */
29 #define	AR5311_QDCLKGATE_DCU_M	0x07FF0000 /* DCU clock disable */
30 
31 #define	AR5311_RXCFG_DEF_RX_ANTENNA	0x00000008 /* Default Receive Antenna */
32 
33 /*
34  * NOTE: MAC_5211/MAC_5311 difference
35  * On Oahu the TX latency field has increased from 6 bits to 9 bits.
36  * The RX latency field is unchanged but is shifted over 3 bits.
37  */
38 #define	AR5311_USEC_TX_LAT_M	0x000FC000 /* tx latency (usec) */
39 #define	AR5311_USEC_TX_LAT_S	14
40 #define	AR5311_USEC_RX_LAT_M	0x03F00000 /* rx latency (usec) */
41 #define	AR5311_USEC_RX_LAT_S	20
42 
43 /*
44  * NOTE: MAC_5211/MAC_5311 difference
45  * On Maui2/Spirit the frame sequence number is controlled per DCU.
46  * On Oahu the frame sequence number is global across all DCUs and
47  * is controlled
48  */
49 #define	AR5311_D_MISC_SEQ_NUM_CONTROL	0x01000000 /* seq num local or global */
50 #define	AR5311_DIAG_USE_ECO	0x00000400	/* "super secret" enable ECO */
51 
52 #endif /* _DEV_ATH_AR5311REG_H_ */
53