1 /* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19 #include "opt_ah.h" 20 21 #include "ah.h" 22 #include "ah_internal.h" 23 #include "ah_devid.h" 24 25 #include "ar5212/ar5212.h" 26 #include "ar5212/ar5212reg.h" 27 #include "ar5212/ar5212phy.h" 28 29 #include "ah_eeprom_v3.h" 30 31 /* Additional Time delay to wait after activiting the Base band */ 32 #define BASE_ACTIVATE_DELAY 100 /* 100 usec */ 33 #define PLL_SETTLE_DELAY 300 /* 300 usec */ 34 35 static HAL_BOOL ar5212SetResetReg(struct ath_hal *, uint32_t resetMask); 36 /* NB: public for 5312 use */ 37 HAL_BOOL ar5212IsSpurChannel(struct ath_hal *, 38 const struct ieee80211_channel *); 39 HAL_BOOL ar5212ChannelChange(struct ath_hal *, 40 const struct ieee80211_channel *); 41 int16_t ar5212GetNf(struct ath_hal *, struct ieee80211_channel *); 42 HAL_BOOL ar5212SetBoardValues(struct ath_hal *, 43 const struct ieee80211_channel *); 44 void ar5212SetDeltaSlope(struct ath_hal *, 45 const struct ieee80211_channel *); 46 HAL_BOOL ar5212SetTransmitPower(struct ath_hal *ah, 47 const struct ieee80211_channel *chan, uint16_t *rfXpdGain); 48 static HAL_BOOL ar5212SetRateTable(struct ath_hal *, 49 const struct ieee80211_channel *, int16_t tpcScaleReduction, 50 int16_t powerLimit, 51 HAL_BOOL commit, int16_t *minPower, int16_t *maxPower); 52 static void ar5212CorrectGainDelta(struct ath_hal *, int twiceOfdmCckDelta); 53 static void ar5212GetTargetPowers(struct ath_hal *, 54 const struct ieee80211_channel *, 55 const TRGT_POWER_INFO *pPowerInfo, uint16_t numChannels, 56 TRGT_POWER_INFO *pNewPower); 57 static uint16_t ar5212GetMaxEdgePower(uint16_t channel, 58 const RD_EDGES_POWER *pRdEdgesPower); 59 void ar5212SetRateDurationTable(struct ath_hal *, 60 const struct ieee80211_channel *); 61 void ar5212SetIFSTiming(struct ath_hal *, 62 const struct ieee80211_channel *); 63 64 /* NB: public for RF backend use */ 65 void ar5212GetLowerUpperValues(uint16_t value, 66 uint16_t *pList, uint16_t listSize, 67 uint16_t *pLowerValue, uint16_t *pUpperValue); 68 void ar5212ModifyRfBuffer(uint32_t *rfBuf, uint32_t reg32, 69 uint32_t numBits, uint32_t firstBit, uint32_t column); 70 71 static int 72 write_common(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 73 HAL_BOOL bChannelChange, int writes) 74 { 75 #define IS_NO_RESET_TIMER_ADDR(x) \ 76 ( (((x) >= AR_BEACON) && ((x) <= AR_CFP_DUR)) || \ 77 (((x) >= AR_SLEEP1) && ((x) <= AR_SLEEP3))) 78 #define V(r, c) (ia)->data[((r)*(ia)->cols) + (c)] 79 int r; 80 81 /* Write Common Array Parameters */ 82 for (r = 0; r < ia->rows; r++) { 83 uint32_t reg = V(r, 0); 84 /* XXX timer/beacon setup registers? */ 85 /* On channel change, don't reset the PCU registers */ 86 if (!(bChannelChange && IS_NO_RESET_TIMER_ADDR(reg))) { 87 OS_REG_WRITE(ah, reg, V(r, 1)); 88 DMA_YIELD(writes); 89 } 90 } 91 return writes; 92 #undef IS_NO_RESET_TIMER_ADDR 93 #undef V 94 } 95 96 #define IS_DISABLE_FAST_ADC_CHAN(x) (((x) == 2462) || ((x) == 2467)) 97 98 /* 99 * XXX NDIS 5.x code had MAX_RESET_WAIT set to 2000 for AP code 100 * and 10 for Client code 101 */ 102 #define MAX_RESET_WAIT 10 103 104 #define TX_QUEUEPEND_CHECK 1 105 #define TX_ENABLE_CHECK 2 106 #define RX_ENABLE_CHECK 4 107 108 /* 109 * Places the device in and out of reset and then places sane 110 * values in the registers based on EEPROM config, initialization 111 * vectors (as determined by the mode), and station configuration 112 * 113 * bChannelChange is used to preserve DMA/PCU registers across 114 * a HW Reset during channel change. 115 */ 116 HAL_BOOL 117 ar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode, 118 struct ieee80211_channel *chan, 119 HAL_BOOL bChannelChange, HAL_STATUS *status) 120 { 121 #define N(a) (sizeof (a) / sizeof (a[0])) 122 #define FAIL(_code) do { ecode = _code; goto bad; } while (0) 123 struct ath_hal_5212 *ahp = AH5212(ah); 124 HAL_CHANNEL_INTERNAL *ichan = AH_NULL; 125 const HAL_EEPROM *ee; 126 uint32_t softLedCfg, softLedState; 127 uint32_t saveFrameSeqCount, saveDefAntenna, saveLedState; 128 uint32_t macStaId1, synthDelay, txFrm2TxDStart; 129 uint16_t rfXpdGain[MAX_NUM_PDGAINS_PER_CHANNEL]; 130 int16_t cckOfdmPwrDelta = 0; 131 u_int modesIndex, freqIndex; 132 HAL_STATUS ecode; 133 int i, regWrites; 134 uint32_t testReg, powerVal; 135 int8_t twiceAntennaGain, twiceAntennaReduction; 136 uint32_t ackTpcPow, ctsTpcPow, chirpTpcPow; 137 HAL_BOOL isBmode = AH_FALSE; 138 139 HALASSERT(ah->ah_magic == AR5212_MAGIC); 140 ee = AH_PRIVATE(ah)->ah_eeprom; 141 142 OS_MARK(ah, AH_MARK_RESET, bChannelChange); 143 144 /* Bring out of sleep mode */ 145 if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 146 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip did not wakeup\n", 147 __func__); 148 FAIL(HAL_EIO); 149 } 150 151 /* 152 * Map public channel to private. 153 */ 154 ichan = ath_hal_checkchannel(ah, chan); 155 if (ichan == AH_NULL) 156 FAIL(HAL_EINVAL); 157 switch (opmode) { 158 case HAL_M_STA: 159 case HAL_M_IBSS: 160 case HAL_M_HOSTAP: 161 case HAL_M_MONITOR: 162 break; 163 default: 164 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid operating mode %u\n", 165 __func__, opmode); 166 FAIL(HAL_EINVAL); 167 break; 168 } 169 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER3); 170 171 SAVE_CCK(ah, chan, isBmode); 172 173 /* Preserve certain DMA hardware registers on a channel change */ 174 if (bChannelChange) { 175 /* 176 * On Venice, the TSF is almost preserved across a reset; 177 * it requires doubling writes to the RESET_TSF 178 * bit in the AR_BEACON register; it also has the quirk 179 * of the TSF going back in time on the station (station 180 * latches onto the last beacon's tsf during a reset 50% 181 * of the times); the latter is not a problem for adhoc 182 * stations since as long as the TSF is behind, it will 183 * get resynchronized on receiving the next beacon; the 184 * TSF going backwards in time could be a problem for the 185 * sleep operation (supported on infrastructure stations 186 * only) - the best and most general fix for this situation 187 * is to resynchronize the various sleep/beacon timers on 188 * the receipt of the next beacon i.e. when the TSF itself 189 * gets resynchronized to the AP's TSF - power save is 190 * needed to be temporarily disabled until that time 191 * 192 * Need to save the sequence number to restore it after 193 * the reset! 194 */ 195 saveFrameSeqCount = OS_REG_READ(ah, AR_D_SEQNUM); 196 } else 197 saveFrameSeqCount = 0; /* NB: silence compiler */ 198 199 /* Blank the channel survey statistics */ 200 OS_MEMZERO(&ahp->ah_chansurvey, sizeof(ahp->ah_chansurvey)); 201 #if 0 202 /* 203 * XXX disable for now; this appears to sometimes cause OFDM 204 * XXX timing error floods when ani is enabled and bg scanning 205 * XXX kicks in 206 */ 207 /* If the channel change is across the same mode - perform a fast channel change */ 208 if (IS_2413(ah) || IS_5413(ah)) { 209 /* 210 * Fast channel change can only be used when: 211 * -channel change requested - so it's not the initial reset. 212 * -it's not a change to the current channel - 213 * often called when switching modes on a channel 214 * -the modes of the previous and requested channel are the 215 * same 216 * XXX opmode shouldn't change either? 217 */ 218 if (bChannelChange && 219 (AH_PRIVATE(ah)->ah_curchan != AH_NULL) && 220 (chan->ic_freq != AH_PRIVATE(ah)->ah_curchan->ic_freq) && 221 ((chan->ic_flags & IEEE80211_CHAN_ALLTURBO) == 222 (AH_PRIVATE(ah)->ah_curchan->ic_flags & IEEE80211_CHAN_ALLTURBO))) { 223 if (ar5212ChannelChange(ah, chan)) { 224 /* If ChannelChange completed - skip the rest of reset */ 225 /* XXX ani? */ 226 goto done; 227 } 228 } 229 } 230 #endif 231 /* 232 * Preserve the antenna on a channel change 233 */ 234 saveDefAntenna = OS_REG_READ(ah, AR_DEF_ANTENNA); 235 if (saveDefAntenna == 0) /* XXX magic constants */ 236 saveDefAntenna = 1; 237 238 /* Save hardware flag before chip reset clears the register */ 239 macStaId1 = OS_REG_READ(ah, AR_STA_ID1) & 240 (AR_STA_ID1_BASE_RATE_11B | AR_STA_ID1_USE_DEFANT); 241 242 /* Save led state from pci config register */ 243 saveLedState = OS_REG_READ(ah, AR_PCICFG) & 244 (AR_PCICFG_LEDCTL | AR_PCICFG_LEDMODE | AR_PCICFG_LEDBLINK | 245 AR_PCICFG_LEDSLOW); 246 softLedCfg = OS_REG_READ(ah, AR_GPIOCR); 247 softLedState = OS_REG_READ(ah, AR_GPIODO); 248 249 ar5212RestoreClock(ah, opmode); /* move to refclk operation */ 250 251 /* 252 * Adjust gain parameters before reset if 253 * there's an outstanding gain updated. 254 */ 255 (void) ar5212GetRfgain(ah); 256 257 if (!ar5212ChipReset(ah, chan)) { 258 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 259 FAIL(HAL_EIO); 260 } 261 262 /* Setup the indices for the next set of register array writes */ 263 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 264 freqIndex = 2; 265 if (IEEE80211_IS_CHAN_108G(chan)) 266 modesIndex = 5; 267 else if (IEEE80211_IS_CHAN_G(chan)) 268 modesIndex = 4; 269 else if (IEEE80211_IS_CHAN_B(chan)) 270 modesIndex = 3; 271 else { 272 HALDEBUG(ah, HAL_DEBUG_ANY, 273 "%s: invalid channel %u/0x%x\n", 274 __func__, chan->ic_freq, chan->ic_flags); 275 FAIL(HAL_EINVAL); 276 } 277 } else { 278 freqIndex = 1; 279 if (IEEE80211_IS_CHAN_TURBO(chan)) 280 modesIndex = 2; 281 else if (IEEE80211_IS_CHAN_A(chan)) 282 modesIndex = 1; 283 else { 284 HALDEBUG(ah, HAL_DEBUG_ANY, 285 "%s: invalid channel %u/0x%x\n", 286 __func__, chan->ic_freq, chan->ic_flags); 287 FAIL(HAL_EINVAL); 288 } 289 } 290 291 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); 292 293 /* Set correct Baseband to analog shift setting to access analog chips. */ 294 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 295 296 regWrites = ath_hal_ini_write(ah, &ahp->ah_ini_modes, modesIndex, 0); 297 regWrites = write_common(ah, &ahp->ah_ini_common, bChannelChange, 298 regWrites); 299 #ifdef AH_RXCFG_SDMAMW_4BYTES 300 /* 301 * Nala doesn't work with 128 byte bursts on pb42(hydra) (ar71xx), 302 * use 4 instead. Enabling it on all platforms would hurt performance, 303 * so we only enable it on the ones that are affected by it. 304 */ 305 OS_REG_WRITE(ah, AR_RXCFG, 0); 306 #endif 307 ahp->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites); 308 309 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); 310 311 if (IEEE80211_IS_CHAN_HALF(chan) || IEEE80211_IS_CHAN_QUARTER(chan)) { 312 ar5212SetIFSTiming(ah, chan); 313 if (IS_5413(ah)) { 314 /* 315 * Force window_length for 1/2 and 1/4 rate channels, 316 * the ini file sets this to zero otherwise. 317 */ 318 OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, 319 AR_PHY_FRAME_CTL_WINLEN, 3); 320 } 321 } 322 323 /* Overwrite INI values for revised chipsets */ 324 if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_2) { 325 /* ADC_CTL */ 326 OS_REG_WRITE(ah, AR_PHY_ADC_CTL, 327 SM(2, AR_PHY_ADC_CTL_OFF_INBUFGAIN) | 328 SM(2, AR_PHY_ADC_CTL_ON_INBUFGAIN) | 329 AR_PHY_ADC_CTL_OFF_PWDDAC | 330 AR_PHY_ADC_CTL_OFF_PWDADC); 331 332 /* TX_PWR_ADJ */ 333 if (ichan->channel == 2484) { 334 cckOfdmPwrDelta = SCALE_OC_DELTA( 335 ee->ee_cckOfdmPwrDelta - 336 ee->ee_scaledCh14FilterCckDelta); 337 } else { 338 cckOfdmPwrDelta = SCALE_OC_DELTA( 339 ee->ee_cckOfdmPwrDelta); 340 } 341 342 if (IEEE80211_IS_CHAN_G(chan)) { 343 OS_REG_WRITE(ah, AR_PHY_TXPWRADJ, 344 SM((ee->ee_cckOfdmPwrDelta*-1), 345 AR_PHY_TXPWRADJ_CCK_GAIN_DELTA) | 346 SM((cckOfdmPwrDelta*-1), 347 AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX)); 348 } else { 349 OS_REG_WRITE(ah, AR_PHY_TXPWRADJ, 0); 350 } 351 352 /* Add barker RSSI thresh enable as disabled */ 353 OS_REG_CLR_BIT(ah, AR_PHY_DAG_CTRLCCK, 354 AR_PHY_DAG_CTRLCCK_EN_RSSI_THR); 355 OS_REG_RMW_FIELD(ah, AR_PHY_DAG_CTRLCCK, 356 AR_PHY_DAG_CTRLCCK_RSSI_THR, 2); 357 358 /* Set the mute mask to the correct default */ 359 OS_REG_WRITE(ah, AR_SEQ_MASK, 0x0000000F); 360 } 361 362 if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_3) { 363 /* Clear reg to alllow RX_CLEAR line debug */ 364 OS_REG_WRITE(ah, AR_PHY_BLUETOOTH, 0); 365 } 366 if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_4) { 367 #ifdef notyet 368 /* Enable burst prefetch for the data queues */ 369 OS_REG_RMW_FIELD(ah, AR_D_FPCTL, ... ); 370 /* Enable double-buffering */ 371 OS_REG_CLR_BIT(ah, AR_TXCFG, AR_TXCFG_DBL_BUF_DIS); 372 #endif 373 } 374 375 /* Set ADC/DAC select values */ 376 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e); 377 378 if (IS_5413(ah) || IS_2417(ah)) { 379 uint32_t newReg = 1; 380 if (IS_DISABLE_FAST_ADC_CHAN(ichan->channel)) 381 newReg = 0; 382 /* As it's a clock changing register, only write when the value needs to be changed */ 383 if (OS_REG_READ(ah, AR_PHY_FAST_ADC) != newReg) 384 OS_REG_WRITE(ah, AR_PHY_FAST_ADC, newReg); 385 } 386 387 /* Setup the transmit power values. */ 388 if (!ar5212SetTransmitPower(ah, chan, rfXpdGain)) { 389 HALDEBUG(ah, HAL_DEBUG_ANY, 390 "%s: error init'ing transmit power\n", __func__); 391 FAIL(HAL_EIO); 392 } 393 394 /* Write the analog registers */ 395 if (!ahp->ah_rfHal->setRfRegs(ah, chan, modesIndex, rfXpdGain)) { 396 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: ar5212SetRfRegs failed\n", 397 __func__); 398 FAIL(HAL_EIO); 399 } 400 401 /* Write delta slope for OFDM enabled modes (A, G, Turbo) */ 402 if (IEEE80211_IS_CHAN_OFDM(chan)) { 403 if (IS_5413(ah) || 404 AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER5_3) 405 ar5212SetSpurMitigation(ah, chan); 406 ar5212SetDeltaSlope(ah, chan); 407 } 408 409 /* Setup board specific options for EEPROM version 3 */ 410 if (!ar5212SetBoardValues(ah, chan)) { 411 HALDEBUG(ah, HAL_DEBUG_ANY, 412 "%s: error setting board options\n", __func__); 413 FAIL(HAL_EIO); 414 } 415 416 /* Restore certain DMA hardware registers on a channel change */ 417 if (bChannelChange) 418 OS_REG_WRITE(ah, AR_D_SEQNUM, saveFrameSeqCount); 419 420 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); 421 422 OS_REG_WRITE(ah, AR_STA_ID0, LE_READ_4(ahp->ah_macaddr)); 423 OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4) 424 | macStaId1 425 | AR_STA_ID1_RTS_USE_DEF 426 | ahp->ah_staId1Defaults 427 ); 428 ar5212SetOperatingMode(ah, opmode); 429 430 /* Set Venice BSSID mask according to current state */ 431 OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssidmask)); 432 OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssidmask + 4)); 433 434 /* Restore previous led state */ 435 OS_REG_WRITE(ah, AR_PCICFG, OS_REG_READ(ah, AR_PCICFG) | saveLedState); 436 437 /* Restore soft Led state to GPIO */ 438 OS_REG_WRITE(ah, AR_GPIOCR, softLedCfg); 439 OS_REG_WRITE(ah, AR_GPIODO, softLedState); 440 441 /* Restore previous antenna */ 442 OS_REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 443 444 /* then our BSSID and associate id */ 445 OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid)); 446 OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4) | 447 (ahp->ah_assocId & 0x3fff) << AR_BSS_ID1_AID_S); 448 449 /* Restore bmiss rssi & count thresholds */ 450 OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr); 451 452 OS_REG_WRITE(ah, AR_ISR, ~0); /* cleared on write */ 453 454 if (!ar5212SetChannel(ah, chan)) 455 FAIL(HAL_EIO); 456 457 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); 458 459 ar5212SetCoverageClass(ah, AH_PRIVATE(ah)->ah_coverageClass, 1); 460 461 ar5212SetRateDurationTable(ah, chan); 462 463 /* Set Tx frame start to tx data start delay */ 464 if (IS_RAD5112_ANY(ah) && 465 (IEEE80211_IS_CHAN_HALF(chan) || IEEE80211_IS_CHAN_QUARTER(chan))) { 466 txFrm2TxDStart = 467 IEEE80211_IS_CHAN_HALF(chan) ? 468 TX_FRAME_D_START_HALF_RATE: 469 TX_FRAME_D_START_QUARTER_RATE; 470 OS_REG_RMW_FIELD(ah, AR_PHY_TX_CTL, 471 AR_PHY_TX_FRAME_TO_TX_DATA_START, txFrm2TxDStart); 472 } 473 474 /* 475 * Setup fast diversity. 476 * Fast diversity can be enabled or disabled via regadd.txt. 477 * Default is enabled. 478 * For reference, 479 * Disable: reg val 480 * 0x00009860 0x00009d18 (if 11a / 11g, else no change) 481 * 0x00009970 0x192bb514 482 * 0x0000a208 0xd03e4648 483 * 484 * Enable: 0x00009860 0x00009d10 (if 11a / 11g, else no change) 485 * 0x00009970 0x192fb514 486 * 0x0000a208 0xd03e6788 487 */ 488 489 /* XXX Setup pre PHY ENABLE EAR additions */ 490 /* 491 * Wait for the frequency synth to settle (synth goes on 492 * via AR_PHY_ACTIVE_EN). Read the phy active delay register. 493 * Value is in 100ns increments. 494 */ 495 synthDelay = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 496 if (IEEE80211_IS_CHAN_B(chan)) { 497 synthDelay = (4 * synthDelay) / 22; 498 } else { 499 synthDelay /= 10; 500 } 501 502 /* Activate the PHY (includes baseband activate and synthesizer on) */ 503 OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 504 505 /* 506 * There is an issue if the AP starts the calibration before 507 * the base band timeout completes. This could result in the 508 * rx_clear false triggering. As a workaround we add delay an 509 * extra BASE_ACTIVATE_DELAY usecs to ensure this condition 510 * does not happen. 511 */ 512 if (IEEE80211_IS_CHAN_HALF(chan)) { 513 OS_DELAY((synthDelay << 1) + BASE_ACTIVATE_DELAY); 514 } else if (IEEE80211_IS_CHAN_QUARTER(chan)) { 515 OS_DELAY((synthDelay << 2) + BASE_ACTIVATE_DELAY); 516 } else { 517 OS_DELAY(synthDelay + BASE_ACTIVATE_DELAY); 518 } 519 520 /* 521 * The udelay method is not reliable with notebooks. 522 * Need to check to see if the baseband is ready 523 */ 524 testReg = OS_REG_READ(ah, AR_PHY_TESTCTRL); 525 /* Selects the Tx hold */ 526 OS_REG_WRITE(ah, AR_PHY_TESTCTRL, AR_PHY_TESTCTRL_TXHOLD); 527 i = 0; 528 while ((i++ < 20) && 529 (OS_REG_READ(ah, 0x9c24) & 0x10)) /* test if baseband not ready */ OS_DELAY(200); 530 OS_REG_WRITE(ah, AR_PHY_TESTCTRL, testReg); 531 532 /* Calibrate the AGC and start a NF calculation */ 533 OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL, 534 OS_REG_READ(ah, AR_PHY_AGC_CONTROL) 535 | AR_PHY_AGC_CONTROL_CAL 536 | AR_PHY_AGC_CONTROL_NF); 537 538 if (!IEEE80211_IS_CHAN_B(chan) && ahp->ah_bIQCalibration != IQ_CAL_DONE) { 539 /* Start IQ calibration w/ 2^(INIT_IQCAL_LOG_COUNT_MAX+1) samples */ 540 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4, 541 AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX, 542 INIT_IQCAL_LOG_COUNT_MAX); 543 OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4, 544 AR_PHY_TIMING_CTRL4_DO_IQCAL); 545 ahp->ah_bIQCalibration = IQ_CAL_RUNNING; 546 } else 547 ahp->ah_bIQCalibration = IQ_CAL_INACTIVE; 548 549 /* Setup compression registers */ 550 ar5212SetCompRegs(ah); 551 552 /* Set 1:1 QCU to DCU mapping for all queues */ 553 for (i = 0; i < AR_NUM_DCU; i++) 554 OS_REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 555 556 ahp->ah_intrTxqs = 0; 557 for (i = 0; i < AH_PRIVATE(ah)->ah_caps.halTotalQueues; i++) 558 ar5212ResetTxQueue(ah, i); 559 560 /* 561 * Setup interrupt handling. Note that ar5212ResetTxQueue 562 * manipulates the secondary IMR's as queues are enabled 563 * and disabled. This is done with RMW ops to insure the 564 * settings we make here are preserved. 565 */ 566 ahp->ah_maskReg = AR_IMR_TXOK | AR_IMR_TXERR | AR_IMR_TXURN 567 | AR_IMR_RXOK | AR_IMR_RXERR | AR_IMR_RXORN 568 | AR_IMR_HIUERR 569 ; 570 if (opmode == HAL_M_HOSTAP) 571 ahp->ah_maskReg |= AR_IMR_MIB; 572 OS_REG_WRITE(ah, AR_IMR, ahp->ah_maskReg); 573 /* Enable bus errors that are OR'd to set the HIUERR bit */ 574 OS_REG_WRITE(ah, AR_IMR_S2, 575 OS_REG_READ(ah, AR_IMR_S2) 576 | AR_IMR_S2_MCABT | AR_IMR_S2_SSERR | AR_IMR_S2_DPERR); 577 578 if (AH_PRIVATE(ah)->ah_rfkillEnabled) 579 ar5212EnableRfKill(ah); 580 581 if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) { 582 HALDEBUG(ah, HAL_DEBUG_ANY, 583 "%s: offset calibration failed to complete in 1ms;" 584 " noisy environment?\n", __func__); 585 } 586 587 /* 588 * Set clocks back to 32kHz if they had been using refClk, then 589 * use an external 32kHz crystal when sleeping, if one exists. 590 */ 591 ar5212SetupClock(ah, opmode); 592 593 /* 594 * Writing to AR_BEACON will start timers. Hence it should 595 * be the last register to be written. Do not reset tsf, do 596 * not enable beacons at this point, but preserve other values 597 * like beaconInterval. 598 */ 599 OS_REG_WRITE(ah, AR_BEACON, 600 (OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_EN | AR_BEACON_RESET_TSF))); 601 602 /* XXX Setup post reset EAR additions */ 603 604 /* QoS support */ 605 if (AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE || 606 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE && 607 AH_PRIVATE(ah)->ah_macRev >= AR_SREV_GRIFFIN_LITE)) { 608 OS_REG_WRITE(ah, AR_QOS_CONTROL, 0x100aa); /* XXX magic */ 609 OS_REG_WRITE(ah, AR_QOS_SELECT, 0x3210); /* XXX magic */ 610 } 611 612 /* Turn on NOACK Support for QoS packets */ 613 OS_REG_WRITE(ah, AR_NOACK, 614 SM(2, AR_NOACK_2BIT_VALUE) | 615 SM(5, AR_NOACK_BIT_OFFSET) | 616 SM(0, AR_NOACK_BYTE_OFFSET)); 617 618 /* Get Antenna Gain reduction */ 619 if (IEEE80211_IS_CHAN_5GHZ(chan)) { 620 ath_hal_eepromGet(ah, AR_EEP_ANTGAINMAX_5, &twiceAntennaGain); 621 } else { 622 ath_hal_eepromGet(ah, AR_EEP_ANTGAINMAX_2, &twiceAntennaGain); 623 } 624 twiceAntennaReduction = 625 ath_hal_getantennareduction(ah, chan, twiceAntennaGain); 626 627 /* TPC for self-generated frames */ 628 629 ackTpcPow = MS(ahp->ah_macTPC, AR_TPC_ACK); 630 if ((ackTpcPow-ahp->ah_txPowerIndexOffset) > chan->ic_maxpower) 631 ackTpcPow = chan->ic_maxpower+ahp->ah_txPowerIndexOffset; 632 633 if (ackTpcPow > (2*chan->ic_maxregpower - twiceAntennaReduction)) 634 ackTpcPow = (2*chan->ic_maxregpower - twiceAntennaReduction) 635 + ahp->ah_txPowerIndexOffset; 636 637 ctsTpcPow = MS(ahp->ah_macTPC, AR_TPC_CTS); 638 if ((ctsTpcPow-ahp->ah_txPowerIndexOffset) > chan->ic_maxpower) 639 ctsTpcPow = chan->ic_maxpower+ahp->ah_txPowerIndexOffset; 640 641 if (ctsTpcPow > (2*chan->ic_maxregpower - twiceAntennaReduction)) 642 ctsTpcPow = (2*chan->ic_maxregpower - twiceAntennaReduction) 643 + ahp->ah_txPowerIndexOffset; 644 645 chirpTpcPow = MS(ahp->ah_macTPC, AR_TPC_CHIRP); 646 if ((chirpTpcPow-ahp->ah_txPowerIndexOffset) > chan->ic_maxpower) 647 chirpTpcPow = chan->ic_maxpower+ahp->ah_txPowerIndexOffset; 648 649 if (chirpTpcPow > (2*chan->ic_maxregpower - twiceAntennaReduction)) 650 chirpTpcPow = (2*chan->ic_maxregpower - twiceAntennaReduction) 651 + ahp->ah_txPowerIndexOffset; 652 653 if (ackTpcPow > 63) 654 ackTpcPow = 63; 655 if (ctsTpcPow > 63) 656 ctsTpcPow = 63; 657 if (chirpTpcPow > 63) 658 chirpTpcPow = 63; 659 660 powerVal = SM(ackTpcPow, AR_TPC_ACK) | 661 SM(ctsTpcPow, AR_TPC_CTS) | 662 SM(chirpTpcPow, AR_TPC_CHIRP); 663 664 OS_REG_WRITE(ah, AR_TPC, powerVal); 665 666 /* Restore user-specified settings */ 667 if (ahp->ah_miscMode != 0) 668 OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode); 669 if (ahp->ah_sifstime != (u_int) -1) 670 ar5212SetSifsTime(ah, ahp->ah_sifstime); 671 if (ahp->ah_slottime != (u_int) -1) 672 ar5212SetSlotTime(ah, ahp->ah_slottime); 673 if (ahp->ah_acktimeout != (u_int) -1) 674 ar5212SetAckTimeout(ah, ahp->ah_acktimeout); 675 if (ahp->ah_ctstimeout != (u_int) -1) 676 ar5212SetCTSTimeout(ah, ahp->ah_ctstimeout); 677 if (AH_PRIVATE(ah)->ah_diagreg != 0) 678 OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg); 679 680 AH_PRIVATE(ah)->ah_opmode = opmode; /* record operating mode */ 681 #if 0 682 done: 683 #endif 684 if (bChannelChange && !IEEE80211_IS_CHAN_DFS(chan)) 685 chan->ic_state &= ~IEEE80211_CHANSTATE_CWINT; 686 687 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: done\n", __func__); 688 689 RESTORE_CCK(ah, chan, isBmode); 690 691 OS_MARK(ah, AH_MARK_RESET_DONE, 0); 692 693 return AH_TRUE; 694 bad: 695 RESTORE_CCK(ah, chan, isBmode); 696 697 OS_MARK(ah, AH_MARK_RESET_DONE, ecode); 698 if (status != AH_NULL) 699 *status = ecode; 700 return AH_FALSE; 701 #undef FAIL 702 #undef N 703 } 704 705 /* 706 * Call the rf backend to change the channel. 707 */ 708 HAL_BOOL 709 ar5212SetChannel(struct ath_hal *ah, const struct ieee80211_channel *chan) 710 { 711 struct ath_hal_5212 *ahp = AH5212(ah); 712 713 /* Change the synth */ 714 if (!ahp->ah_rfHal->setChannel(ah, chan)) 715 return AH_FALSE; 716 return AH_TRUE; 717 } 718 719 /* 720 * This channel change evaluates whether the selected hardware can 721 * perform a synthesizer-only channel change (no reset). If the 722 * TX is not stopped, or the RFBus cannot be granted in the given 723 * time, the function returns false as a reset is necessary 724 */ 725 HAL_BOOL 726 ar5212ChannelChange(struct ath_hal *ah, const struct ieee80211_channel *chan) 727 { 728 uint32_t ulCount; 729 uint32_t data, synthDelay, qnum; 730 uint16_t rfXpdGain[MAX_NUM_PDGAINS_PER_CHANNEL]; 731 HAL_BOOL txStopped = AH_TRUE; 732 HAL_CHANNEL_INTERNAL *ichan; 733 734 /* 735 * Map public channel to private. 736 */ 737 ichan = ath_hal_checkchannel(ah, chan); 738 739 /* TX must be stopped or RF Bus grant will not work */ 740 for (qnum = 0; qnum < AH_PRIVATE(ah)->ah_caps.halTotalQueues; qnum++) { 741 if (ar5212NumTxPending(ah, qnum)) { 742 txStopped = AH_FALSE; 743 break; 744 } 745 } 746 if (!txStopped) 747 return AH_FALSE; 748 749 /* Kill last Baseband Rx Frame */ 750 OS_REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_REQUEST); /* Request analog bus grant */ 751 for (ulCount = 0; ulCount < 100; ulCount++) { 752 if (OS_REG_READ(ah, AR_PHY_RFBUS_GNT)) 753 break; 754 OS_DELAY(5); 755 } 756 if (ulCount >= 100) 757 return AH_FALSE; 758 759 /* Change the synth */ 760 if (!ar5212SetChannel(ah, chan)) 761 return AH_FALSE; 762 763 /* 764 * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN). 765 * Read the phy active delay register. Value is in 100ns increments. 766 */ 767 data = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 768 if (IEEE80211_IS_CHAN_B(chan)) { 769 synthDelay = (4 * data) / 22; 770 } else { 771 synthDelay = data / 10; 772 } 773 OS_DELAY(synthDelay + BASE_ACTIVATE_DELAY); 774 775 /* Setup the transmit power values. */ 776 if (!ar5212SetTransmitPower(ah, chan, rfXpdGain)) { 777 HALDEBUG(ah, HAL_DEBUG_ANY, 778 "%s: error init'ing transmit power\n", __func__); 779 return AH_FALSE; 780 } 781 782 /* Write delta slope for OFDM enabled modes (A, G, Turbo) */ 783 if (IEEE80211_IS_CHAN_OFDM(chan)) { 784 if (IS_5413(ah) || 785 AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER5_3) 786 ar5212SetSpurMitigation(ah, chan); 787 ar5212SetDeltaSlope(ah, chan); 788 } 789 790 /* Release the RFBus Grant */ 791 OS_REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); 792 793 /* Start Noise Floor Cal */ 794 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); 795 return AH_TRUE; 796 } 797 798 void 799 ar5212SetOperatingMode(struct ath_hal *ah, int opmode) 800 { 801 uint32_t val; 802 803 val = OS_REG_READ(ah, AR_STA_ID1); 804 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC); 805 switch (opmode) { 806 case HAL_M_HOSTAP: 807 OS_REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP 808 | AR_STA_ID1_KSRCH_MODE); 809 OS_REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 810 break; 811 case HAL_M_IBSS: 812 OS_REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC 813 | AR_STA_ID1_KSRCH_MODE); 814 OS_REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 815 break; 816 case HAL_M_STA: 817 case HAL_M_MONITOR: 818 OS_REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE); 819 break; 820 } 821 } 822 823 /* 824 * Places the PHY and Radio chips into reset. A full reset 825 * must be called to leave this state. The PCI/MAC/PCU are 826 * not placed into reset as we must receive interrupt to 827 * re-enable the hardware. 828 */ 829 HAL_BOOL 830 ar5212PhyDisable(struct ath_hal *ah) 831 { 832 return ar5212SetResetReg(ah, AR_RC_BB); 833 } 834 835 /* 836 * Places all of hardware into reset 837 */ 838 HAL_BOOL 839 ar5212Disable(struct ath_hal *ah) 840 { 841 if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 842 return AH_FALSE; 843 /* 844 * Reset the HW - PCI must be reset after the rest of the 845 * device has been reset. 846 */ 847 return ar5212SetResetReg(ah, AR_RC_MAC | AR_RC_BB | AR_RC_PCI); 848 } 849 850 /* 851 * Places the hardware into reset and then pulls it out of reset 852 * 853 * TODO: Only write the PLL if we're changing to or from CCK mode 854 * 855 * WARNING: The order of the PLL and mode registers must be correct. 856 */ 857 HAL_BOOL 858 ar5212ChipReset(struct ath_hal *ah, const struct ieee80211_channel *chan) 859 { 860 861 OS_MARK(ah, AH_MARK_CHIPRESET, chan ? chan->ic_freq : 0); 862 863 /* 864 * Reset the HW - PCI must be reset after the rest of the 865 * device has been reset 866 */ 867 if (!ar5212SetResetReg(ah, AR_RC_MAC | AR_RC_BB | AR_RC_PCI)) 868 return AH_FALSE; 869 870 /* Bring out of sleep mode (AGAIN) */ 871 if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 872 return AH_FALSE; 873 874 /* Clear warm reset register */ 875 if (!ar5212SetResetReg(ah, 0)) 876 return AH_FALSE; 877 878 /* 879 * Perform warm reset before the mode/PLL/turbo registers 880 * are changed in order to deactivate the radio. Mode changes 881 * with an active radio can result in corrupted shifts to the 882 * radio device. 883 */ 884 885 /* 886 * Set CCK and Turbo modes correctly. 887 */ 888 if (chan != AH_NULL) { /* NB: can be null during attach */ 889 uint32_t rfMode, phyPLL = 0, curPhyPLL, turbo; 890 891 if (IS_5413(ah)) { /* NB: =>'s 5424 also */ 892 rfMode = AR_PHY_MODE_AR5112; 893 if (IEEE80211_IS_CHAN_HALF(chan)) 894 rfMode |= AR_PHY_MODE_HALF; 895 else if (IEEE80211_IS_CHAN_QUARTER(chan)) 896 rfMode |= AR_PHY_MODE_QUARTER; 897 898 if (IEEE80211_IS_CHAN_CCK(chan)) 899 phyPLL = AR_PHY_PLL_CTL_44_5112; 900 else 901 phyPLL = AR_PHY_PLL_CTL_40_5413; 902 } else if (IS_RAD5111(ah)) { 903 rfMode = AR_PHY_MODE_AR5111; 904 if (IEEE80211_IS_CHAN_CCK(chan)) 905 phyPLL = AR_PHY_PLL_CTL_44; 906 else 907 phyPLL = AR_PHY_PLL_CTL_40; 908 if (IEEE80211_IS_CHAN_HALF(chan)) 909 phyPLL = AR_PHY_PLL_CTL_HALF; 910 else if (IEEE80211_IS_CHAN_QUARTER(chan)) 911 phyPLL = AR_PHY_PLL_CTL_QUARTER; 912 } else { /* 5112, 2413, 2316, 2317 */ 913 rfMode = AR_PHY_MODE_AR5112; 914 if (IEEE80211_IS_CHAN_CCK(chan)) 915 phyPLL = AR_PHY_PLL_CTL_44_5112; 916 else 917 phyPLL = AR_PHY_PLL_CTL_40_5112; 918 if (IEEE80211_IS_CHAN_HALF(chan)) 919 phyPLL |= AR_PHY_PLL_CTL_HALF; 920 else if (IEEE80211_IS_CHAN_QUARTER(chan)) 921 phyPLL |= AR_PHY_PLL_CTL_QUARTER; 922 } 923 if (IEEE80211_IS_CHAN_G(chan)) 924 rfMode |= AR_PHY_MODE_DYNAMIC; 925 else if (IEEE80211_IS_CHAN_OFDM(chan)) 926 rfMode |= AR_PHY_MODE_OFDM; 927 else 928 rfMode |= AR_PHY_MODE_CCK; 929 if (IEEE80211_IS_CHAN_5GHZ(chan)) 930 rfMode |= AR_PHY_MODE_RF5GHZ; 931 else 932 rfMode |= AR_PHY_MODE_RF2GHZ; 933 turbo = IEEE80211_IS_CHAN_TURBO(chan) ? 934 (AR_PHY_FC_TURBO_MODE | AR_PHY_FC_TURBO_SHORT) : 0; 935 curPhyPLL = OS_REG_READ(ah, AR_PHY_PLL_CTL); 936 /* 937 * PLL, Mode, and Turbo values must be written in the correct 938 * order to ensure: 939 * - The PLL cannot be set to 44 unless the CCK or DYNAMIC 940 * mode bit is set 941 * - Turbo cannot be set at the same time as CCK or DYNAMIC 942 */ 943 if (IEEE80211_IS_CHAN_CCK(chan)) { 944 OS_REG_WRITE(ah, AR_PHY_TURBO, turbo); 945 OS_REG_WRITE(ah, AR_PHY_MODE, rfMode); 946 if (curPhyPLL != phyPLL) { 947 OS_REG_WRITE(ah, AR_PHY_PLL_CTL, phyPLL); 948 /* Wait for the PLL to settle */ 949 OS_DELAY(PLL_SETTLE_DELAY); 950 } 951 } else { 952 if (curPhyPLL != phyPLL) { 953 OS_REG_WRITE(ah, AR_PHY_PLL_CTL, phyPLL); 954 /* Wait for the PLL to settle */ 955 OS_DELAY(PLL_SETTLE_DELAY); 956 } 957 OS_REG_WRITE(ah, AR_PHY_TURBO, turbo); 958 OS_REG_WRITE(ah, AR_PHY_MODE, rfMode); 959 } 960 } 961 return AH_TRUE; 962 } 963 964 /* 965 * Recalibrate the lower PHY chips to account for temperature/environment 966 * changes. 967 */ 968 HAL_BOOL 969 ar5212PerCalibrationN(struct ath_hal *ah, 970 struct ieee80211_channel *chan, 971 u_int chainMask, HAL_BOOL longCal, HAL_BOOL *isCalDone) 972 { 973 #define IQ_CAL_TRIES 10 974 struct ath_hal_5212 *ahp = AH5212(ah); 975 HAL_CHANNEL_INTERNAL *ichan; 976 int32_t qCoff, qCoffDenom; 977 int32_t iqCorrMeas, iCoff, iCoffDenom; 978 uint32_t powerMeasQ, powerMeasI; 979 HAL_BOOL isBmode = AH_FALSE; 980 981 OS_MARK(ah, AH_MARK_PERCAL, chan->ic_freq); 982 *isCalDone = AH_FALSE; 983 ichan = ath_hal_checkchannel(ah, chan); 984 if (ichan == AH_NULL) { 985 HALDEBUG(ah, HAL_DEBUG_ANY, 986 "%s: invalid channel %u/0x%x; no mapping\n", 987 __func__, chan->ic_freq, chan->ic_flags); 988 return AH_FALSE; 989 } 990 SAVE_CCK(ah, chan, isBmode); 991 992 if (ahp->ah_bIQCalibration == IQ_CAL_DONE || 993 ahp->ah_bIQCalibration == IQ_CAL_INACTIVE) 994 *isCalDone = AH_TRUE; 995 996 /* IQ calibration in progress. Check to see if it has finished. */ 997 if (ahp->ah_bIQCalibration == IQ_CAL_RUNNING && 998 !(OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) & AR_PHY_TIMING_CTRL4_DO_IQCAL)) { 999 int i; 1000 1001 /* IQ Calibration has finished. */ 1002 ahp->ah_bIQCalibration = IQ_CAL_INACTIVE; 1003 *isCalDone = AH_TRUE; 1004 1005 /* workaround for misgated IQ Cal results */ 1006 i = 0; 1007 do { 1008 /* Read calibration results. */ 1009 powerMeasI = OS_REG_READ(ah, AR_PHY_IQCAL_RES_PWR_MEAS_I); 1010 powerMeasQ = OS_REG_READ(ah, AR_PHY_IQCAL_RES_PWR_MEAS_Q); 1011 iqCorrMeas = OS_REG_READ(ah, AR_PHY_IQCAL_RES_IQ_CORR_MEAS); 1012 if (powerMeasI && powerMeasQ) 1013 break; 1014 /* Do we really need this??? */ 1015 OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4, 1016 AR_PHY_TIMING_CTRL4_DO_IQCAL); 1017 } while (++i < IQ_CAL_TRIES); 1018 1019 HALDEBUG(ah, HAL_DEBUG_PERCAL, 1020 "%s: IQ cal finished: %d tries\n", __func__, i); 1021 HALDEBUG(ah, HAL_DEBUG_PERCAL, 1022 "%s: powerMeasI %u powerMeasQ %u iqCorrMeas %d\n", 1023 __func__, powerMeasI, powerMeasQ, iqCorrMeas); 1024 1025 /* 1026 * Prescale these values to remove 64-bit operation 1027 * requirement at the loss of a little precision. 1028 */ 1029 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128; 1030 qCoffDenom = powerMeasQ / 128; 1031 1032 /* Protect against divide-by-0 and loss of sign bits. */ 1033 if (iCoffDenom != 0 && qCoffDenom >= 2) { 1034 iCoff = (int8_t)(-iqCorrMeas) / iCoffDenom; 1035 /* IQCORR_Q_I_COFF is a signed 6 bit number */ 1036 if (iCoff < -32) { 1037 iCoff = -32; 1038 } else if (iCoff > 31) { 1039 iCoff = 31; 1040 } 1041 1042 /* IQCORR_Q_Q_COFF is a signed 5 bit number */ 1043 qCoff = (powerMeasI / qCoffDenom) - 128; 1044 if (qCoff < -16) { 1045 qCoff = -16; 1046 } else if (qCoff > 15) { 1047 qCoff = 15; 1048 } 1049 1050 HALDEBUG(ah, HAL_DEBUG_PERCAL, 1051 "%s: iCoff %d qCoff %d\n", __func__, iCoff, qCoff); 1052 1053 /* Write values and enable correction */ 1054 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4, 1055 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, iCoff); 1056 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4, 1057 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, qCoff); 1058 OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4, 1059 AR_PHY_TIMING_CTRL4_IQCORR_ENABLE); 1060 1061 ahp->ah_bIQCalibration = IQ_CAL_DONE; 1062 ichan->privFlags |= CHANNEL_IQVALID; 1063 ichan->iCoff = iCoff; 1064 ichan->qCoff = qCoff; 1065 } 1066 } else if (!IEEE80211_IS_CHAN_B(chan) && 1067 ahp->ah_bIQCalibration == IQ_CAL_DONE && 1068 (ichan->privFlags & CHANNEL_IQVALID) == 0) { 1069 /* 1070 * Start IQ calibration if configured channel has changed. 1071 * Use a magic number of 15 based on default value. 1072 */ 1073 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4, 1074 AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX, 1075 INIT_IQCAL_LOG_COUNT_MAX); 1076 OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4, 1077 AR_PHY_TIMING_CTRL4_DO_IQCAL); 1078 ahp->ah_bIQCalibration = IQ_CAL_RUNNING; 1079 } 1080 /* XXX EAR */ 1081 1082 if (longCal) { 1083 /* Check noise floor results */ 1084 ar5212GetNf(ah, chan); 1085 if (!IEEE80211_IS_CHAN_CWINT(chan)) { 1086 /* Perform cal for 5Ghz channels and any OFDM on 5112 */ 1087 if (IEEE80211_IS_CHAN_5GHZ(chan) || 1088 (IS_RAD5112(ah) && IEEE80211_IS_CHAN_OFDM(chan))) 1089 ar5212RequestRfgain(ah); 1090 } 1091 } 1092 RESTORE_CCK(ah, chan, isBmode); 1093 1094 return AH_TRUE; 1095 #undef IQ_CAL_TRIES 1096 } 1097 1098 HAL_BOOL 1099 ar5212PerCalibration(struct ath_hal *ah, struct ieee80211_channel *chan, 1100 HAL_BOOL *isIQdone) 1101 { 1102 return ar5212PerCalibrationN(ah, chan, 0x1, AH_TRUE, isIQdone); 1103 } 1104 1105 HAL_BOOL 1106 ar5212ResetCalValid(struct ath_hal *ah, const struct ieee80211_channel *chan) 1107 { 1108 HAL_CHANNEL_INTERNAL *ichan; 1109 1110 ichan = ath_hal_checkchannel(ah, chan); 1111 if (ichan == AH_NULL) { 1112 HALDEBUG(ah, HAL_DEBUG_ANY, 1113 "%s: invalid channel %u/0x%x; no mapping\n", 1114 __func__, chan->ic_freq, chan->ic_flags); 1115 return AH_FALSE; 1116 } 1117 ichan->privFlags &= ~CHANNEL_IQVALID; 1118 return AH_TRUE; 1119 } 1120 1121 /************************************************************** 1122 * ar5212MacStop 1123 * 1124 * Disables all active QCUs and ensure that the mac is in a 1125 * quiessence state. 1126 */ 1127 static HAL_BOOL 1128 ar5212MacStop(struct ath_hal *ah) 1129 { 1130 HAL_BOOL status; 1131 uint32_t count; 1132 uint32_t pendFrameCount; 1133 uint32_t macStateFlag; 1134 uint32_t queue; 1135 1136 status = AH_FALSE; 1137 1138 /* Disable Rx Operation ***********************************/ 1139 OS_REG_SET_BIT(ah, AR_CR, AR_CR_RXD); 1140 1141 /* Disable TX Operation ***********************************/ 1142 #ifdef NOT_YET 1143 ar5212SetTxdpInvalid(ah); 1144 #endif 1145 OS_REG_SET_BIT(ah, AR_Q_TXD, AR_Q_TXD_M); 1146 1147 /* Polling operation for completion of disable ************/ 1148 macStateFlag = TX_ENABLE_CHECK | RX_ENABLE_CHECK; 1149 1150 for (count = 0; count < MAX_RESET_WAIT; count++) { 1151 if (macStateFlag & RX_ENABLE_CHECK) { 1152 if (!OS_REG_IS_BIT_SET(ah, AR_CR, AR_CR_RXE)) { 1153 macStateFlag &= ~RX_ENABLE_CHECK; 1154 } 1155 } 1156 1157 if (macStateFlag & TX_ENABLE_CHECK) { 1158 if (!OS_REG_IS_BIT_SET(ah, AR_Q_TXE, AR_Q_TXE_M)) { 1159 macStateFlag &= ~TX_ENABLE_CHECK; 1160 macStateFlag |= TX_QUEUEPEND_CHECK; 1161 } 1162 } 1163 if (macStateFlag & TX_QUEUEPEND_CHECK) { 1164 pendFrameCount = 0; 1165 for (queue = 0; queue < AR_NUM_DCU; queue++) { 1166 pendFrameCount += OS_REG_READ(ah, 1167 AR_Q0_STS + (queue * 4)) & 1168 AR_Q_STS_PEND_FR_CNT; 1169 } 1170 if (pendFrameCount == 0) { 1171 macStateFlag &= ~TX_QUEUEPEND_CHECK; 1172 } 1173 } 1174 if (macStateFlag == 0) { 1175 status = AH_TRUE; 1176 break; 1177 } 1178 OS_DELAY(50); 1179 } 1180 1181 if (status != AH_TRUE) { 1182 HALDEBUG(ah, HAL_DEBUG_RESET, 1183 "%s:Failed to stop the MAC state 0x%x\n", 1184 __func__, macStateFlag); 1185 } 1186 1187 return status; 1188 } 1189 1190 1191 /* 1192 * Write the given reset bit mask into the reset register 1193 */ 1194 static HAL_BOOL 1195 ar5212SetResetReg(struct ath_hal *ah, uint32_t resetMask) 1196 { 1197 uint32_t mask = resetMask ? resetMask : ~0; 1198 HAL_BOOL rt; 1199 1200 /* Never reset the PCIE core */ 1201 if (AH_PRIVATE(ah)->ah_ispcie) { 1202 resetMask &= ~AR_RC_PCI; 1203 } 1204 1205 if (resetMask & (AR_RC_MAC | AR_RC_PCI)) { 1206 /* 1207 * To ensure that the driver can reset the 1208 * MAC, wake up the chip 1209 */ 1210 rt = ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE); 1211 1212 if (rt != AH_TRUE) { 1213 return rt; 1214 } 1215 1216 /* 1217 * Disable interrupts 1218 */ 1219 OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE); 1220 OS_REG_READ(ah, AR_IER); 1221 1222 if (ar5212MacStop(ah) != AH_TRUE) { 1223 /* 1224 * Failed to stop the MAC gracefully; let's be more forceful then 1225 */ 1226 1227 /* need some delay before flush any pending MMR writes */ 1228 OS_DELAY(15); 1229 OS_REG_READ(ah, AR_RXDP); 1230 1231 resetMask |= AR_RC_MAC | AR_RC_BB; 1232 /* _Never_ reset PCI Express core */ 1233 if (! AH_PRIVATE(ah)->ah_ispcie) { 1234 resetMask |= AR_RC_PCI; 1235 } 1236 #if 0 1237 /* 1238 * Flush the park address of the PCI controller 1239 */ 1240 /* Read PCI slot information less than Hainan revision */ 1241 if (AH_PRIVATE(ah)->ah_bustype == HAL_BUS_TYPE_PCI) { 1242 if (!IS_5112_REV5_UP(ah)) { 1243 #define PCI_COMMON_CONFIG_STATUS 0x06 1244 u_int32_t i; 1245 u_int16_t reg16; 1246 1247 for (i = 0; i < 32; i++) { 1248 ath_hal_read_pci_config_space(ah, 1249 PCI_COMMON_CONFIG_STATUS, 1250 ®16, sizeof(reg16)); 1251 } 1252 } 1253 #undef PCI_COMMON_CONFIG_STATUS 1254 } 1255 #endif 1256 } else { 1257 /* 1258 * MAC stopped gracefully; no need to warm-reset the PCI bus 1259 */ 1260 1261 resetMask &= ~AR_RC_PCI; 1262 1263 /* need some delay before flush any pending MMR writes */ 1264 OS_DELAY(15); 1265 OS_REG_READ(ah, AR_RXDP); 1266 } 1267 } 1268 1269 (void) OS_REG_READ(ah, AR_RXDP);/* flush any pending MMR writes */ 1270 OS_REG_WRITE(ah, AR_RC, resetMask); 1271 OS_DELAY(15); /* need to wait at least 128 clocks 1272 when reseting PCI before read */ 1273 mask &= (AR_RC_MAC | AR_RC_BB); 1274 resetMask &= (AR_RC_MAC | AR_RC_BB); 1275 rt = ath_hal_wait(ah, AR_RC, mask, resetMask); 1276 if ((resetMask & AR_RC_MAC) == 0) { 1277 if (isBigEndian()) { 1278 /* 1279 * Set CFG, little-endian for descriptor accesses. 1280 */ 1281 mask = INIT_CONFIG_STATUS | AR_CFG_SWRD; 1282 #ifndef AH_NEED_DESC_SWAP 1283 mask |= AR_CFG_SWTD; 1284 #endif 1285 OS_REG_WRITE(ah, AR_CFG, mask); 1286 } else 1287 OS_REG_WRITE(ah, AR_CFG, INIT_CONFIG_STATUS); 1288 if (ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 1289 (void) OS_REG_READ(ah, AR_ISR_RAC); 1290 } 1291 1292 /* track PHY power state so we don't try to r/w BB registers */ 1293 AH5212(ah)->ah_phyPowerOn = ((resetMask & AR_RC_BB) == 0); 1294 return rt; 1295 } 1296 1297 int16_t 1298 ar5212GetNoiseFloor(struct ath_hal *ah) 1299 { 1300 int16_t nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff; 1301 if (nf & 0x100) 1302 nf = 0 - ((nf ^ 0x1ff) + 1); 1303 return nf; 1304 } 1305 1306 static HAL_BOOL 1307 getNoiseFloorThresh(struct ath_hal *ah, const struct ieee80211_channel *chan, 1308 int16_t *nft) 1309 { 1310 const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 1311 1312 HALASSERT(ah->ah_magic == AR5212_MAGIC); 1313 1314 switch (chan->ic_flags & IEEE80211_CHAN_ALLFULL) { 1315 case IEEE80211_CHAN_A: 1316 *nft = ee->ee_noiseFloorThresh[headerInfo11A]; 1317 break; 1318 case IEEE80211_CHAN_B: 1319 *nft = ee->ee_noiseFloorThresh[headerInfo11B]; 1320 break; 1321 case IEEE80211_CHAN_G: 1322 case IEEE80211_CHAN_PUREG: /* NB: really 108G */ 1323 *nft = ee->ee_noiseFloorThresh[headerInfo11G]; 1324 break; 1325 default: 1326 HALDEBUG(ah, HAL_DEBUG_ANY, 1327 "%s: invalid channel flags %u/0x%x\n", 1328 __func__, chan->ic_freq, chan->ic_flags); 1329 return AH_FALSE; 1330 } 1331 return AH_TRUE; 1332 } 1333 1334 /* 1335 * Setup the noise floor cal history buffer. 1336 */ 1337 void 1338 ar5212InitNfCalHistBuffer(struct ath_hal *ah) 1339 { 1340 struct ath_hal_5212 *ahp = AH5212(ah); 1341 int i; 1342 1343 ahp->ah_nfCalHist.first_run = 1; 1344 ahp->ah_nfCalHist.currIndex = 0; 1345 ahp->ah_nfCalHist.privNF = AR5212_CCA_MAX_GOOD_VALUE; 1346 ahp->ah_nfCalHist.invalidNFcount = AR512_NF_CAL_HIST_MAX; 1347 for (i = 0; i < AR512_NF_CAL_HIST_MAX; i ++) 1348 ahp->ah_nfCalHist.nfCalBuffer[i] = AR5212_CCA_MAX_GOOD_VALUE; 1349 } 1350 1351 /* 1352 * Add a noise floor value to the ring buffer. 1353 */ 1354 static __inline void 1355 updateNFHistBuff(struct ar5212NfCalHist *h, int16_t nf) 1356 { 1357 h->nfCalBuffer[h->currIndex] = nf; 1358 if (++h->currIndex >= AR512_NF_CAL_HIST_MAX) 1359 h->currIndex = 0; 1360 } 1361 1362 /* 1363 * Return the median noise floor value in the ring buffer. 1364 */ 1365 int16_t 1366 ar5212GetNfHistMid(const int16_t calData[AR512_NF_CAL_HIST_MAX]) 1367 { 1368 int16_t sort[AR512_NF_CAL_HIST_MAX]; 1369 int i, j; 1370 1371 OS_MEMCPY(sort, calData, AR512_NF_CAL_HIST_MAX*sizeof(int16_t)); 1372 for (i = 0; i < AR512_NF_CAL_HIST_MAX-1; i ++) { 1373 for (j = 1; j < AR512_NF_CAL_HIST_MAX-i; j ++) { 1374 if (sort[j] > sort[j-1]) { 1375 int16_t nf = sort[j]; 1376 sort[j] = sort[j-1]; 1377 sort[j-1] = nf; 1378 } 1379 } 1380 } 1381 return sort[(AR512_NF_CAL_HIST_MAX-1)>>1]; 1382 } 1383 1384 /* 1385 * Read the NF and check it against the noise floor threshhold 1386 */ 1387 int16_t 1388 ar5212GetNf(struct ath_hal *ah, struct ieee80211_channel *chan) 1389 { 1390 struct ath_hal_5212 *ahp = AH5212(ah); 1391 struct ar5212NfCalHist *h = &ahp->ah_nfCalHist; 1392 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan); 1393 int16_t nf, nfThresh; 1394 int32_t val; 1395 1396 if (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) { 1397 HALDEBUG(ah, HAL_DEBUG_ANY, 1398 "%s: NF did not complete in calibration window\n", __func__); 1399 ichan->rawNoiseFloor = h->privNF; /* most recent value */ 1400 return ichan->rawNoiseFloor; 1401 } 1402 1403 /* 1404 * Finished NF cal, check against threshold. 1405 */ 1406 nf = ar5212GetNoiseFloor(ah); 1407 if (getNoiseFloorThresh(ah, chan, &nfThresh)) { 1408 if (nf > nfThresh) { 1409 HALDEBUG(ah, HAL_DEBUG_ANY, 1410 "%s: noise floor failed detected; detected %u, " 1411 "threshold %u\n", __func__, nf, nfThresh); 1412 /* 1413 * NB: Don't discriminate 2.4 vs 5Ghz, if this 1414 * happens it indicates a problem regardless 1415 * of the band. 1416 */ 1417 chan->ic_state |= IEEE80211_CHANSTATE_CWINT; 1418 nf = 0; 1419 } 1420 } else 1421 nf = 0; 1422 1423 /* 1424 * Pass through histogram and write median value as 1425 * calculated from the accrued window. We require a 1426 * full window of in-range values to be seen before we 1427 * start using the history. 1428 */ 1429 updateNFHistBuff(h, nf); 1430 if (h->first_run) { 1431 if (nf < AR5212_CCA_MIN_BAD_VALUE || 1432 nf > AR5212_CCA_MAX_HIGH_VALUE) { 1433 nf = AR5212_CCA_MAX_GOOD_VALUE; 1434 h->invalidNFcount = AR512_NF_CAL_HIST_MAX; 1435 } else if (--(h->invalidNFcount) == 0) { 1436 h->first_run = 0; 1437 h->privNF = nf = ar5212GetNfHistMid(h->nfCalBuffer); 1438 } else { 1439 nf = AR5212_CCA_MAX_GOOD_VALUE; 1440 } 1441 } else { 1442 h->privNF = nf = ar5212GetNfHistMid(h->nfCalBuffer); 1443 } 1444 1445 val = OS_REG_READ(ah, AR_PHY(25)); 1446 val &= 0xFFFFFE00; 1447 val |= (((uint32_t)nf << 1) & 0x1FF); 1448 OS_REG_WRITE(ah, AR_PHY(25), val); 1449 OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF); 1450 OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF); 1451 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); 1452 1453 if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF, 0)) { 1454 #ifdef AH_DEBUG 1455 ath_hal_printf(ah, "%s: AGC not ready AGC_CONTROL 0x%x\n", 1456 __func__, OS_REG_READ(ah, AR_PHY_AGC_CONTROL)); 1457 #endif 1458 } 1459 1460 /* 1461 * Now load a high maxCCAPower value again so that we're 1462 * not capped by the median we just loaded 1463 */ 1464 val &= 0xFFFFFE00; 1465 val |= (((uint32_t)(-50) << 1) & 0x1FF); 1466 OS_REG_WRITE(ah, AR_PHY(25), val); 1467 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF); 1468 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF); 1469 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); 1470 1471 return (ichan->rawNoiseFloor = nf); 1472 } 1473 1474 /* 1475 * Set up compression configuration registers 1476 */ 1477 void 1478 ar5212SetCompRegs(struct ath_hal *ah) 1479 { 1480 struct ath_hal_5212 *ahp = AH5212(ah); 1481 int i; 1482 1483 /* Check if h/w supports compression */ 1484 if (!AH_PRIVATE(ah)->ah_caps.halCompressSupport) 1485 return; 1486 1487 OS_REG_WRITE(ah, AR_DCCFG, 1); 1488 1489 OS_REG_WRITE(ah, AR_CCFG, 1490 (AR_COMPRESSION_WINDOW_SIZE >> 8) & AR_CCFG_WIN_M); 1491 1492 OS_REG_WRITE(ah, AR_CCFG, 1493 OS_REG_READ(ah, AR_CCFG) | AR_CCFG_MIB_INT_EN); 1494 OS_REG_WRITE(ah, AR_CCUCFG, 1495 AR_CCUCFG_RESET_VAL | AR_CCUCFG_CATCHUP_EN); 1496 1497 OS_REG_WRITE(ah, AR_CPCOVF, 0); 1498 1499 /* reset decompression mask */ 1500 for (i = 0; i < HAL_DECOMP_MASK_SIZE; i++) { 1501 OS_REG_WRITE(ah, AR_DCM_A, i); 1502 OS_REG_WRITE(ah, AR_DCM_D, ahp->ah_decompMask[i]); 1503 } 1504 } 1505 1506 HAL_BOOL 1507 ar5212SetAntennaSwitchInternal(struct ath_hal *ah, HAL_ANT_SETTING settings, 1508 const struct ieee80211_channel *chan) 1509 { 1510 #define ANT_SWITCH_TABLE1 AR_PHY(88) 1511 #define ANT_SWITCH_TABLE2 AR_PHY(89) 1512 struct ath_hal_5212 *ahp = AH5212(ah); 1513 const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 1514 uint32_t antSwitchA, antSwitchB; 1515 int ix; 1516 1517 HALASSERT(ah->ah_magic == AR5212_MAGIC); 1518 HALASSERT(ahp->ah_phyPowerOn); 1519 1520 switch (chan->ic_flags & IEEE80211_CHAN_ALLFULL) { 1521 case IEEE80211_CHAN_A: 1522 ix = 0; 1523 break; 1524 case IEEE80211_CHAN_G: 1525 case IEEE80211_CHAN_PUREG: /* NB: 108G */ 1526 ix = 2; 1527 break; 1528 case IEEE80211_CHAN_B: 1529 if (IS_2425(ah) || IS_2417(ah)) { 1530 /* NB: Nala/Swan: 11b is handled using 11g */ 1531 ix = 2; 1532 } else 1533 ix = 1; 1534 break; 1535 default: 1536 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n", 1537 __func__, chan->ic_flags); 1538 return AH_FALSE; 1539 } 1540 1541 antSwitchA = ee->ee_antennaControl[1][ix] 1542 | (ee->ee_antennaControl[2][ix] << 6) 1543 | (ee->ee_antennaControl[3][ix] << 12) 1544 | (ee->ee_antennaControl[4][ix] << 18) 1545 | (ee->ee_antennaControl[5][ix] << 24) 1546 ; 1547 antSwitchB = ee->ee_antennaControl[6][ix] 1548 | (ee->ee_antennaControl[7][ix] << 6) 1549 | (ee->ee_antennaControl[8][ix] << 12) 1550 | (ee->ee_antennaControl[9][ix] << 18) 1551 | (ee->ee_antennaControl[10][ix] << 24) 1552 ; 1553 /* 1554 * For fixed antenna, give the same setting for both switch banks 1555 */ 1556 switch (settings) { 1557 case HAL_ANT_FIXED_A: 1558 antSwitchB = antSwitchA; 1559 break; 1560 case HAL_ANT_FIXED_B: 1561 antSwitchA = antSwitchB; 1562 break; 1563 case HAL_ANT_VARIABLE: 1564 break; 1565 default: 1566 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad antenna setting %u\n", 1567 __func__, settings); 1568 return AH_FALSE; 1569 } 1570 if (antSwitchB == antSwitchA) { 1571 HALDEBUG(ah, HAL_DEBUG_RFPARAM, 1572 "%s: Setting fast diversity off.\n", __func__); 1573 OS_REG_CLR_BIT(ah,AR_PHY_CCK_DETECT, 1574 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); 1575 ahp->ah_diversity = AH_FALSE; 1576 } else { 1577 HALDEBUG(ah, HAL_DEBUG_RFPARAM, 1578 "%s: Setting fast diversity on.\n", __func__); 1579 OS_REG_SET_BIT(ah,AR_PHY_CCK_DETECT, 1580 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); 1581 ahp->ah_diversity = AH_TRUE; 1582 } 1583 ahp->ah_antControl = settings; 1584 1585 OS_REG_WRITE(ah, ANT_SWITCH_TABLE1, antSwitchA); 1586 OS_REG_WRITE(ah, ANT_SWITCH_TABLE2, antSwitchB); 1587 1588 return AH_TRUE; 1589 #undef ANT_SWITCH_TABLE2 1590 #undef ANT_SWITCH_TABLE1 1591 } 1592 1593 HAL_BOOL 1594 ar5212IsSpurChannel(struct ath_hal *ah, const struct ieee80211_channel *chan) 1595 { 1596 uint16_t freq = ath_hal_gethwchannel(ah, chan); 1597 uint32_t clockFreq = 1598 ((IS_5413(ah) || IS_RAD5112_ANY(ah) || IS_2417(ah)) ? 40 : 32); 1599 return ( ((freq % clockFreq) != 0) 1600 && (((freq % clockFreq) < 10) 1601 || (((freq) % clockFreq) > 22)) ); 1602 } 1603 1604 /* 1605 * Read EEPROM header info and program the device for correct operation 1606 * given the channel value. 1607 */ 1608 HAL_BOOL 1609 ar5212SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan) 1610 { 1611 #define NO_FALSE_DETECT_BACKOFF 2 1612 #define CB22_FALSE_DETECT_BACKOFF 6 1613 #define AR_PHY_BIS(_ah, _reg, _mask, _val) \ 1614 OS_REG_WRITE(_ah, AR_PHY(_reg), \ 1615 (OS_REG_READ(_ah, AR_PHY(_reg)) & _mask) | (_val)); 1616 struct ath_hal_5212 *ahp = AH5212(ah); 1617 const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 1618 int arrayMode, falseDectectBackoff; 1619 int is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 1620 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan); 1621 int8_t adcDesiredSize, pgaDesiredSize; 1622 uint16_t switchSettling, txrxAtten, rxtxMargin; 1623 int iCoff, qCoff; 1624 1625 HALASSERT(ah->ah_magic == AR5212_MAGIC); 1626 1627 switch (chan->ic_flags & IEEE80211_CHAN_ALLTURBOFULL) { 1628 case IEEE80211_CHAN_A: 1629 case IEEE80211_CHAN_ST: 1630 arrayMode = headerInfo11A; 1631 if (!IS_RAD5112_ANY(ah) && !IS_2413(ah) && !IS_5413(ah)) 1632 OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, 1633 AR_PHY_FRAME_CTL_TX_CLIP, 1634 ahp->ah_gainValues.currStep->paramVal[GP_TXCLIP]); 1635 break; 1636 case IEEE80211_CHAN_B: 1637 arrayMode = headerInfo11B; 1638 break; 1639 case IEEE80211_CHAN_G: 1640 case IEEE80211_CHAN_108G: 1641 arrayMode = headerInfo11G; 1642 break; 1643 default: 1644 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n", 1645 __func__, chan->ic_flags); 1646 return AH_FALSE; 1647 } 1648 1649 /* Set the antenna register(s) correctly for the chip revision */ 1650 AR_PHY_BIS(ah, 68, 0xFFFFFC06, 1651 (ee->ee_antennaControl[0][arrayMode] << 4) | 0x1); 1652 1653 ar5212SetAntennaSwitchInternal(ah, ahp->ah_antControl, chan); 1654 1655 /* Set the Noise Floor Thresh on ar5211 devices */ 1656 OS_REG_WRITE(ah, AR_PHY(90), 1657 (ee->ee_noiseFloorThresh[arrayMode] & 0x1FF) 1658 | (1 << 9)); 1659 1660 if (ee->ee_version >= AR_EEPROM_VER5_0 && IEEE80211_IS_CHAN_TURBO(chan)) { 1661 switchSettling = ee->ee_switchSettlingTurbo[is2GHz]; 1662 adcDesiredSize = ee->ee_adcDesiredSizeTurbo[is2GHz]; 1663 pgaDesiredSize = ee->ee_pgaDesiredSizeTurbo[is2GHz]; 1664 txrxAtten = ee->ee_txrxAttenTurbo[is2GHz]; 1665 rxtxMargin = ee->ee_rxtxMarginTurbo[is2GHz]; 1666 } else { 1667 switchSettling = ee->ee_switchSettling[arrayMode]; 1668 adcDesiredSize = ee->ee_adcDesiredSize[arrayMode]; 1669 pgaDesiredSize = ee->ee_pgaDesiredSize[is2GHz]; 1670 txrxAtten = ee->ee_txrxAtten[is2GHz]; 1671 rxtxMargin = ee->ee_rxtxMargin[is2GHz]; 1672 } 1673 1674 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, 1675 AR_PHY_SETTLING_SWITCH, switchSettling); 1676 OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, 1677 AR_PHY_DESIRED_SZ_ADC, adcDesiredSize); 1678 OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, 1679 AR_PHY_DESIRED_SZ_PGA, pgaDesiredSize); 1680 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN, 1681 AR_PHY_RXGAIN_TXRX_ATTEN, txrxAtten); 1682 OS_REG_WRITE(ah, AR_PHY(13), 1683 (ee->ee_txEndToXPAOff[arrayMode] << 24) 1684 | (ee->ee_txEndToXPAOff[arrayMode] << 16) 1685 | (ee->ee_txFrameToXPAOn[arrayMode] << 8) 1686 | ee->ee_txFrameToXPAOn[arrayMode]); 1687 AR_PHY_BIS(ah, 10, 0xFFFF00FF, 1688 ee->ee_txEndToXLNAOn[arrayMode] << 8); 1689 AR_PHY_BIS(ah, 25, 0xFFF80FFF, 1690 (ee->ee_thresh62[arrayMode] << 12) & 0x7F000); 1691 1692 /* 1693 * False detect backoff - suspected 32 MHz spur causes false 1694 * detects in OFDM, causing Tx Hangs. Decrease weak signal 1695 * sensitivity for this card. 1696 */ 1697 falseDectectBackoff = NO_FALSE_DETECT_BACKOFF; 1698 if (ee->ee_version < AR_EEPROM_VER3_3) { 1699 /* XXX magic number */ 1700 if (AH_PRIVATE(ah)->ah_subvendorid == 0x1022 && 1701 IEEE80211_IS_CHAN_OFDM(chan)) 1702 falseDectectBackoff += CB22_FALSE_DETECT_BACKOFF; 1703 } else { 1704 if (ar5212IsSpurChannel(ah, chan)) 1705 falseDectectBackoff += ee->ee_falseDetectBackoff[arrayMode]; 1706 } 1707 AR_PHY_BIS(ah, 73, 0xFFFFFF01, (falseDectectBackoff << 1) & 0xFE); 1708 1709 if (ichan->privFlags & CHANNEL_IQVALID) { 1710 iCoff = ichan->iCoff; 1711 qCoff = ichan->qCoff; 1712 } else { 1713 iCoff = ee->ee_iqCalI[is2GHz]; 1714 qCoff = ee->ee_iqCalQ[is2GHz]; 1715 } 1716 1717 /* write previous IQ results */ 1718 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4, 1719 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, iCoff); 1720 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4, 1721 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, qCoff); 1722 OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4, 1723 AR_PHY_TIMING_CTRL4_IQCORR_ENABLE); 1724 1725 if (ee->ee_version >= AR_EEPROM_VER4_1) { 1726 if (!IEEE80211_IS_CHAN_108G(chan) || ee->ee_version >= AR_EEPROM_VER5_0) 1727 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, 1728 AR_PHY_GAIN_2GHZ_RXTX_MARGIN, rxtxMargin); 1729 } 1730 if (ee->ee_version >= AR_EEPROM_VER5_1) { 1731 /* for now always disabled */ 1732 OS_REG_WRITE(ah, AR_PHY_HEAVY_CLIP_ENABLE, 0); 1733 } 1734 1735 return AH_TRUE; 1736 #undef AR_PHY_BIS 1737 #undef NO_FALSE_DETECT_BACKOFF 1738 #undef CB22_FALSE_DETECT_BACKOFF 1739 } 1740 1741 /* 1742 * Apply Spur Immunity to Boards that require it. 1743 * Applies only to OFDM RX operation. 1744 */ 1745 1746 void 1747 ar5212SetSpurMitigation(struct ath_hal *ah, 1748 const struct ieee80211_channel *chan) 1749 { 1750 uint32_t pilotMask[2] = {0, 0}, binMagMask[4] = {0, 0, 0 , 0}; 1751 uint16_t i, finalSpur, curChanAsSpur, binWidth = 0, spurDetectWidth, spurChan; 1752 int32_t spurDeltaPhase = 0, spurFreqSd = 0, spurOffset, binOffsetNumT16, curBinOffset; 1753 int16_t numBinOffsets; 1754 static const uint16_t magMapFor4[4] = {1, 2, 2, 1}; 1755 static const uint16_t magMapFor3[3] = {1, 2, 1}; 1756 const uint16_t *pMagMap; 1757 HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 1758 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan); 1759 uint32_t val; 1760 1761 #define CHAN_TO_SPUR(_f, _freq) ( ((_freq) - ((_f) ? 2300 : 4900)) * 10 ) 1762 if (IS_2417(ah)) { 1763 HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: no spur mitigation\n", 1764 __func__); 1765 return; 1766 } 1767 1768 curChanAsSpur = CHAN_TO_SPUR(is2GHz, ichan->channel); 1769 1770 if (ichan->mainSpur) { 1771 /* Pull out the saved spur value */ 1772 finalSpur = ichan->mainSpur; 1773 } else { 1774 /* 1775 * Check if spur immunity should be performed for this channel 1776 * Should only be performed once per channel and then saved 1777 */ 1778 finalSpur = AR_NO_SPUR; 1779 spurDetectWidth = HAL_SPUR_CHAN_WIDTH; 1780 if (IEEE80211_IS_CHAN_TURBO(chan)) 1781 spurDetectWidth *= 2; 1782 1783 /* Decide if any spur affects the current channel */ 1784 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 1785 spurChan = ath_hal_getSpurChan(ah, i, is2GHz); 1786 if (spurChan == AR_NO_SPUR) { 1787 break; 1788 } 1789 if ((curChanAsSpur - spurDetectWidth <= (spurChan & HAL_SPUR_VAL_MASK)) && 1790 (curChanAsSpur + spurDetectWidth >= (spurChan & HAL_SPUR_VAL_MASK))) { 1791 finalSpur = spurChan & HAL_SPUR_VAL_MASK; 1792 break; 1793 } 1794 } 1795 /* Save detected spur (or no spur) for this channel */ 1796 ichan->mainSpur = finalSpur; 1797 } 1798 1799 /* Write spur immunity data */ 1800 if (finalSpur == AR_NO_SPUR) { 1801 /* Disable Spur Immunity Regs if they appear set */ 1802 if (OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) & AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER) { 1803 /* Clear Spur Delta Phase, Spur Freq, and enable bits */ 1804 OS_REG_RMW_FIELD(ah, AR_PHY_MASK_CTL, AR_PHY_MASK_CTL_RATE, 0); 1805 val = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4); 1806 val &= ~(AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 1807 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 1808 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 1809 OS_REG_WRITE(ah, AR_PHY_MASK_CTL, val); 1810 OS_REG_WRITE(ah, AR_PHY_TIMING11, 0); 1811 1812 /* Clear pilot masks */ 1813 OS_REG_WRITE(ah, AR_PHY_TIMING7, 0); 1814 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING8, AR_PHY_TIMING8_PILOT_MASK_2, 0); 1815 OS_REG_WRITE(ah, AR_PHY_TIMING9, 0); 1816 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING10, AR_PHY_TIMING10_PILOT_MASK_2, 0); 1817 1818 /* Clear magnitude masks */ 1819 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, 0); 1820 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, 0); 1821 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, 0); 1822 OS_REG_RMW_FIELD(ah, AR_PHY_MASK_CTL, AR_PHY_MASK_CTL_MASK_4, 0); 1823 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, 0); 1824 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, 0); 1825 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, 0); 1826 OS_REG_RMW_FIELD(ah, AR_PHY_BIN_MASK2_4, AR_PHY_BIN_MASK2_4_MASK_4, 0); 1827 } 1828 } else { 1829 spurOffset = finalSpur - curChanAsSpur; 1830 /* 1831 * Spur calculations: 1832 * spurDeltaPhase is (spurOffsetIn100KHz / chipFrequencyIn100KHz) << 21 1833 * spurFreqSd is (spurOffsetIn100KHz / sampleFrequencyIn100KHz) << 11 1834 */ 1835 if (IEEE80211_IS_CHAN_TURBO(chan)) { 1836 /* Chip Frequency & sampleFrequency are 80 MHz */ 1837 spurDeltaPhase = (spurOffset << 16) / 25; 1838 spurFreqSd = spurDeltaPhase >> 10; 1839 binWidth = HAL_BIN_WIDTH_TURBO_100HZ; 1840 } else if (IEEE80211_IS_CHAN_G(chan)) { 1841 /* Chip Frequency is 44MHz, sampleFrequency is 40 MHz */ 1842 spurFreqSd = (spurOffset << 8) / 55; 1843 spurDeltaPhase = (spurOffset << 17) / 25; 1844 binWidth = HAL_BIN_WIDTH_BASE_100HZ; 1845 } else { 1846 HALASSERT(!IEEE80211_IS_CHAN_B(chan)); 1847 /* Chip Frequency & sampleFrequency are 40 MHz */ 1848 spurDeltaPhase = (spurOffset << 17) / 25; 1849 spurFreqSd = spurDeltaPhase >> 10; 1850 binWidth = HAL_BIN_WIDTH_BASE_100HZ; 1851 } 1852 1853 /* Compute Pilot Mask */ 1854 binOffsetNumT16 = ((spurOffset * 1000) << 4) / binWidth; 1855 /* The spur is on a bin if it's remainder at times 16 is 0 */ 1856 if (binOffsetNumT16 & 0xF) { 1857 numBinOffsets = 4; 1858 pMagMap = magMapFor4; 1859 } else { 1860 numBinOffsets = 3; 1861 pMagMap = magMapFor3; 1862 } 1863 for (i = 0; i < numBinOffsets; i++) { 1864 if ((binOffsetNumT16 >> 4) > HAL_MAX_BINS_ALLOWED) { 1865 HALDEBUG(ah, HAL_DEBUG_ANY, 1866 "Too man bins in spur mitigation\n"); 1867 return; 1868 } 1869 1870 /* Get Pilot Mask values */ 1871 curBinOffset = (binOffsetNumT16 >> 4) + i + 25; 1872 if ((curBinOffset >= 0) && (curBinOffset <= 32)) { 1873 if (curBinOffset <= 25) 1874 pilotMask[0] |= 1 << curBinOffset; 1875 else if (curBinOffset >= 27) 1876 pilotMask[0] |= 1 << (curBinOffset - 1); 1877 } else if ((curBinOffset >= 33) && (curBinOffset <= 52)) 1878 pilotMask[1] |= 1 << (curBinOffset - 33); 1879 1880 /* Get viterbi values */ 1881 if ((curBinOffset >= -1) && (curBinOffset <= 14)) 1882 binMagMask[0] |= pMagMap[i] << (curBinOffset + 1) * 2; 1883 else if ((curBinOffset >= 15) && (curBinOffset <= 30)) 1884 binMagMask[1] |= pMagMap[i] << (curBinOffset - 15) * 2; 1885 else if ((curBinOffset >= 31) && (curBinOffset <= 46)) 1886 binMagMask[2] |= pMagMap[i] << (curBinOffset -31) * 2; 1887 else if((curBinOffset >= 47) && (curBinOffset <= 53)) 1888 binMagMask[3] |= pMagMap[i] << (curBinOffset -47) * 2; 1889 } 1890 1891 /* Write Spur Delta Phase, Spur Freq, and enable bits */ 1892 OS_REG_RMW_FIELD(ah, AR_PHY_MASK_CTL, AR_PHY_MASK_CTL_RATE, 0xFF); 1893 val = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4); 1894 val |= (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 1895 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 1896 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 1897 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4, val); 1898 OS_REG_WRITE(ah, AR_PHY_TIMING11, AR_PHY_TIMING11_USE_SPUR_IN_AGC | 1899 SM(spurFreqSd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 1900 SM(spurDeltaPhase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 1901 1902 /* Write pilot masks */ 1903 OS_REG_WRITE(ah, AR_PHY_TIMING7, pilotMask[0]); 1904 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING8, AR_PHY_TIMING8_PILOT_MASK_2, pilotMask[1]); 1905 OS_REG_WRITE(ah, AR_PHY_TIMING9, pilotMask[0]); 1906 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING10, AR_PHY_TIMING10_PILOT_MASK_2, pilotMask[1]); 1907 1908 /* Write magnitude masks */ 1909 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, binMagMask[0]); 1910 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, binMagMask[1]); 1911 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, binMagMask[2]); 1912 OS_REG_RMW_FIELD(ah, AR_PHY_MASK_CTL, AR_PHY_MASK_CTL_MASK_4, binMagMask[3]); 1913 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, binMagMask[0]); 1914 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, binMagMask[1]); 1915 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, binMagMask[2]); 1916 OS_REG_RMW_FIELD(ah, AR_PHY_BIN_MASK2_4, AR_PHY_BIN_MASK2_4_MASK_4, binMagMask[3]); 1917 } 1918 #undef CHAN_TO_SPUR 1919 } 1920 1921 1922 /* 1923 * Delta slope coefficient computation. 1924 * Required for OFDM operation. 1925 */ 1926 void 1927 ar5212SetDeltaSlope(struct ath_hal *ah, const struct ieee80211_channel *chan) 1928 { 1929 #define COEF_SCALE_S 24 1930 #define INIT_CLOCKMHZSCALED 0x64000000 1931 uint16_t freq = ath_hal_gethwchannel(ah, chan); 1932 unsigned long coef_scaled, coef_exp, coef_man, ds_coef_exp, ds_coef_man; 1933 unsigned long clockMhzScaled = INIT_CLOCKMHZSCALED; 1934 1935 if (IEEE80211_IS_CHAN_TURBO(chan)) 1936 clockMhzScaled *= 2; 1937 /* half and quarter rate can divide the scaled clock by 2 or 4 respectively */ 1938 /* scale for selected channel bandwidth */ 1939 if (IEEE80211_IS_CHAN_HALF(chan)) { 1940 clockMhzScaled = clockMhzScaled >> 1; 1941 } else if (IEEE80211_IS_CHAN_QUARTER(chan)) { 1942 clockMhzScaled = clockMhzScaled >> 2; 1943 } 1944 1945 /* 1946 * ALGO -> coef = 1e8/fcarrier*fclock/40; 1947 * scaled coef to provide precision for this floating calculation 1948 */ 1949 coef_scaled = clockMhzScaled / freq; 1950 1951 /* 1952 * ALGO -> coef_exp = 14-floor(log2(coef)); 1953 * floor(log2(x)) is the highest set bit position 1954 */ 1955 for (coef_exp = 31; coef_exp > 0; coef_exp--) 1956 if ((coef_scaled >> coef_exp) & 0x1) 1957 break; 1958 /* A coef_exp of 0 is a legal bit position but an unexpected coef_exp */ 1959 HALASSERT(coef_exp); 1960 coef_exp = 14 - (coef_exp - COEF_SCALE_S); 1961 1962 /* 1963 * ALGO -> coef_man = floor(coef* 2^coef_exp+0.5); 1964 * The coefficient is already shifted up for scaling 1965 */ 1966 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); 1967 ds_coef_man = coef_man >> (COEF_SCALE_S - coef_exp); 1968 ds_coef_exp = coef_exp - 16; 1969 1970 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3, 1971 AR_PHY_TIMING3_DSC_MAN, ds_coef_man); 1972 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3, 1973 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp); 1974 #undef INIT_CLOCKMHZSCALED 1975 #undef COEF_SCALE_S 1976 } 1977 1978 /* 1979 * Set a limit on the overall output power. Used for dynamic 1980 * transmit power control and the like. 1981 * 1982 * NB: limit is in units of 0.5 dbM. 1983 */ 1984 HAL_BOOL 1985 ar5212SetTxPowerLimit(struct ath_hal *ah, uint32_t limit) 1986 { 1987 /* XXX blech, construct local writable copy */ 1988 struct ieee80211_channel dummy = *AH_PRIVATE(ah)->ah_curchan; 1989 uint16_t dummyXpdGains[2]; 1990 HAL_BOOL isBmode; 1991 1992 SAVE_CCK(ah, &dummy, isBmode); 1993 AH_PRIVATE(ah)->ah_powerLimit = AH_MIN(limit, MAX_RATE_POWER); 1994 return ar5212SetTransmitPower(ah, &dummy, dummyXpdGains); 1995 } 1996 1997 /* 1998 * Set the transmit power in the baseband for the given 1999 * operating channel and mode. 2000 */ 2001 HAL_BOOL 2002 ar5212SetTransmitPower(struct ath_hal *ah, 2003 const struct ieee80211_channel *chan, uint16_t *rfXpdGain) 2004 { 2005 #define POW_OFDM(_r, _s) (((0 & 1)<< ((_s)+6)) | (((_r) & 0x3f) << (_s))) 2006 #define POW_CCK(_r, _s) (((_r) & 0x3f) << (_s)) 2007 #define N(a) (sizeof (a) / sizeof (a[0])) 2008 static const uint16_t tpcScaleReductionTable[5] = 2009 { 0, 3, 6, 9, MAX_RATE_POWER }; 2010 struct ath_hal_5212 *ahp = AH5212(ah); 2011 uint16_t freq = ath_hal_gethwchannel(ah, chan); 2012 const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 2013 int16_t minPower, maxPower, tpcInDb, powerLimit; 2014 int i; 2015 2016 HALASSERT(ah->ah_magic == AR5212_MAGIC); 2017 2018 OS_MEMZERO(ahp->ah_pcdacTable, ahp->ah_pcdacTableSize); 2019 OS_MEMZERO(ahp->ah_ratesArray, sizeof(ahp->ah_ratesArray)); 2020 2021 powerLimit = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit); 2022 if (powerLimit >= MAX_RATE_POWER || powerLimit == 0) 2023 tpcInDb = tpcScaleReductionTable[AH_PRIVATE(ah)->ah_tpScale]; 2024 else 2025 tpcInDb = 0; 2026 if (!ar5212SetRateTable(ah, chan, tpcInDb, powerLimit, 2027 AH_TRUE, &minPower, &maxPower)) { 2028 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set rate table\n", 2029 __func__); 2030 return AH_FALSE; 2031 } 2032 if (!ahp->ah_rfHal->setPowerTable(ah, 2033 &minPower, &maxPower, chan, rfXpdGain)) { 2034 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set power table\n", 2035 __func__); 2036 return AH_FALSE; 2037 } 2038 2039 /* 2040 * Adjust XR power/rate up by 2 dB to account for greater peak 2041 * to avg ratio - except in newer avg power designs 2042 */ 2043 if (!IS_2413(ah) && !IS_5413(ah)) 2044 ahp->ah_ratesArray[15] += 4; 2045 /* 2046 * txPowerIndexOffset is set by the SetPowerTable() call - 2047 * adjust the rate table 2048 */ 2049 for (i = 0; i < N(ahp->ah_ratesArray); i++) { 2050 ahp->ah_ratesArray[i] += ahp->ah_txPowerIndexOffset; 2051 if (ahp->ah_ratesArray[i] > 63) 2052 ahp->ah_ratesArray[i] = 63; 2053 } 2054 2055 if (ee->ee_eepMap < 2) { 2056 /* 2057 * Correct gain deltas for 5212 G operation - 2058 * Removed with revised chipset 2059 */ 2060 if (AH_PRIVATE(ah)->ah_phyRev < AR_PHY_CHIP_ID_REV_2 && 2061 IEEE80211_IS_CHAN_G(chan)) { 2062 uint16_t cckOfdmPwrDelta; 2063 2064 if (freq == 2484) 2065 cckOfdmPwrDelta = SCALE_OC_DELTA( 2066 ee->ee_cckOfdmPwrDelta - 2067 ee->ee_scaledCh14FilterCckDelta); 2068 else 2069 cckOfdmPwrDelta = SCALE_OC_DELTA( 2070 ee->ee_cckOfdmPwrDelta); 2071 ar5212CorrectGainDelta(ah, cckOfdmPwrDelta); 2072 } 2073 /* 2074 * Finally, write the power values into the 2075 * baseband power table 2076 */ 2077 for (i = 0; i < (PWR_TABLE_SIZE/2); i++) { 2078 OS_REG_WRITE(ah, AR_PHY_PCDAC_TX_POWER(i), 2079 ((((ahp->ah_pcdacTable[2*i + 1] << 8) | 0xff) & 0xffff) << 16) 2080 | (((ahp->ah_pcdacTable[2*i] << 8) | 0xff) & 0xffff) 2081 ); 2082 } 2083 } 2084 2085 /* Write the OFDM power per rate set */ 2086 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, 2087 POW_OFDM(ahp->ah_ratesArray[3], 24) 2088 | POW_OFDM(ahp->ah_ratesArray[2], 16) 2089 | POW_OFDM(ahp->ah_ratesArray[1], 8) 2090 | POW_OFDM(ahp->ah_ratesArray[0], 0) 2091 ); 2092 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, 2093 POW_OFDM(ahp->ah_ratesArray[7], 24) 2094 | POW_OFDM(ahp->ah_ratesArray[6], 16) 2095 | POW_OFDM(ahp->ah_ratesArray[5], 8) 2096 | POW_OFDM(ahp->ah_ratesArray[4], 0) 2097 ); 2098 2099 /* Write the CCK power per rate set */ 2100 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, 2101 POW_CCK(ahp->ah_ratesArray[10], 24) 2102 | POW_CCK(ahp->ah_ratesArray[9], 16) 2103 | POW_CCK(ahp->ah_ratesArray[15], 8) /* XR target power */ 2104 | POW_CCK(ahp->ah_ratesArray[8], 0) 2105 ); 2106 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, 2107 POW_CCK(ahp->ah_ratesArray[14], 24) 2108 | POW_CCK(ahp->ah_ratesArray[13], 16) 2109 | POW_CCK(ahp->ah_ratesArray[12], 8) 2110 | POW_CCK(ahp->ah_ratesArray[11], 0) 2111 ); 2112 2113 /* 2114 * Set max power to 30 dBm and, optionally, 2115 * enable TPC in tx descriptors. 2116 */ 2117 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE_MAX, MAX_RATE_POWER | 2118 (ahp->ah_tpcEnabled ? AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE : 0)); 2119 2120 return AH_TRUE; 2121 #undef N 2122 #undef POW_CCK 2123 #undef POW_OFDM 2124 } 2125 2126 /* 2127 * Sets the transmit power in the baseband for the given 2128 * operating channel and mode. 2129 */ 2130 static HAL_BOOL 2131 ar5212SetRateTable(struct ath_hal *ah, const struct ieee80211_channel *chan, 2132 int16_t tpcScaleReduction, int16_t powerLimit, HAL_BOOL commit, 2133 int16_t *pMinPower, int16_t *pMaxPower) 2134 { 2135 struct ath_hal_5212 *ahp = AH5212(ah); 2136 uint16_t freq = ath_hal_gethwchannel(ah, chan); 2137 const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 2138 uint16_t *rpow = ahp->ah_ratesArray; 2139 uint16_t twiceMaxEdgePower = MAX_RATE_POWER; 2140 uint16_t twiceMaxEdgePowerCck = MAX_RATE_POWER; 2141 uint16_t twiceMaxRDPower = MAX_RATE_POWER; 2142 int i; 2143 uint8_t cfgCtl; 2144 int8_t twiceAntennaGain, twiceAntennaReduction; 2145 const RD_EDGES_POWER *rep; 2146 TRGT_POWER_INFO targetPowerOfdm, targetPowerCck; 2147 int16_t scaledPower, maxAvailPower = 0; 2148 int16_t r13, r9, r7, r0; 2149 2150 HALASSERT(ah->ah_magic == AR5212_MAGIC); 2151 2152 twiceMaxRDPower = chan->ic_maxregpower * 2; 2153 *pMaxPower = -MAX_RATE_POWER; 2154 *pMinPower = MAX_RATE_POWER; 2155 2156 /* Get conformance test limit maximum for this channel */ 2157 cfgCtl = ath_hal_getctl(ah, chan); 2158 for (i = 0; i < ee->ee_numCtls; i++) { 2159 uint16_t twiceMinEdgePower; 2160 2161 if (ee->ee_ctl[i] == 0) 2162 continue; 2163 if (ee->ee_ctl[i] == cfgCtl || 2164 cfgCtl == ((ee->ee_ctl[i] & CTL_MODE_M) | SD_NO_CTL)) { 2165 rep = &ee->ee_rdEdgesPower[i * NUM_EDGES]; 2166 twiceMinEdgePower = ar5212GetMaxEdgePower(freq, rep); 2167 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { 2168 /* Find the minimum of all CTL edge powers that apply to this channel */ 2169 twiceMaxEdgePower = AH_MIN(twiceMaxEdgePower, twiceMinEdgePower); 2170 } else { 2171 twiceMaxEdgePower = twiceMinEdgePower; 2172 break; 2173 } 2174 } 2175 } 2176 2177 if (IEEE80211_IS_CHAN_G(chan)) { 2178 /* Check for a CCK CTL for 11G CCK powers */ 2179 cfgCtl = (cfgCtl & ~CTL_MODE_M) | CTL_11B; 2180 for (i = 0; i < ee->ee_numCtls; i++) { 2181 uint16_t twiceMinEdgePowerCck; 2182 2183 if (ee->ee_ctl[i] == 0) 2184 continue; 2185 if (ee->ee_ctl[i] == cfgCtl || 2186 cfgCtl == ((ee->ee_ctl[i] & CTL_MODE_M) | SD_NO_CTL)) { 2187 rep = &ee->ee_rdEdgesPower[i * NUM_EDGES]; 2188 twiceMinEdgePowerCck = ar5212GetMaxEdgePower(freq, rep); 2189 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { 2190 /* Find the minimum of all CTL edge powers that apply to this channel */ 2191 twiceMaxEdgePowerCck = AH_MIN(twiceMaxEdgePowerCck, twiceMinEdgePowerCck); 2192 } else { 2193 twiceMaxEdgePowerCck = twiceMinEdgePowerCck; 2194 break; 2195 } 2196 } 2197 } 2198 } else { 2199 /* Set the 11B cck edge power to the one found before */ 2200 twiceMaxEdgePowerCck = twiceMaxEdgePower; 2201 } 2202 2203 /* Get Antenna Gain reduction */ 2204 if (IEEE80211_IS_CHAN_5GHZ(chan)) { 2205 ath_hal_eepromGet(ah, AR_EEP_ANTGAINMAX_5, &twiceAntennaGain); 2206 } else { 2207 ath_hal_eepromGet(ah, AR_EEP_ANTGAINMAX_2, &twiceAntennaGain); 2208 } 2209 twiceAntennaReduction = 2210 ath_hal_getantennareduction(ah, chan, twiceAntennaGain); 2211 2212 if (IEEE80211_IS_CHAN_OFDM(chan)) { 2213 /* Get final OFDM target powers */ 2214 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 2215 ar5212GetTargetPowers(ah, chan, ee->ee_trgtPwr_11g, 2216 ee->ee_numTargetPwr_11g, &targetPowerOfdm); 2217 } else { 2218 ar5212GetTargetPowers(ah, chan, ee->ee_trgtPwr_11a, 2219 ee->ee_numTargetPwr_11a, &targetPowerOfdm); 2220 } 2221 2222 /* Get Maximum OFDM power */ 2223 /* Minimum of target and edge powers */ 2224 scaledPower = AH_MIN(twiceMaxEdgePower, 2225 twiceMaxRDPower - twiceAntennaReduction); 2226 2227 /* 2228 * If turbo is set, reduce power to keep power 2229 * consumption under 2 Watts. Note that we always do 2230 * this unless specially configured. Then we limit 2231 * power only for non-AP operation. 2232 */ 2233 if (IEEE80211_IS_CHAN_TURBO(chan) 2234 #ifdef AH_ENABLE_AP_SUPPORT 2235 && AH_PRIVATE(ah)->ah_opmode != HAL_M_HOSTAP 2236 #endif 2237 ) { 2238 /* 2239 * If turbo is set, reduce power to keep power 2240 * consumption under 2 Watts 2241 */ 2242 if (ee->ee_version >= AR_EEPROM_VER3_1) 2243 scaledPower = AH_MIN(scaledPower, 2244 ee->ee_turbo2WMaxPower5); 2245 /* 2246 * EEPROM version 4.0 added an additional 2247 * constraint on 2.4GHz channels. 2248 */ 2249 if (ee->ee_version >= AR_EEPROM_VER4_0 && 2250 IEEE80211_IS_CHAN_2GHZ(chan)) 2251 scaledPower = AH_MIN(scaledPower, 2252 ee->ee_turbo2WMaxPower2); 2253 } 2254 2255 maxAvailPower = AH_MIN(scaledPower, 2256 targetPowerOfdm.twicePwr6_24); 2257 2258 /* Reduce power by max regulatory domain allowed restrictions */ 2259 scaledPower = maxAvailPower - (tpcScaleReduction * 2); 2260 scaledPower = (scaledPower < 0) ? 0 : scaledPower; 2261 scaledPower = AH_MIN(scaledPower, powerLimit); 2262 2263 if (commit) { 2264 /* Set OFDM rates 9, 12, 18, 24 */ 2265 r0 = rpow[0] = rpow[1] = rpow[2] = rpow[3] = rpow[4] = scaledPower; 2266 2267 /* Set OFDM rates 36, 48, 54, XR */ 2268 rpow[5] = AH_MIN(rpow[0], targetPowerOfdm.twicePwr36); 2269 rpow[6] = AH_MIN(rpow[0], targetPowerOfdm.twicePwr48); 2270 r7 = rpow[7] = AH_MIN(rpow[0], targetPowerOfdm.twicePwr54); 2271 2272 if (ee->ee_version >= AR_EEPROM_VER4_0) { 2273 /* Setup XR target power from EEPROM */ 2274 rpow[15] = AH_MIN(scaledPower, IEEE80211_IS_CHAN_2GHZ(chan) ? 2275 ee->ee_xrTargetPower2 : ee->ee_xrTargetPower5); 2276 } else { 2277 /* XR uses 6mb power */ 2278 rpow[15] = rpow[0]; 2279 } 2280 ahp->ah_ofdmTxPower = *pMaxPower; 2281 2282 } else { 2283 r0 = scaledPower; 2284 r7 = AH_MIN(r0, targetPowerOfdm.twicePwr54); 2285 } 2286 *pMinPower = r7; 2287 *pMaxPower = r0; 2288 2289 HALDEBUG(ah, HAL_DEBUG_RFPARAM, 2290 "%s: MaxRD: %d TurboMax: %d MaxCTL: %d " 2291 "TPC_Reduction %d chan=%d (0x%x) maxAvailPower=%d pwr6_24=%d, maxPower=%d\n", 2292 __func__, twiceMaxRDPower, ee->ee_turbo2WMaxPower5, 2293 twiceMaxEdgePower, tpcScaleReduction * 2, 2294 chan->ic_freq, chan->ic_flags, 2295 maxAvailPower, targetPowerOfdm.twicePwr6_24, *pMaxPower); 2296 } 2297 2298 if (IEEE80211_IS_CHAN_CCK(chan)) { 2299 /* Get final CCK target powers */ 2300 ar5212GetTargetPowers(ah, chan, ee->ee_trgtPwr_11b, 2301 ee->ee_numTargetPwr_11b, &targetPowerCck); 2302 2303 /* Reduce power by max regulatory domain allowed restrictions */ 2304 scaledPower = AH_MIN(twiceMaxEdgePowerCck, 2305 twiceMaxRDPower - twiceAntennaReduction); 2306 if (maxAvailPower < AH_MIN(scaledPower, targetPowerCck.twicePwr6_24)) 2307 maxAvailPower = AH_MIN(scaledPower, targetPowerCck.twicePwr6_24); 2308 2309 /* Reduce power by user selection */ 2310 scaledPower = AH_MIN(scaledPower, targetPowerCck.twicePwr6_24) - (tpcScaleReduction * 2); 2311 scaledPower = (scaledPower < 0) ? 0 : scaledPower; 2312 scaledPower = AH_MIN(scaledPower, powerLimit); 2313 2314 if (commit) { 2315 /* Set CCK rates 2L, 2S, 5.5L, 5.5S, 11L, 11S */ 2316 rpow[8] = AH_MIN(scaledPower, targetPowerCck.twicePwr6_24); 2317 r9 = rpow[9] = AH_MIN(scaledPower, targetPowerCck.twicePwr36); 2318 rpow[10] = rpow[9]; 2319 rpow[11] = AH_MIN(scaledPower, targetPowerCck.twicePwr48); 2320 rpow[12] = rpow[11]; 2321 r13 = rpow[13] = AH_MIN(scaledPower, targetPowerCck.twicePwr54); 2322 rpow[14] = rpow[13]; 2323 } else { 2324 r9 = AH_MIN(scaledPower, targetPowerCck.twicePwr36); 2325 r13 = AH_MIN(scaledPower, targetPowerCck.twicePwr54); 2326 } 2327 2328 /* Set min/max power based off OFDM values or initialization */ 2329 if (r13 < *pMinPower) 2330 *pMinPower = r13; 2331 if (r9 > *pMaxPower) 2332 *pMaxPower = r9; 2333 2334 HALDEBUG(ah, HAL_DEBUG_RFPARAM, 2335 "%s: cck: MaxRD: %d MaxCTL: %d " 2336 "TPC_Reduction %d chan=%d (0x%x) maxAvailPower=%d pwr6_24=%d, maxPower=%d\n", 2337 __func__, twiceMaxRDPower, twiceMaxEdgePowerCck, 2338 tpcScaleReduction * 2, chan->ic_freq, chan->ic_flags, 2339 maxAvailPower, targetPowerCck.twicePwr6_24, *pMaxPower); 2340 } 2341 if (commit) { 2342 ahp->ah_tx6PowerInHalfDbm = *pMaxPower; 2343 AH_PRIVATE(ah)->ah_maxPowerLevel = ahp->ah_tx6PowerInHalfDbm; 2344 } 2345 return AH_TRUE; 2346 } 2347 2348 HAL_BOOL 2349 ar5212GetChipPowerLimits(struct ath_hal *ah, struct ieee80211_channel *chan) 2350 { 2351 struct ath_hal_5212 *ahp = AH5212(ah); 2352 #if 0 2353 static const uint16_t tpcScaleReductionTable[5] = 2354 { 0, 3, 6, 9, MAX_RATE_POWER }; 2355 int16_t tpcInDb, powerLimit; 2356 #endif 2357 int16_t minPower, maxPower; 2358 2359 /* 2360 * Get Pier table max and min powers. 2361 */ 2362 if (ahp->ah_rfHal->getChannelMaxMinPower(ah, chan, &maxPower, &minPower)) { 2363 /* NB: rf code returns 1/4 dBm units, convert */ 2364 chan->ic_maxpower = maxPower / 2; 2365 chan->ic_minpower = minPower / 2; 2366 } else { 2367 HALDEBUG(ah, HAL_DEBUG_ANY, 2368 "%s: no min/max power for %u/0x%x\n", 2369 __func__, chan->ic_freq, chan->ic_flags); 2370 chan->ic_maxpower = MAX_RATE_POWER; 2371 chan->ic_minpower = 0; 2372 } 2373 #if 0 2374 /* 2375 * Now adjust to reflect any global scale and/or CTL's. 2376 * (XXX is that correct?) 2377 */ 2378 powerLimit = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit); 2379 if (powerLimit >= MAX_RATE_POWER || powerLimit == 0) 2380 tpcInDb = tpcScaleReductionTable[AH_PRIVATE(ah)->ah_tpScale]; 2381 else 2382 tpcInDb = 0; 2383 if (!ar5212SetRateTable(ah, chan, tpcInDb, powerLimit, 2384 AH_FALSE, &minPower, &maxPower)) { 2385 HALDEBUG(ah, HAL_DEBUG_ANY, 2386 "%s: unable to find max/min power\n",__func__); 2387 return AH_FALSE; 2388 } 2389 if (maxPower < chan->ic_maxpower) 2390 chan->ic_maxpower = maxPower; 2391 if (minPower < chan->ic_minpower) 2392 chan->ic_minpower = minPower; 2393 HALDEBUG(ah, HAL_DEBUG_RESET, 2394 "Chan %d: MaxPow = %d MinPow = %d\n", 2395 chan->ic_freq, chan->ic_maxpower, chans->ic_minpower); 2396 #endif 2397 return AH_TRUE; 2398 } 2399 2400 /* 2401 * Correct for the gain-delta between ofdm and cck mode target 2402 * powers. Write the results to the rate table and the power table. 2403 * 2404 * Conventions : 2405 * 1. rpow[ii] is the integer value of 2*(desired power 2406 * for the rate ii in dBm) to provide 0.5dB resolution. rate 2407 * mapping is as following : 2408 * [0..7] --> ofdm 6, 9, .. 48, 54 2409 * [8..14] --> cck 1L, 2L, 2S, .. 11L, 11S 2410 * [15] --> XR (all rates get the same power) 2411 * 2. powv[ii] is the pcdac corresponding to ii/2 dBm. 2412 */ 2413 static void 2414 ar5212CorrectGainDelta(struct ath_hal *ah, int twiceOfdmCckDelta) 2415 { 2416 #define N(_a) (sizeof(_a) / sizeof(_a[0])) 2417 struct ath_hal_5212 *ahp = AH5212(ah); 2418 const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 2419 int16_t ratesIndex[N(ahp->ah_ratesArray)]; 2420 uint16_t ii, jj, iter; 2421 int32_t cckIndex; 2422 int16_t gainDeltaAdjust; 2423 2424 HALASSERT(ah->ah_magic == AR5212_MAGIC); 2425 2426 gainDeltaAdjust = ee->ee_cckOfdmGainDelta; 2427 2428 /* make a local copy of desired powers as initial indices */ 2429 OS_MEMCPY(ratesIndex, ahp->ah_ratesArray, sizeof(ratesIndex)); 2430 2431 /* fix only the CCK indices */ 2432 for (ii = 8; ii < 15; ii++) { 2433 /* apply a gain_delta correction of -15 for CCK */ 2434 ratesIndex[ii] -= gainDeltaAdjust; 2435 2436 /* Now check for contention with all ofdm target powers */ 2437 jj = 0; 2438 iter = 0; 2439 /* indicates not all ofdm rates checked forcontention yet */ 2440 while (jj < 16) { 2441 if (ratesIndex[ii] < 0) 2442 ratesIndex[ii] = 0; 2443 if (jj == 8) { /* skip CCK rates */ 2444 jj = 15; 2445 continue; 2446 } 2447 if (ratesIndex[ii] == ahp->ah_ratesArray[jj]) { 2448 if (ahp->ah_ratesArray[jj] == 0) 2449 ratesIndex[ii]++; 2450 else if (iter > 50) { 2451 /* 2452 * To avoid pathological case of of 2453 * dm target powers 0 and 0.5dBm 2454 */ 2455 ratesIndex[ii]++; 2456 } else 2457 ratesIndex[ii]--; 2458 /* check with all rates again */ 2459 jj = 0; 2460 iter++; 2461 } else 2462 jj++; 2463 } 2464 if (ratesIndex[ii] >= PWR_TABLE_SIZE) 2465 ratesIndex[ii] = PWR_TABLE_SIZE -1; 2466 cckIndex = ahp->ah_ratesArray[ii] - twiceOfdmCckDelta; 2467 if (cckIndex < 0) 2468 cckIndex = 0; 2469 2470 /* 2471 * Validate that the indexes for the powv are not 2472 * out of bounds. 2473 */ 2474 HALASSERT(cckIndex < PWR_TABLE_SIZE); 2475 HALASSERT(ratesIndex[ii] < PWR_TABLE_SIZE); 2476 ahp->ah_pcdacTable[ratesIndex[ii]] = 2477 ahp->ah_pcdacTable[cckIndex]; 2478 } 2479 /* Override rate per power table with new values */ 2480 for (ii = 8; ii < 15; ii++) 2481 ahp->ah_ratesArray[ii] = ratesIndex[ii]; 2482 #undef N 2483 } 2484 2485 /* 2486 * Find the maximum conformance test limit for the given channel and CTL info 2487 */ 2488 static uint16_t 2489 ar5212GetMaxEdgePower(uint16_t channel, const RD_EDGES_POWER *pRdEdgesPower) 2490 { 2491 /* temp array for holding edge channels */ 2492 uint16_t tempChannelList[NUM_EDGES]; 2493 uint16_t clo, chi, twiceMaxEdgePower; 2494 int i, numEdges; 2495 2496 /* Get the edge power */ 2497 for (i = 0; i < NUM_EDGES; i++) { 2498 if (pRdEdgesPower[i].rdEdge == 0) 2499 break; 2500 tempChannelList[i] = pRdEdgesPower[i].rdEdge; 2501 } 2502 numEdges = i; 2503 2504 ar5212GetLowerUpperValues(channel, tempChannelList, 2505 numEdges, &clo, &chi); 2506 /* Get the index for the lower channel */ 2507 for (i = 0; i < numEdges && clo != tempChannelList[i]; i++) 2508 ; 2509 /* Is lower channel ever outside the rdEdge? */ 2510 HALASSERT(i != numEdges); 2511 2512 if ((clo == chi && clo == channel) || (pRdEdgesPower[i].flag)) { 2513 /* 2514 * If there's an exact channel match or an inband flag set 2515 * on the lower channel use the given rdEdgePower 2516 */ 2517 twiceMaxEdgePower = pRdEdgesPower[i].twice_rdEdgePower; 2518 HALASSERT(twiceMaxEdgePower > 0); 2519 } else 2520 twiceMaxEdgePower = MAX_RATE_POWER; 2521 return twiceMaxEdgePower; 2522 } 2523 2524 /* 2525 * Returns interpolated or the scaled up interpolated value 2526 */ 2527 static uint16_t 2528 interpolate(uint16_t target, uint16_t srcLeft, uint16_t srcRight, 2529 uint16_t targetLeft, uint16_t targetRight) 2530 { 2531 uint16_t rv; 2532 int16_t lRatio; 2533 2534 /* to get an accurate ratio, always scale, if want to scale, then don't scale back down */ 2535 if ((targetLeft * targetRight) == 0) 2536 return 0; 2537 2538 if (srcRight != srcLeft) { 2539 /* 2540 * Note the ratio always need to be scaled, 2541 * since it will be a fraction. 2542 */ 2543 lRatio = (target - srcLeft) * EEP_SCALE / (srcRight - srcLeft); 2544 if (lRatio < 0) { 2545 /* Return as Left target if value would be negative */ 2546 rv = targetLeft; 2547 } else if (lRatio > EEP_SCALE) { 2548 /* Return as Right target if Ratio is greater than 100% (SCALE) */ 2549 rv = targetRight; 2550 } else { 2551 rv = (lRatio * targetRight + (EEP_SCALE - lRatio) * 2552 targetLeft) / EEP_SCALE; 2553 } 2554 } else { 2555 rv = targetLeft; 2556 } 2557 return rv; 2558 } 2559 2560 /* 2561 * Return the four rates of target power for the given target power table 2562 * channel, and number of channels 2563 */ 2564 static void 2565 ar5212GetTargetPowers(struct ath_hal *ah, const struct ieee80211_channel *chan, 2566 const TRGT_POWER_INFO *powInfo, 2567 uint16_t numChannels, TRGT_POWER_INFO *pNewPower) 2568 { 2569 uint16_t freq = ath_hal_gethwchannel(ah, chan); 2570 /* temp array for holding target power channels */ 2571 uint16_t tempChannelList[NUM_TEST_FREQUENCIES]; 2572 uint16_t clo, chi, ixlo, ixhi; 2573 int i; 2574 2575 /* Copy the target powers into the temp channel list */ 2576 for (i = 0; i < numChannels; i++) 2577 tempChannelList[i] = powInfo[i].testChannel; 2578 2579 ar5212GetLowerUpperValues(freq, tempChannelList, 2580 numChannels, &clo, &chi); 2581 2582 /* Get the indices for the channel */ 2583 ixlo = ixhi = 0; 2584 for (i = 0; i < numChannels; i++) { 2585 if (clo == tempChannelList[i]) { 2586 ixlo = i; 2587 } 2588 if (chi == tempChannelList[i]) { 2589 ixhi = i; 2590 break; 2591 } 2592 } 2593 2594 /* 2595 * Get the lower and upper channels, target powers, 2596 * and interpolate between them. 2597 */ 2598 pNewPower->twicePwr6_24 = interpolate(freq, clo, chi, 2599 powInfo[ixlo].twicePwr6_24, powInfo[ixhi].twicePwr6_24); 2600 pNewPower->twicePwr36 = interpolate(freq, clo, chi, 2601 powInfo[ixlo].twicePwr36, powInfo[ixhi].twicePwr36); 2602 pNewPower->twicePwr48 = interpolate(freq, clo, chi, 2603 powInfo[ixlo].twicePwr48, powInfo[ixhi].twicePwr48); 2604 pNewPower->twicePwr54 = interpolate(freq, clo, chi, 2605 powInfo[ixlo].twicePwr54, powInfo[ixhi].twicePwr54); 2606 } 2607 2608 static uint32_t 2609 udiff(uint32_t u, uint32_t v) 2610 { 2611 return (u >= v ? u - v : v - u); 2612 } 2613 2614 /* 2615 * Search a list for a specified value v that is within 2616 * EEP_DELTA of the search values. Return the closest 2617 * values in the list above and below the desired value. 2618 * EEP_DELTA is a factional value; everything is scaled 2619 * so only integer arithmetic is used. 2620 * 2621 * NB: the input list is assumed to be sorted in ascending order 2622 */ 2623 void 2624 ar5212GetLowerUpperValues(uint16_t v, uint16_t *lp, uint16_t listSize, 2625 uint16_t *vlo, uint16_t *vhi) 2626 { 2627 uint32_t target = v * EEP_SCALE; 2628 uint16_t *ep = lp+listSize; 2629 2630 /* 2631 * Check first and last elements for out-of-bounds conditions. 2632 */ 2633 if (target < (uint32_t)(lp[0] * EEP_SCALE - EEP_DELTA)) { 2634 *vlo = *vhi = lp[0]; 2635 return; 2636 } 2637 if (target > (uint32_t)(ep[-1] * EEP_SCALE + EEP_DELTA)) { 2638 *vlo = *vhi = ep[-1]; 2639 return; 2640 } 2641 2642 /* look for value being near or between 2 values in list */ 2643 for (; lp < ep; lp++) { 2644 /* 2645 * If value is close to the current value of the list 2646 * then target is not between values, it is one of the values 2647 */ 2648 if (udiff(lp[0] * EEP_SCALE, target) < EEP_DELTA) { 2649 *vlo = *vhi = lp[0]; 2650 return; 2651 } 2652 /* 2653 * Look for value being between current value and next value 2654 * if so return these 2 values 2655 */ 2656 if (target < (uint32_t)(lp[1] * EEP_SCALE - EEP_DELTA)) { 2657 *vlo = lp[0]; 2658 *vhi = lp[1]; 2659 return; 2660 } 2661 } 2662 HALASSERT(AH_FALSE); /* should not reach here */ 2663 } 2664 2665 /* 2666 * Perform analog "swizzling" of parameters into their location 2667 * 2668 * NB: used by RF backends 2669 */ 2670 void 2671 ar5212ModifyRfBuffer(uint32_t *rfBuf, uint32_t reg32, uint32_t numBits, 2672 uint32_t firstBit, uint32_t column) 2673 { 2674 #define MAX_ANALOG_START 319 /* XXX */ 2675 uint32_t tmp32, mask, arrayEntry, lastBit; 2676 int32_t bitPosition, bitsLeft; 2677 2678 HALASSERT(column <= 3); 2679 HALASSERT(numBits <= 32); 2680 HALASSERT(firstBit + numBits <= MAX_ANALOG_START); 2681 2682 tmp32 = ath_hal_reverseBits(reg32, numBits); 2683 arrayEntry = (firstBit - 1) / 8; 2684 bitPosition = (firstBit - 1) % 8; 2685 bitsLeft = numBits; 2686 while (bitsLeft > 0) { 2687 lastBit = (bitPosition + bitsLeft > 8) ? 2688 8 : bitPosition + bitsLeft; 2689 mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) << 2690 (column * 8); 2691 rfBuf[arrayEntry] &= ~mask; 2692 rfBuf[arrayEntry] |= ((tmp32 << bitPosition) << 2693 (column * 8)) & mask; 2694 bitsLeft -= 8 - bitPosition; 2695 tmp32 = tmp32 >> (8 - bitPosition); 2696 bitPosition = 0; 2697 arrayEntry++; 2698 } 2699 #undef MAX_ANALOG_START 2700 } 2701 2702 /* 2703 * Sets the rate to duration values in MAC - used for multi- 2704 * rate retry. 2705 * The rate duration table needs to cover all valid rate codes; 2706 * the 11g table covers all ofdm rates, while the 11b table 2707 * covers all cck rates => all valid rates get covered between 2708 * these two mode's ratetables! 2709 * But if we're turbo, the ofdm phy is replaced by the turbo phy 2710 * and cck is not valid with turbo => all rates get covered 2711 * by the turbo ratetable only 2712 */ 2713 void 2714 ar5212SetRateDurationTable(struct ath_hal *ah, 2715 const struct ieee80211_channel *chan) 2716 { 2717 const HAL_RATE_TABLE *rt; 2718 int i; 2719 2720 /* NB: band doesn't matter for 1/2 and 1/4 rate */ 2721 if (IEEE80211_IS_CHAN_HALF(chan)) { 2722 rt = ar5212GetRateTable(ah, HAL_MODE_11A_HALF_RATE); 2723 } else if (IEEE80211_IS_CHAN_QUARTER(chan)) { 2724 rt = ar5212GetRateTable(ah, HAL_MODE_11A_QUARTER_RATE); 2725 } else { 2726 rt = ar5212GetRateTable(ah, 2727 IEEE80211_IS_CHAN_TURBO(chan) ? HAL_MODE_TURBO : HAL_MODE_11G); 2728 } 2729 2730 for (i = 0; i < rt->rateCount; ++i) 2731 OS_REG_WRITE(ah, 2732 AR_RATE_DURATION(rt->info[i].rateCode), 2733 ath_hal_computetxtime(ah, rt, 2734 WLAN_CTRL_FRAME_SIZE, 2735 rt->info[i].controlRate, AH_FALSE)); 2736 if (!IEEE80211_IS_CHAN_TURBO(chan)) { 2737 /* 11g Table is used to cover the CCK rates. */ 2738 rt = ar5212GetRateTable(ah, HAL_MODE_11G); 2739 for (i = 0; i < rt->rateCount; ++i) { 2740 uint32_t reg = AR_RATE_DURATION(rt->info[i].rateCode); 2741 2742 if (rt->info[i].phy != IEEE80211_T_CCK) 2743 continue; 2744 2745 OS_REG_WRITE(ah, reg, 2746 ath_hal_computetxtime(ah, rt, 2747 WLAN_CTRL_FRAME_SIZE, 2748 rt->info[i].controlRate, AH_FALSE)); 2749 /* cck rates have short preamble option also */ 2750 if (rt->info[i].shortPreamble) { 2751 reg += rt->info[i].shortPreamble << 2; 2752 OS_REG_WRITE(ah, reg, 2753 ath_hal_computetxtime(ah, rt, 2754 WLAN_CTRL_FRAME_SIZE, 2755 rt->info[i].controlRate, 2756 AH_TRUE)); 2757 } 2758 } 2759 } 2760 } 2761 2762 /* Adjust various register settings based on half/quarter rate clock setting. 2763 * This includes: +USEC, TX/RX latency, 2764 * + IFS params: slot, eifs, misc etc. 2765 */ 2766 void 2767 ar5212SetIFSTiming(struct ath_hal *ah, const struct ieee80211_channel *chan) 2768 { 2769 uint32_t txLat, rxLat, usec, slot, refClock, eifs, init_usec; 2770 2771 HALASSERT(IEEE80211_IS_CHAN_HALF(chan) || 2772 IEEE80211_IS_CHAN_QUARTER(chan)); 2773 2774 refClock = OS_REG_READ(ah, AR_USEC) & AR_USEC_USEC32; 2775 if (IEEE80211_IS_CHAN_HALF(chan)) { 2776 slot = IFS_SLOT_HALF_RATE; 2777 rxLat = RX_NON_FULL_RATE_LATENCY << AR5212_USEC_RX_LAT_S; 2778 txLat = TX_HALF_RATE_LATENCY << AR5212_USEC_TX_LAT_S; 2779 usec = HALF_RATE_USEC; 2780 eifs = IFS_EIFS_HALF_RATE; 2781 init_usec = INIT_USEC >> 1; 2782 } else { /* quarter rate */ 2783 slot = IFS_SLOT_QUARTER_RATE; 2784 rxLat = RX_NON_FULL_RATE_LATENCY << AR5212_USEC_RX_LAT_S; 2785 txLat = TX_QUARTER_RATE_LATENCY << AR5212_USEC_TX_LAT_S; 2786 usec = QUARTER_RATE_USEC; 2787 eifs = IFS_EIFS_QUARTER_RATE; 2788 init_usec = INIT_USEC >> 2; 2789 } 2790 2791 OS_REG_WRITE(ah, AR_USEC, (usec | refClock | txLat | rxLat)); 2792 OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, slot); 2793 OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, eifs); 2794 OS_REG_RMW_FIELD(ah, AR_D_GBL_IFS_MISC, 2795 AR_D_GBL_IFS_MISC_USEC_DURATION, init_usec); 2796 } 2797