1 /* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19 #include "opt_ah.h" 20 21 #include "ah.h" 22 #include "ah_internal.h" 23 24 #include "ar5212/ar5212.h" 25 #include "ar5212/ar5212reg.h" 26 #include "ar5212/ar5212desc.h" 27 28 /* 29 * Get the RXDP. 30 */ 31 uint32_t 32 ar5212GetRxDP(struct ath_hal *ath, HAL_RX_QUEUE qtype) 33 { 34 35 HALASSERT(qtype == HAL_RX_QUEUE_HP); 36 return OS_REG_READ(ath, AR_RXDP); 37 } 38 39 /* 40 * Set the RxDP. 41 */ 42 void 43 ar5212SetRxDP(struct ath_hal *ah, uint32_t rxdp, HAL_RX_QUEUE qtype) 44 { 45 46 HALASSERT(qtype == HAL_RX_QUEUE_HP); 47 OS_REG_WRITE(ah, AR_RXDP, rxdp); 48 HALASSERT(OS_REG_READ(ah, AR_RXDP) == rxdp); 49 } 50 51 /* 52 * Set Receive Enable bits. 53 */ 54 void 55 ar5212EnableReceive(struct ath_hal *ah) 56 { 57 OS_REG_WRITE(ah, AR_CR, AR_CR_RXE); 58 } 59 60 /* 61 * Stop Receive at the DMA engine 62 */ 63 HAL_BOOL 64 ar5212StopDmaReceive(struct ath_hal *ah) 65 { 66 OS_MARK(ah, AH_MARK_RX_CTL, AH_MARK_RX_CTL_DMA_STOP); 67 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */ 68 if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) { 69 OS_MARK(ah, AH_MARK_RX_CTL, AH_MARK_RX_CTL_DMA_STOP_ERR); 70 #ifdef AH_DEBUG 71 ath_hal_printf(ah, "%s: dma failed to stop in 10ms\n" 72 "AR_CR=0x%08x\nAR_DIAG_SW=0x%08x\n", 73 __func__, 74 OS_REG_READ(ah, AR_CR), 75 OS_REG_READ(ah, AR_DIAG_SW)); 76 #endif 77 return AH_FALSE; 78 } else { 79 return AH_TRUE; 80 } 81 } 82 83 /* 84 * Start Transmit at the PCU engine (unpause receive) 85 */ 86 void 87 ar5212StartPcuReceive(struct ath_hal *ah) 88 { 89 struct ath_hal_private *ahp = AH_PRIVATE(ah); 90 91 OS_MARK(ah, AH_MARK_RX_CTL, AH_MARK_RX_CTL_PCU_START); 92 OS_REG_WRITE(ah, AR_DIAG_SW, 93 OS_REG_READ(ah, AR_DIAG_SW) &~ AR_DIAG_RX_DIS); 94 ar5212EnableMibCounters(ah); 95 /* NB: restore current settings */ 96 ar5212AniReset(ah, ahp->ah_curchan, ahp->ah_opmode, AH_TRUE); 97 } 98 99 /* 100 * Stop Transmit at the PCU engine (pause receive) 101 */ 102 void 103 ar5212StopPcuReceive(struct ath_hal *ah) 104 { 105 OS_MARK(ah, AH_MARK_RX_CTL, AH_MARK_RX_CTL_PCU_STOP); 106 OS_REG_WRITE(ah, AR_DIAG_SW, 107 OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_RX_DIS); 108 ar5212DisableMibCounters(ah); 109 } 110 111 /* 112 * Set multicast filter 0 (lower 32-bits) 113 * filter 1 (upper 32-bits) 114 */ 115 void 116 ar5212SetMulticastFilter(struct ath_hal *ah, uint32_t filter0, uint32_t filter1) 117 { 118 OS_REG_WRITE(ah, AR_MCAST_FIL0, filter0); 119 OS_REG_WRITE(ah, AR_MCAST_FIL1, filter1); 120 } 121 122 /* 123 * Clear multicast filter by index 124 */ 125 HAL_BOOL 126 ar5212ClrMulticastFilterIndex(struct ath_hal *ah, uint32_t ix) 127 { 128 uint32_t val; 129 130 if (ix >= 64) 131 return AH_FALSE; 132 if (ix >= 32) { 133 val = OS_REG_READ(ah, AR_MCAST_FIL1); 134 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val &~ (1<<(ix-32)))); 135 } else { 136 val = OS_REG_READ(ah, AR_MCAST_FIL0); 137 OS_REG_WRITE(ah, AR_MCAST_FIL0, (val &~ (1<<ix))); 138 } 139 return AH_TRUE; 140 } 141 142 /* 143 * Set multicast filter by index 144 */ 145 HAL_BOOL 146 ar5212SetMulticastFilterIndex(struct ath_hal *ah, uint32_t ix) 147 { 148 uint32_t val; 149 150 if (ix >= 64) 151 return AH_FALSE; 152 if (ix >= 32) { 153 val = OS_REG_READ(ah, AR_MCAST_FIL1); 154 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val | (1<<(ix-32)))); 155 } else { 156 val = OS_REG_READ(ah, AR_MCAST_FIL0); 157 OS_REG_WRITE(ah, AR_MCAST_FIL0, (val | (1<<ix))); 158 } 159 return AH_TRUE; 160 } 161 162 /* 163 * Get the receive filter. 164 */ 165 uint32_t 166 ar5212GetRxFilter(struct ath_hal *ah) 167 { 168 uint32_t bits = OS_REG_READ(ah, AR_RX_FILTER); 169 uint32_t phybits = OS_REG_READ(ah, AR_PHY_ERR); 170 if (phybits & AR_PHY_ERR_RADAR) 171 bits |= HAL_RX_FILTER_PHYRADAR; 172 if (phybits & (AR_PHY_ERR_OFDM_TIMING|AR_PHY_ERR_CCK_TIMING)) 173 bits |= HAL_RX_FILTER_PHYERR; 174 if (AH_PRIVATE(ah)->ah_caps.halBssidMatchSupport && 175 (AH5212(ah)->ah_miscMode & AR_MISC_MODE_BSSID_MATCH_FORCE)) 176 bits |= HAL_RX_FILTER_BSSID; 177 return bits; 178 } 179 180 /* 181 * Set the receive filter. 182 */ 183 void 184 ar5212SetRxFilter(struct ath_hal *ah, uint32_t bits) 185 { 186 struct ath_hal_5212 *ahp = AH5212(ah); 187 uint32_t phybits; 188 189 OS_REG_WRITE(ah, AR_RX_FILTER, 190 bits &~ (HAL_RX_FILTER_PHYRADAR|HAL_RX_FILTER_PHYERR| 191 HAL_RX_FILTER_BSSID)); 192 phybits = 0; 193 if (bits & HAL_RX_FILTER_PHYRADAR) 194 phybits |= AR_PHY_ERR_RADAR; 195 if (bits & HAL_RX_FILTER_PHYERR) 196 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; 197 OS_REG_WRITE(ah, AR_PHY_ERR, phybits); 198 if (phybits) { 199 OS_REG_WRITE(ah, AR_RXCFG, 200 OS_REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA); 201 } else { 202 OS_REG_WRITE(ah, AR_RXCFG, 203 OS_REG_READ(ah, AR_RXCFG) &~ AR_RXCFG_ZLFDMA); 204 } 205 if (AH_PRIVATE(ah)->ah_caps.halBssidMatchSupport) { 206 if (bits & HAL_RX_FILTER_BSSID) 207 ahp->ah_miscMode |= AR_MISC_MODE_BSSID_MATCH_FORCE; 208 else 209 ahp->ah_miscMode &= ~AR_MISC_MODE_BSSID_MATCH_FORCE; 210 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode); 211 } 212 } 213 214 /* 215 * Initialize RX descriptor, by clearing the status and setting 216 * the size (and any other flags). 217 */ 218 HAL_BOOL 219 ar5212SetupRxDesc(struct ath_hal *ah, struct ath_desc *ds, 220 uint32_t size, u_int flags) 221 { 222 struct ar5212_desc *ads = AR5212DESC(ds); 223 224 HALASSERT((size &~ AR_BufLen) == 0); 225 226 ads->ds_ctl0 = 0; 227 ads->ds_ctl1 = size & AR_BufLen; 228 229 if (flags & HAL_RXDESC_INTREQ) 230 ads->ds_ctl1 |= AR_RxInterReq; 231 ads->ds_rxstatus0 = ads->ds_rxstatus1 = 0; 232 233 return AH_TRUE; 234 } 235 236 /* 237 * Process an RX descriptor, and return the status to the caller. 238 * Copy some hardware specific items into the software portion 239 * of the descriptor. 240 * 241 * NB: the caller is responsible for validating the memory contents 242 * of the descriptor (e.g. flushing any cached copy). 243 */ 244 HAL_STATUS 245 ar5212ProcRxDesc(struct ath_hal *ah, struct ath_desc *ds, 246 uint32_t pa, struct ath_desc *nds, uint64_t tsf, 247 struct ath_rx_status *rs) 248 { 249 struct ar5212_desc *ads = AR5212DESC(ds); 250 struct ar5212_desc *ands = AR5212DESC(nds); 251 252 if ((ads->ds_rxstatus1 & AR_Done) == 0) 253 return HAL_EINPROGRESS; 254 /* 255 * Given the use of a self-linked tail be very sure that the hw is 256 * done with this descriptor; the hw may have done this descriptor 257 * once and picked it up again...make sure the hw has moved on. 258 */ 259 if ((ands->ds_rxstatus1&AR_Done) == 0 && OS_REG_READ(ah, AR_RXDP) == pa) 260 return HAL_EINPROGRESS; 261 262 rs->rs_datalen = ads->ds_rxstatus0 & AR_DataLen; 263 rs->rs_tstamp = MS(ads->ds_rxstatus1, AR_RcvTimestamp); 264 rs->rs_status = 0; 265 /* XXX what about KeyCacheMiss? */ 266 rs->rs_rssi = MS(ads->ds_rxstatus0, AR_RcvSigStrength); 267 /* discard invalid h/w rssi data */ 268 if (rs->rs_rssi == -128) 269 rs->rs_rssi = 0; 270 if (ads->ds_rxstatus1 & AR_KeyIdxValid) 271 rs->rs_keyix = MS(ads->ds_rxstatus1, AR_KeyIdx); 272 else 273 rs->rs_keyix = HAL_RXKEYIX_INVALID; 274 /* NB: caller expected to do rate table mapping */ 275 rs->rs_rate = MS(ads->ds_rxstatus0, AR_RcvRate); 276 rs->rs_antenna = MS(ads->ds_rxstatus0, AR_RcvAntenna); 277 rs->rs_more = (ads->ds_rxstatus0 & AR_More) ? 1 : 0; 278 279 /* 280 * The AR5413 (at least) sometimes sets both AR_CRCErr and 281 * AR_PHYErr when reporting radar pulses. In this instance 282 * set HAL_RXERR_PHY as well as HAL_RXERR_CRC and 283 * let the driver layer figure out what to do. 284 * 285 * See PR kern/169362. 286 */ 287 if ((ads->ds_rxstatus1 & AR_FrmRcvOK) == 0) { 288 /* 289 * These four bits should not be set together. The 290 * 5212 spec states a Michael error can only occur if 291 * DecryptCRCErr not set (and TKIP is used). Experience 292 * indicates however that you can also get Michael errors 293 * when a CRC error is detected, but these are specious. 294 * Consequently we filter them out here so we don't 295 * confuse and/or complicate drivers. 296 */ 297 if (ads->ds_rxstatus1 & AR_PHYErr) { 298 u_int phyerr; 299 300 rs->rs_status |= HAL_RXERR_PHY; 301 phyerr = MS(ads->ds_rxstatus1, AR_PHYErrCode); 302 rs->rs_phyerr = phyerr; 303 if (!AH5212(ah)->ah_hasHwPhyCounters && 304 phyerr != HAL_PHYERR_RADAR) 305 ar5212AniPhyErrReport(ah, rs); 306 } 307 308 if (ads->ds_rxstatus1 & AR_CRCErr) 309 rs->rs_status |= HAL_RXERR_CRC; 310 else if (ads->ds_rxstatus1 & AR_DecryptCRCErr) 311 rs->rs_status |= HAL_RXERR_DECRYPT; 312 else if (ads->ds_rxstatus1 & AR_MichaelErr) 313 rs->rs_status |= HAL_RXERR_MIC; 314 } 315 return HAL_OK; 316 } 317