1 /*- 2 * SPDX-License-Identifier: ISC 3 * 4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 5 * Copyright (c) 2002-2008 Atheros Communications, Inc. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 #include "opt_ah.h" 20 21 #include "ah.h" 22 #include "ah_internal.h" 23 24 #include "ar5212/ar5212.h" 25 #include "ar5212/ar5212reg.h" 26 #include "ar5212/ar5212phy.h" 27 28 /* 29 * Checks to see if an interrupt is pending on our NIC 30 * 31 * Returns: TRUE if an interrupt is pending 32 * FALSE if not 33 */ 34 HAL_BOOL 35 ar5212IsInterruptPending(struct ath_hal *ah) 36 { 37 /* 38 * Some platforms trigger our ISR before applying power to 39 * the card, so make sure the INTPEND is really 1, not 0xffffffff. 40 */ 41 return (OS_REG_READ(ah, AR_INTPEND) == AR_INTPEND_TRUE); 42 } 43 44 /* 45 * Reads the Interrupt Status Register value from the NIC, thus deasserting 46 * the interrupt line, and returns both the masked and unmasked mapped ISR 47 * values. The value returned is mapped to abstract the hw-specific bit 48 * locations in the Interrupt Status Register. 49 * 50 * Returns: A hardware-abstracted bitmap of all non-masked-out 51 * interrupts pending, as well as an unmasked value 52 */ 53 HAL_BOOL 54 ar5212GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked) 55 { 56 uint32_t isr, isr0, isr1; 57 uint32_t mask2; 58 struct ath_hal_5212 *ahp = AH5212(ah); 59 60 isr = OS_REG_READ(ah, AR_ISR); 61 mask2 = 0; 62 if (isr & AR_ISR_BCNMISC) { 63 uint32_t isr2 = OS_REG_READ(ah, AR_ISR_S2); 64 if (isr2 & AR_ISR_S2_TIM) 65 mask2 |= HAL_INT_TIM; 66 if (isr2 & AR_ISR_S2_DTIM) 67 mask2 |= HAL_INT_DTIM; 68 if (isr2 & AR_ISR_S2_DTIMSYNC) 69 mask2 |= HAL_INT_DTIMSYNC; 70 if (isr2 & AR_ISR_S2_CABEND) 71 mask2 |= HAL_INT_CABEND; 72 if (isr2 & AR_ISR_S2_TBTT) 73 mask2 |= HAL_INT_TBTT; 74 } 75 isr = OS_REG_READ(ah, AR_ISR_RAC); 76 if (isr == 0xffffffff) { 77 *masked = 0; 78 return AH_FALSE; 79 } 80 81 *masked = isr & HAL_INT_COMMON; 82 83 if (isr & AR_ISR_HIUERR) 84 *masked |= HAL_INT_FATAL; 85 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR)) 86 *masked |= HAL_INT_RX; 87 if (isr & (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | AR_ISR_TXEOL)) { 88 *masked |= HAL_INT_TX; 89 isr0 = OS_REG_READ(ah, AR_ISR_S0_S); 90 ahp->ah_intrTxqs |= MS(isr0, AR_ISR_S0_QCU_TXOK); 91 ahp->ah_intrTxqs |= MS(isr0, AR_ISR_S0_QCU_TXDESC); 92 isr1 = OS_REG_READ(ah, AR_ISR_S1_S); 93 ahp->ah_intrTxqs |= MS(isr1, AR_ISR_S1_QCU_TXERR); 94 ahp->ah_intrTxqs |= MS(isr1, AR_ISR_S1_QCU_TXEOL); 95 } 96 97 /* 98 * Receive overrun is usually non-fatal on Oahu/Spirit. 99 * BUT on some parts rx could fail and the chip must be reset. 100 * So we force a hardware reset in all cases. 101 */ 102 if ((isr & AR_ISR_RXORN) && AH_PRIVATE(ah)->ah_rxornIsFatal) { 103 HALDEBUG(ah, HAL_DEBUG_ANY, 104 "%s: receive FIFO overrun interrupt\n", __func__); 105 *masked |= HAL_INT_FATAL; 106 } 107 *masked |= mask2; 108 109 /* 110 * On fatal errors collect ISR state for debugging. 111 */ 112 if (*masked & HAL_INT_FATAL) { 113 AH_PRIVATE(ah)->ah_fatalState[0] = isr; 114 AH_PRIVATE(ah)->ah_fatalState[1] = OS_REG_READ(ah, AR_ISR_S0_S); 115 AH_PRIVATE(ah)->ah_fatalState[2] = OS_REG_READ(ah, AR_ISR_S1_S); 116 AH_PRIVATE(ah)->ah_fatalState[3] = OS_REG_READ(ah, AR_ISR_S2_S); 117 AH_PRIVATE(ah)->ah_fatalState[4] = OS_REG_READ(ah, AR_ISR_S3_S); 118 AH_PRIVATE(ah)->ah_fatalState[5] = OS_REG_READ(ah, AR_ISR_S4_S); 119 HALDEBUG(ah, HAL_DEBUG_ANY, 120 "%s: fatal error, ISR_RAC=0x%x ISR_S2_S=0x%x\n", 121 __func__, isr, AH_PRIVATE(ah)->ah_fatalState[3]); 122 } 123 return AH_TRUE; 124 } 125 126 HAL_INT 127 ar5212GetInterrupts(struct ath_hal *ah) 128 { 129 return AH5212(ah)->ah_maskReg; 130 } 131 132 /* 133 * Atomically enables NIC interrupts. Interrupts are passed in 134 * via the enumerated bitmask in ints. 135 */ 136 HAL_INT 137 ar5212SetInterrupts(struct ath_hal *ah, HAL_INT ints) 138 { 139 struct ath_hal_5212 *ahp = AH5212(ah); 140 uint32_t omask = ahp->ah_maskReg; 141 uint32_t mask, mask2; 142 143 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: 0x%x => 0x%x\n", 144 __func__, omask, ints); 145 146 if (omask & HAL_INT_GLOBAL) { 147 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: disable IER\n", __func__); 148 OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE); 149 (void) OS_REG_READ(ah, AR_IER); /* flush write to HW */ 150 } 151 152 mask = ints & HAL_INT_COMMON; 153 mask2 = 0; 154 if (ints & HAL_INT_TX) { 155 if (ahp->ah_txOkInterruptMask) 156 mask |= AR_IMR_TXOK; 157 if (ahp->ah_txErrInterruptMask) 158 mask |= AR_IMR_TXERR; 159 if (ahp->ah_txDescInterruptMask) 160 mask |= AR_IMR_TXDESC; 161 if (ahp->ah_txEolInterruptMask) 162 mask |= AR_IMR_TXEOL; 163 } 164 if (ints & HAL_INT_RX) 165 mask |= AR_IMR_RXOK | AR_IMR_RXERR | AR_IMR_RXDESC; 166 if (ints & (HAL_INT_BMISC)) { 167 mask |= AR_IMR_BCNMISC; 168 if (ints & HAL_INT_TIM) 169 mask2 |= AR_IMR_S2_TIM; 170 if (ints & HAL_INT_DTIM) 171 mask2 |= AR_IMR_S2_DTIM; 172 if (ints & HAL_INT_DTIMSYNC) 173 mask2 |= AR_IMR_S2_DTIMSYNC; 174 if (ints & HAL_INT_CABEND) 175 mask2 |= AR_IMR_S2_CABEND; 176 if (ints & HAL_INT_TBTT) 177 mask2 |= AR_IMR_S2_TBTT; 178 } 179 if (ints & HAL_INT_FATAL) { 180 /* 181 * NB: ar5212Reset sets MCABT+SSERR+DPERR in AR_IMR_S2 182 * so enabling HIUERR enables delivery. 183 */ 184 mask |= AR_IMR_HIUERR; 185 } 186 187 /* Write the new IMR and store off our SW copy. */ 188 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: new IMR 0x%x\n", __func__, mask); 189 OS_REG_WRITE(ah, AR_IMR, mask); 190 OS_REG_WRITE(ah, AR_IMR_S2, 191 (OS_REG_READ(ah, AR_IMR_S2) &~ AR_IMR_SR2_BCNMISC) | mask2); 192 ahp->ah_maskReg = ints; 193 194 /* Re-enable interrupts if they were enabled before. */ 195 if (ints & HAL_INT_GLOBAL) { 196 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: enable IER\n", __func__); 197 OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE); 198 } 199 return omask; 200 } 201