1 /*- 2 * SPDX-License-Identifier: ISC 3 * 4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 5 * Copyright (c) 2002-2008 Atheros Communications, Inc. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 * 19 * $FreeBSD$ 20 */ 21 #include "opt_ah.h" 22 23 #include "ah.h" 24 #include "ah_internal.h" 25 26 #include "ar5212/ar5212.h" 27 #include "ar5212/ar5212reg.h" 28 #include "ar5212/ar5212phy.h" 29 30 31 /* 32 * Checks to see if an interrupt is pending on our NIC 33 * 34 * Returns: TRUE if an interrupt is pending 35 * FALSE if not 36 */ 37 HAL_BOOL 38 ar5212IsInterruptPending(struct ath_hal *ah) 39 { 40 /* 41 * Some platforms trigger our ISR before applying power to 42 * the card, so make sure the INTPEND is really 1, not 0xffffffff. 43 */ 44 return (OS_REG_READ(ah, AR_INTPEND) == AR_INTPEND_TRUE); 45 } 46 47 /* 48 * Reads the Interrupt Status Register value from the NIC, thus deasserting 49 * the interrupt line, and returns both the masked and unmasked mapped ISR 50 * values. The value returned is mapped to abstract the hw-specific bit 51 * locations in the Interrupt Status Register. 52 * 53 * Returns: A hardware-abstracted bitmap of all non-masked-out 54 * interrupts pending, as well as an unmasked value 55 */ 56 HAL_BOOL 57 ar5212GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked) 58 { 59 uint32_t isr, isr0, isr1; 60 uint32_t mask2; 61 struct ath_hal_5212 *ahp = AH5212(ah); 62 63 isr = OS_REG_READ(ah, AR_ISR); 64 mask2 = 0; 65 if (isr & AR_ISR_BCNMISC) { 66 uint32_t isr2 = OS_REG_READ(ah, AR_ISR_S2); 67 if (isr2 & AR_ISR_S2_TIM) 68 mask2 |= HAL_INT_TIM; 69 if (isr2 & AR_ISR_S2_DTIM) 70 mask2 |= HAL_INT_DTIM; 71 if (isr2 & AR_ISR_S2_DTIMSYNC) 72 mask2 |= HAL_INT_DTIMSYNC; 73 if (isr2 & AR_ISR_S2_CABEND) 74 mask2 |= HAL_INT_CABEND; 75 if (isr2 & AR_ISR_S2_TBTT) 76 mask2 |= HAL_INT_TBTT; 77 } 78 isr = OS_REG_READ(ah, AR_ISR_RAC); 79 if (isr == 0xffffffff) { 80 *masked = 0; 81 return AH_FALSE; 82 } 83 84 *masked = isr & HAL_INT_COMMON; 85 86 if (isr & AR_ISR_HIUERR) 87 *masked |= HAL_INT_FATAL; 88 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR)) 89 *masked |= HAL_INT_RX; 90 if (isr & (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | AR_ISR_TXEOL)) { 91 *masked |= HAL_INT_TX; 92 isr0 = OS_REG_READ(ah, AR_ISR_S0_S); 93 ahp->ah_intrTxqs |= MS(isr0, AR_ISR_S0_QCU_TXOK); 94 ahp->ah_intrTxqs |= MS(isr0, AR_ISR_S0_QCU_TXDESC); 95 isr1 = OS_REG_READ(ah, AR_ISR_S1_S); 96 ahp->ah_intrTxqs |= MS(isr1, AR_ISR_S1_QCU_TXERR); 97 ahp->ah_intrTxqs |= MS(isr1, AR_ISR_S1_QCU_TXEOL); 98 } 99 100 /* 101 * Receive overrun is usually non-fatal on Oahu/Spirit. 102 * BUT on some parts rx could fail and the chip must be reset. 103 * So we force a hardware reset in all cases. 104 */ 105 if ((isr & AR_ISR_RXORN) && AH_PRIVATE(ah)->ah_rxornIsFatal) { 106 HALDEBUG(ah, HAL_DEBUG_ANY, 107 "%s: receive FIFO overrun interrupt\n", __func__); 108 *masked |= HAL_INT_FATAL; 109 } 110 *masked |= mask2; 111 112 /* 113 * On fatal errors collect ISR state for debugging. 114 */ 115 if (*masked & HAL_INT_FATAL) { 116 AH_PRIVATE(ah)->ah_fatalState[0] = isr; 117 AH_PRIVATE(ah)->ah_fatalState[1] = OS_REG_READ(ah, AR_ISR_S0_S); 118 AH_PRIVATE(ah)->ah_fatalState[2] = OS_REG_READ(ah, AR_ISR_S1_S); 119 AH_PRIVATE(ah)->ah_fatalState[3] = OS_REG_READ(ah, AR_ISR_S2_S); 120 AH_PRIVATE(ah)->ah_fatalState[4] = OS_REG_READ(ah, AR_ISR_S3_S); 121 AH_PRIVATE(ah)->ah_fatalState[5] = OS_REG_READ(ah, AR_ISR_S4_S); 122 HALDEBUG(ah, HAL_DEBUG_ANY, 123 "%s: fatal error, ISR_RAC=0x%x ISR_S2_S=0x%x\n", 124 __func__, isr, AH_PRIVATE(ah)->ah_fatalState[3]); 125 } 126 return AH_TRUE; 127 } 128 129 HAL_INT 130 ar5212GetInterrupts(struct ath_hal *ah) 131 { 132 return AH5212(ah)->ah_maskReg; 133 } 134 135 /* 136 * Atomically enables NIC interrupts. Interrupts are passed in 137 * via the enumerated bitmask in ints. 138 */ 139 HAL_INT 140 ar5212SetInterrupts(struct ath_hal *ah, HAL_INT ints) 141 { 142 struct ath_hal_5212 *ahp = AH5212(ah); 143 uint32_t omask = ahp->ah_maskReg; 144 uint32_t mask, mask2; 145 146 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: 0x%x => 0x%x\n", 147 __func__, omask, ints); 148 149 if (omask & HAL_INT_GLOBAL) { 150 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: disable IER\n", __func__); 151 OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE); 152 (void) OS_REG_READ(ah, AR_IER); /* flush write to HW */ 153 } 154 155 mask = ints & HAL_INT_COMMON; 156 mask2 = 0; 157 if (ints & HAL_INT_TX) { 158 if (ahp->ah_txOkInterruptMask) 159 mask |= AR_IMR_TXOK; 160 if (ahp->ah_txErrInterruptMask) 161 mask |= AR_IMR_TXERR; 162 if (ahp->ah_txDescInterruptMask) 163 mask |= AR_IMR_TXDESC; 164 if (ahp->ah_txEolInterruptMask) 165 mask |= AR_IMR_TXEOL; 166 } 167 if (ints & HAL_INT_RX) 168 mask |= AR_IMR_RXOK | AR_IMR_RXERR | AR_IMR_RXDESC; 169 if (ints & (HAL_INT_BMISC)) { 170 mask |= AR_IMR_BCNMISC; 171 if (ints & HAL_INT_TIM) 172 mask2 |= AR_IMR_S2_TIM; 173 if (ints & HAL_INT_DTIM) 174 mask2 |= AR_IMR_S2_DTIM; 175 if (ints & HAL_INT_DTIMSYNC) 176 mask2 |= AR_IMR_S2_DTIMSYNC; 177 if (ints & HAL_INT_CABEND) 178 mask2 |= AR_IMR_S2_CABEND; 179 if (ints & HAL_INT_TBTT) 180 mask2 |= AR_IMR_S2_TBTT; 181 } 182 if (ints & HAL_INT_FATAL) { 183 /* 184 * NB: ar5212Reset sets MCABT+SSERR+DPERR in AR_IMR_S2 185 * so enabling HIUERR enables delivery. 186 */ 187 mask |= AR_IMR_HIUERR; 188 } 189 190 /* Write the new IMR and store off our SW copy. */ 191 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: new IMR 0x%x\n", __func__, mask); 192 OS_REG_WRITE(ah, AR_IMR, mask); 193 OS_REG_WRITE(ah, AR_IMR_S2, 194 (OS_REG_READ(ah, AR_IMR_S2) &~ AR_IMR_SR2_BCNMISC) | mask2); 195 ahp->ah_maskReg = ints; 196 197 /* Re-enable interrupts if they were enabled before. */ 198 if (ints & HAL_INT_GLOBAL) { 199 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: enable IER\n", __func__); 200 OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE); 201 } 202 return omask; 203 } 204