1 /*- 2 * SPDX-License-Identifier: ISC 3 * 4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 5 * Copyright (c) 2002-2008 Atheros Communications, Inc. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 #include "opt_ah.h" 20 21 #include "ah.h" 22 #include "ah_internal.h" 23 24 #include "ar5212/ar5212.h" 25 #include "ar5212/ar5212reg.h" 26 #include "ar5212/ar5212desc.h" 27 28 /* 29 * Return the hardware NextTBTT in TSF 30 */ 31 uint64_t 32 ar5212GetNextTBTT(struct ath_hal *ah) 33 { 34 #define TU_TO_TSF(_tu) (((uint64_t)(_tu)) << 10) 35 return TU_TO_TSF(OS_REG_READ(ah, AR_TIMER0)); 36 #undef TU_TO_TSF 37 } 38 39 /* 40 * Initialize all of the hardware registers used to 41 * send beacons. Note that for station operation the 42 * driver calls ar5212SetStaBeaconTimers instead. 43 */ 44 void 45 ar5212SetBeaconTimers(struct ath_hal *ah, const HAL_BEACON_TIMERS *bt) 46 { 47 struct ath_hal_5212 *ahp = AH5212(ah); 48 49 /* 50 * Limit the timers to their specific resolutions: 51 * 52 * + Timer 0 - 0..15 0xffff TU 53 * + Timer 1 - 0..18 0x7ffff TU/8 54 * + Timer 2 - 0..24 0x1ffffff TU/8 55 * + Timer 3 - 0..15 0xffff TU 56 */ 57 OS_REG_WRITE(ah, AR_TIMER0, bt->bt_nexttbtt & 0xffff); 58 OS_REG_WRITE(ah, AR_TIMER1, bt->bt_nextdba & 0x7ffff); 59 OS_REG_WRITE(ah, AR_TIMER2, bt->bt_nextswba & 0x1ffffff); 60 /* XXX force nextatim to be non-zero? */ 61 OS_REG_WRITE(ah, AR_TIMER3, bt->bt_nextatim & 0xffff); 62 /* 63 * Set the Beacon register after setting all timers. 64 */ 65 if (bt->bt_intval & AR_BEACON_RESET_TSF) { 66 /* 67 * When resetting the TSF, 68 * write twice to the corresponding register; each 69 * write to the RESET_TSF bit toggles the internal 70 * signal to cause a reset of the TSF - but if the signal 71 * is left high, it will reset the TSF on the next 72 * chip reset also! writing the bit an even number 73 * of times fixes this issue 74 */ 75 OS_REG_WRITE(ah, AR_BEACON, AR_BEACON_RESET_TSF); 76 } 77 OS_REG_WRITE(ah, AR_BEACON, bt->bt_intval); 78 ahp->ah_beaconInterval = (bt->bt_intval & HAL_BEACON_PERIOD); 79 } 80 81 /* 82 * Old api for setting up beacon timer registers when 83 * operating in !station mode. Note the fixed constants 84 * adjusting the DBA and SWBA timers and the fixed ATIM 85 * window. 86 */ 87 void 88 ar5212BeaconInit(struct ath_hal *ah, 89 uint32_t next_beacon, uint32_t beacon_period) 90 { 91 HAL_BEACON_TIMERS bt; 92 93 bt.bt_nexttbtt = next_beacon; 94 /* 95 * TIMER1: in AP/adhoc mode this controls the DMA beacon 96 * alert timer; otherwise it controls the next wakeup time. 97 * TIMER2: in AP mode, it controls the SBA beacon alert 98 * interrupt; otherwise it sets the start of the next CFP. 99 */ 100 switch (AH_PRIVATE(ah)->ah_opmode) { 101 case HAL_M_STA: 102 case HAL_M_MONITOR: 103 bt.bt_nextdba = 0xffff; 104 bt.bt_nextswba = 0x7ffff; 105 break; 106 case HAL_M_HOSTAP: 107 case HAL_M_IBSS: 108 bt.bt_nextdba = (next_beacon - 109 ah->ah_config.ah_dma_beacon_response_time) << 3; /* 1/8 TU */ 110 bt.bt_nextswba = (next_beacon - 111 ah->ah_config.ah_sw_beacon_response_time) << 3; /* 1/8 TU */ 112 break; 113 } 114 /* 115 * Set the ATIM window 116 * Our hardware does not support an ATIM window of 0 117 * (beacons will not work). If the ATIM windows is 0, 118 * force it to 1. 119 */ 120 bt.bt_nextatim = next_beacon + 1; 121 bt.bt_intval = beacon_period & 122 (AR_BEACON_PERIOD | AR_BEACON_RESET_TSF | AR_BEACON_EN); 123 ar5212SetBeaconTimers(ah, &bt); 124 } 125 126 void 127 ar5212ResetStaBeaconTimers(struct ath_hal *ah) 128 { 129 uint32_t val; 130 131 OS_REG_WRITE(ah, AR_TIMER0, 0); /* no beacons */ 132 val = OS_REG_READ(ah, AR_STA_ID1); 133 val |= AR_STA_ID1_PWR_SAV; /* XXX */ 134 /* tell the h/w that the associated AP is not PCF capable */ 135 OS_REG_WRITE(ah, AR_STA_ID1, 136 val & ~(AR_STA_ID1_USE_DEFANT | AR_STA_ID1_PCF)); 137 OS_REG_WRITE(ah, AR_BEACON, AR_BEACON_PERIOD); 138 } 139 140 /* 141 * Set all the beacon related bits on the h/w for stations 142 * i.e. initializes the corresponding h/w timers; 143 * also tells the h/w whether to anticipate PCF beacons 144 */ 145 void 146 ar5212SetStaBeaconTimers(struct ath_hal *ah, const HAL_BEACON_STATE *bs) 147 { 148 struct ath_hal_5212 *ahp = AH5212(ah); 149 uint32_t nextTbtt, nextdtim,beaconintval, dtimperiod; 150 151 HALASSERT(bs->bs_intval != 0); 152 /* if the AP will do PCF */ 153 if (bs->bs_cfpmaxduration != 0) { 154 /* tell the h/w that the associated AP is PCF capable */ 155 OS_REG_WRITE(ah, AR_STA_ID1, 156 OS_REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PCF); 157 158 /* set CFP_PERIOD(1.024ms) register */ 159 OS_REG_WRITE(ah, AR_CFP_PERIOD, bs->bs_cfpperiod); 160 161 /* set CFP_DUR(1.024ms) register to max cfp duration */ 162 OS_REG_WRITE(ah, AR_CFP_DUR, bs->bs_cfpmaxduration); 163 164 /* set TIMER2(128us) to anticipated time of next CFP */ 165 OS_REG_WRITE(ah, AR_TIMER2, bs->bs_cfpnext << 3); 166 } else { 167 /* tell the h/w that the associated AP is not PCF capable */ 168 OS_REG_WRITE(ah, AR_STA_ID1, 169 OS_REG_READ(ah, AR_STA_ID1) &~ AR_STA_ID1_PCF); 170 } 171 172 /* 173 * Set TIMER0(1.024ms) to the anticipated time of the next beacon. 174 */ 175 OS_REG_WRITE(ah, AR_TIMER0, bs->bs_nexttbtt); 176 177 /* 178 * Start the beacon timers by setting the BEACON register 179 * to the beacon interval; also write the tim offset which 180 * we should know by now. The code, in ar5211WriteAssocid, 181 * also sets the tim offset once the AID is known which can 182 * be left as such for now. 183 */ 184 OS_REG_WRITE(ah, AR_BEACON, 185 (OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_PERIOD|AR_BEACON_TIM)) 186 | SM(bs->bs_intval, AR_BEACON_PERIOD) 187 | SM(bs->bs_timoffset ? bs->bs_timoffset + 4 : 0, AR_BEACON_TIM) 188 ); 189 190 /* 191 * Configure the BMISS interrupt. Note that we 192 * assume the caller blocks interrupts while enabling 193 * the threshold. 194 */ 195 HALASSERT(bs->bs_bmissthreshold <= MS(0xffffffff, AR_RSSI_THR_BM_THR)); 196 ahp->ah_rssiThr = (ahp->ah_rssiThr &~ AR_RSSI_THR_BM_THR) 197 | SM(bs->bs_bmissthreshold, AR_RSSI_THR_BM_THR); 198 OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr); 199 200 /* 201 * Program the sleep registers to correlate with the beacon setup. 202 */ 203 204 /* 205 * Oahu beacons timers on the station were used for power 206 * save operation (waking up in anticipation of a beacon) 207 * and any CFP function; Venice does sleep/power-save timers 208 * differently - so this is the right place to set them up; 209 * don't think the beacon timers are used by venice sta hw 210 * for any useful purpose anymore 211 * Setup venice's sleep related timers 212 * Current implementation assumes sw processing of beacons - 213 * assuming an interrupt is generated every beacon which 214 * causes the hardware to become awake until the sw tells 215 * it to go to sleep again; beacon timeout is to allow for 216 * beacon jitter; cab timeout is max time to wait for cab 217 * after seeing the last DTIM or MORE CAB bit 218 */ 219 #define CAB_TIMEOUT_VAL 10 /* in TU */ 220 #define BEACON_TIMEOUT_VAL 10 /* in TU */ 221 #define SLEEP_SLOP 3 /* in TU */ 222 223 /* 224 * For max powersave mode we may want to sleep for longer than a 225 * beacon period and not want to receive all beacons; modify the 226 * timers accordingly; make sure to align the next TIM to the 227 * next DTIM if we decide to wake for DTIMs only 228 */ 229 beaconintval = bs->bs_intval & HAL_BEACON_PERIOD; 230 HALASSERT(beaconintval != 0); 231 if (bs->bs_sleepduration > beaconintval) { 232 HALASSERT(roundup(bs->bs_sleepduration, beaconintval) == 233 bs->bs_sleepduration); 234 beaconintval = bs->bs_sleepduration; 235 } 236 dtimperiod = bs->bs_dtimperiod; 237 if (bs->bs_sleepduration > dtimperiod) { 238 HALASSERT(dtimperiod == 0 || 239 roundup(bs->bs_sleepduration, dtimperiod) == 240 bs->bs_sleepduration); 241 dtimperiod = bs->bs_sleepduration; 242 } 243 HALASSERT(beaconintval <= dtimperiod); 244 if (beaconintval == dtimperiod) 245 nextTbtt = bs->bs_nextdtim; 246 else 247 nextTbtt = bs->bs_nexttbtt; 248 nextdtim = bs->bs_nextdtim; 249 250 OS_REG_WRITE(ah, AR_SLEEP1, 251 SM((nextdtim - SLEEP_SLOP) << 3, AR_SLEEP1_NEXT_DTIM) 252 | SM(CAB_TIMEOUT_VAL, AR_SLEEP1_CAB_TIMEOUT) 253 | AR_SLEEP1_ASSUME_DTIM 254 | AR_SLEEP1_ENH_SLEEP_ENA 255 ); 256 OS_REG_WRITE(ah, AR_SLEEP2, 257 SM((nextTbtt - SLEEP_SLOP) << 3, AR_SLEEP2_NEXT_TIM) 258 | SM(BEACON_TIMEOUT_VAL, AR_SLEEP2_BEACON_TIMEOUT) 259 ); 260 OS_REG_WRITE(ah, AR_SLEEP3, 261 SM(beaconintval, AR_SLEEP3_TIM_PERIOD) 262 | SM(dtimperiod, AR_SLEEP3_DTIM_PERIOD) 263 ); 264 HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: next DTIM %d\n", 265 __func__, bs->bs_nextdtim); 266 HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: next beacon %d\n", 267 __func__, nextTbtt); 268 HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: beacon period %d\n", 269 __func__, beaconintval); 270 HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: DTIM period %d\n", 271 __func__, dtimperiod); 272 #undef CAB_TIMEOUT_VAL 273 #undef BEACON_TIMEOUT_VAL 274 #undef SLEEP_SLOP 275 } 276