1 /* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19 #include "opt_ah.h" 20 21 #include "ah.h" 22 #include "ah_internal.h" 23 24 #include "ar5212/ar5212.h" 25 #include "ar5212/ar5212reg.h" 26 #include "ar5212/ar5212desc.h" 27 28 /* 29 * Return the hardware NextTBTT in TSF 30 */ 31 uint64_t 32 ar5212GetNextTBTT(struct ath_hal *ah) 33 { 34 #define TU_TO_TSF(_tu) (((uint64_t)(_tu)) << 10) 35 return TU_TO_TSF(OS_REG_READ(ah, AR_TIMER0)); 36 #undef TU_TO_TSF 37 } 38 39 /* 40 * Initialize all of the hardware registers used to 41 * send beacons. Note that for station operation the 42 * driver calls ar5212SetStaBeaconTimers instead. 43 */ 44 void 45 ar5212SetBeaconTimers(struct ath_hal *ah, const HAL_BEACON_TIMERS *bt) 46 { 47 struct ath_hal_5212 *ahp = AH5212(ah); 48 49 OS_REG_WRITE(ah, AR_TIMER0, bt->bt_nexttbtt); 50 OS_REG_WRITE(ah, AR_TIMER1, bt->bt_nextdba); 51 OS_REG_WRITE(ah, AR_TIMER2, bt->bt_nextswba); 52 OS_REG_WRITE(ah, AR_TIMER3, bt->bt_nextatim); 53 /* 54 * Set the Beacon register after setting all timers. 55 */ 56 if (bt->bt_intval & AR_BEACON_RESET_TSF) { 57 /* 58 * When resetting the TSF, 59 * write twice to the corresponding register; each 60 * write to the RESET_TSF bit toggles the internal 61 * signal to cause a reset of the TSF - but if the signal 62 * is left high, it will reset the TSF on the next 63 * chip reset also! writing the bit an even number 64 * of times fixes this issue 65 */ 66 OS_REG_WRITE(ah, AR_BEACON, AR_BEACON_RESET_TSF); 67 } 68 OS_REG_WRITE(ah, AR_BEACON, bt->bt_intval); 69 ahp->ah_beaconInterval = (bt->bt_intval & HAL_BEACON_PERIOD); 70 } 71 72 /* 73 * Old api for setting up beacon timer registers when 74 * operating in !station mode. Note the fixed constants 75 * adjusting the DBA and SWBA timers and the fixed ATIM 76 * window. 77 */ 78 void 79 ar5212BeaconInit(struct ath_hal *ah, 80 uint32_t next_beacon, uint32_t beacon_period) 81 { 82 HAL_BEACON_TIMERS bt; 83 84 bt.bt_nexttbtt = next_beacon; 85 /* 86 * TIMER1: in AP/adhoc mode this controls the DMA beacon 87 * alert timer; otherwise it controls the next wakeup time. 88 * TIMER2: in AP mode, it controls the SBA beacon alert 89 * interrupt; otherwise it sets the start of the next CFP. 90 */ 91 switch (AH_PRIVATE(ah)->ah_opmode) { 92 case HAL_M_STA: 93 case HAL_M_MONITOR: 94 bt.bt_nextdba = 0xffff; 95 bt.bt_nextswba = 0x7ffff; 96 break; 97 case HAL_M_HOSTAP: 98 case HAL_M_IBSS: 99 bt.bt_nextdba = (next_beacon - 100 ah->ah_config.ah_dma_beacon_response_time) << 3; /* 1/8 TU */ 101 bt.bt_nextswba = (next_beacon - 102 ah->ah_config.ah_sw_beacon_response_time) << 3; /* 1/8 TU */ 103 break; 104 } 105 /* 106 * Set the ATIM window 107 * Our hardware does not support an ATIM window of 0 108 * (beacons will not work). If the ATIM windows is 0, 109 * force it to 1. 110 */ 111 bt.bt_nextatim = next_beacon + 1; 112 bt.bt_intval = beacon_period & 113 (AR_BEACON_PERIOD | AR_BEACON_RESET_TSF | AR_BEACON_EN); 114 ar5212SetBeaconTimers(ah, &bt); 115 } 116 117 void 118 ar5212ResetStaBeaconTimers(struct ath_hal *ah) 119 { 120 uint32_t val; 121 122 OS_REG_WRITE(ah, AR_TIMER0, 0); /* no beacons */ 123 val = OS_REG_READ(ah, AR_STA_ID1); 124 val |= AR_STA_ID1_PWR_SAV; /* XXX */ 125 /* tell the h/w that the associated AP is not PCF capable */ 126 OS_REG_WRITE(ah, AR_STA_ID1, 127 val & ~(AR_STA_ID1_USE_DEFANT | AR_STA_ID1_PCF)); 128 OS_REG_WRITE(ah, AR_BEACON, AR_BEACON_PERIOD); 129 } 130 131 /* 132 * Set all the beacon related bits on the h/w for stations 133 * i.e. initializes the corresponding h/w timers; 134 * also tells the h/w whether to anticipate PCF beacons 135 */ 136 void 137 ar5212SetStaBeaconTimers(struct ath_hal *ah, const HAL_BEACON_STATE *bs) 138 { 139 struct ath_hal_5212 *ahp = AH5212(ah); 140 uint32_t nextTbtt, nextdtim,beaconintval, dtimperiod; 141 142 HALASSERT(bs->bs_intval != 0); 143 /* if the AP will do PCF */ 144 if (bs->bs_cfpmaxduration != 0) { 145 /* tell the h/w that the associated AP is PCF capable */ 146 OS_REG_WRITE(ah, AR_STA_ID1, 147 OS_REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PCF); 148 149 /* set CFP_PERIOD(1.024ms) register */ 150 OS_REG_WRITE(ah, AR_CFP_PERIOD, bs->bs_cfpperiod); 151 152 /* set CFP_DUR(1.024ms) register to max cfp duration */ 153 OS_REG_WRITE(ah, AR_CFP_DUR, bs->bs_cfpmaxduration); 154 155 /* set TIMER2(128us) to anticipated time of next CFP */ 156 OS_REG_WRITE(ah, AR_TIMER2, bs->bs_cfpnext << 3); 157 } else { 158 /* tell the h/w that the associated AP is not PCF capable */ 159 OS_REG_WRITE(ah, AR_STA_ID1, 160 OS_REG_READ(ah, AR_STA_ID1) &~ AR_STA_ID1_PCF); 161 } 162 163 /* 164 * Set TIMER0(1.024ms) to the anticipated time of the next beacon. 165 */ 166 OS_REG_WRITE(ah, AR_TIMER0, bs->bs_nexttbtt); 167 168 /* 169 * Start the beacon timers by setting the BEACON register 170 * to the beacon interval; also write the tim offset which 171 * we should know by now. The code, in ar5211WriteAssocid, 172 * also sets the tim offset once the AID is known which can 173 * be left as such for now. 174 */ 175 OS_REG_WRITE(ah, AR_BEACON, 176 (OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_PERIOD|AR_BEACON_TIM)) 177 | SM(bs->bs_intval, AR_BEACON_PERIOD) 178 | SM(bs->bs_timoffset ? bs->bs_timoffset + 4 : 0, AR_BEACON_TIM) 179 ); 180 181 /* 182 * Configure the BMISS interrupt. Note that we 183 * assume the caller blocks interrupts while enabling 184 * the threshold. 185 */ 186 HALASSERT(bs->bs_bmissthreshold <= MS(0xffffffff, AR_RSSI_THR_BM_THR)); 187 ahp->ah_rssiThr = (ahp->ah_rssiThr &~ AR_RSSI_THR_BM_THR) 188 | SM(bs->bs_bmissthreshold, AR_RSSI_THR_BM_THR); 189 OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr); 190 191 /* 192 * Program the sleep registers to correlate with the beacon setup. 193 */ 194 195 /* 196 * Oahu beacons timers on the station were used for power 197 * save operation (waking up in anticipation of a beacon) 198 * and any CFP function; Venice does sleep/power-save timers 199 * differently - so this is the right place to set them up; 200 * don't think the beacon timers are used by venice sta hw 201 * for any useful purpose anymore 202 * Setup venice's sleep related timers 203 * Current implementation assumes sw processing of beacons - 204 * assuming an interrupt is generated every beacon which 205 * causes the hardware to become awake until the sw tells 206 * it to go to sleep again; beacon timeout is to allow for 207 * beacon jitter; cab timeout is max time to wait for cab 208 * after seeing the last DTIM or MORE CAB bit 209 */ 210 #define CAB_TIMEOUT_VAL 10 /* in TU */ 211 #define BEACON_TIMEOUT_VAL 10 /* in TU */ 212 #define SLEEP_SLOP 3 /* in TU */ 213 214 /* 215 * For max powersave mode we may want to sleep for longer than a 216 * beacon period and not want to receive all beacons; modify the 217 * timers accordingly; make sure to align the next TIM to the 218 * next DTIM if we decide to wake for DTIMs only 219 */ 220 beaconintval = bs->bs_intval & HAL_BEACON_PERIOD; 221 HALASSERT(beaconintval != 0); 222 if (bs->bs_sleepduration > beaconintval) { 223 HALASSERT(roundup(bs->bs_sleepduration, beaconintval) == 224 bs->bs_sleepduration); 225 beaconintval = bs->bs_sleepduration; 226 } 227 dtimperiod = bs->bs_dtimperiod; 228 if (bs->bs_sleepduration > dtimperiod) { 229 HALASSERT(dtimperiod == 0 || 230 roundup(bs->bs_sleepduration, dtimperiod) == 231 bs->bs_sleepduration); 232 dtimperiod = bs->bs_sleepduration; 233 } 234 HALASSERT(beaconintval <= dtimperiod); 235 if (beaconintval == dtimperiod) 236 nextTbtt = bs->bs_nextdtim; 237 else 238 nextTbtt = bs->bs_nexttbtt; 239 nextdtim = bs->bs_nextdtim; 240 241 OS_REG_WRITE(ah, AR_SLEEP1, 242 SM((nextdtim - SLEEP_SLOP) << 3, AR_SLEEP1_NEXT_DTIM) 243 | SM(CAB_TIMEOUT_VAL, AR_SLEEP1_CAB_TIMEOUT) 244 | AR_SLEEP1_ASSUME_DTIM 245 | AR_SLEEP1_ENH_SLEEP_ENA 246 ); 247 OS_REG_WRITE(ah, AR_SLEEP2, 248 SM((nextTbtt - SLEEP_SLOP) << 3, AR_SLEEP2_NEXT_TIM) 249 | SM(BEACON_TIMEOUT_VAL, AR_SLEEP2_BEACON_TIMEOUT) 250 ); 251 OS_REG_WRITE(ah, AR_SLEEP3, 252 SM(beaconintval, AR_SLEEP3_TIM_PERIOD) 253 | SM(dtimperiod, AR_SLEEP3_DTIM_PERIOD) 254 ); 255 HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: next DTIM %d\n", 256 __func__, bs->bs_nextdtim); 257 HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: next beacon %d\n", 258 __func__, nextTbtt); 259 HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: beacon period %d\n", 260 __func__, beaconintval); 261 HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: DTIM period %d\n", 262 __func__, dtimperiod); 263 #undef CAB_TIMEOUT_VAL 264 #undef BEACON_TIMEOUT_VAL 265 #undef SLEEP_SLOP 266 } 267