1 /* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19 #include "opt_ah.h" 20 21 #include "ah.h" 22 #include "ah_internal.h" 23 #include "ah_devid.h" 24 25 #include "ar5212/ar5212.h" 26 #include "ar5212/ar5212reg.h" 27 #include "ar5212/ar5212phy.h" 28 29 #define AH_5212_COMMON 30 #include "ar5212/ar5212.ini" 31 32 static void ar5212ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore); 33 static void ar5212DisablePCIE(struct ath_hal *ah); 34 35 static const struct ath_hal_private ar5212hal = {{ 36 .ah_magic = AR5212_MAGIC, 37 38 .ah_getRateTable = ar5212GetRateTable, 39 .ah_detach = ar5212Detach, 40 41 /* Reset Functions */ 42 .ah_reset = ar5212Reset, 43 .ah_phyDisable = ar5212PhyDisable, 44 .ah_disable = ar5212Disable, 45 .ah_configPCIE = ar5212ConfigPCIE, 46 .ah_disablePCIE = ar5212DisablePCIE, 47 .ah_setPCUConfig = ar5212SetPCUConfig, 48 .ah_perCalibration = ar5212PerCalibration, 49 .ah_perCalibrationN = ar5212PerCalibrationN, 50 .ah_resetCalValid = ar5212ResetCalValid, 51 .ah_setTxPowerLimit = ar5212SetTxPowerLimit, 52 .ah_getChanNoise = ath_hal_getChanNoise, 53 54 /* Transmit functions */ 55 .ah_updateTxTrigLevel = ar5212UpdateTxTrigLevel, 56 .ah_setupTxQueue = ar5212SetupTxQueue, 57 .ah_setTxQueueProps = ar5212SetTxQueueProps, 58 .ah_getTxQueueProps = ar5212GetTxQueueProps, 59 .ah_releaseTxQueue = ar5212ReleaseTxQueue, 60 .ah_resetTxQueue = ar5212ResetTxQueue, 61 .ah_getTxDP = ar5212GetTxDP, 62 .ah_setTxDP = ar5212SetTxDP, 63 .ah_numTxPending = ar5212NumTxPending, 64 .ah_startTxDma = ar5212StartTxDma, 65 .ah_stopTxDma = ar5212StopTxDma, 66 .ah_setupTxDesc = ar5212SetupTxDesc, 67 .ah_setupXTxDesc = ar5212SetupXTxDesc, 68 .ah_fillTxDesc = ar5212FillTxDesc, 69 .ah_procTxDesc = ar5212ProcTxDesc, 70 .ah_getTxIntrQueue = ar5212GetTxIntrQueue, 71 .ah_reqTxIntrDesc = ar5212IntrReqTxDesc, 72 .ah_getTxCompletionRates = ar5212GetTxCompletionRates, 73 74 /* RX Functions */ 75 .ah_getRxDP = ar5212GetRxDP, 76 .ah_setRxDP = ar5212SetRxDP, 77 .ah_enableReceive = ar5212EnableReceive, 78 .ah_stopDmaReceive = ar5212StopDmaReceive, 79 .ah_startPcuReceive = ar5212StartPcuReceive, 80 .ah_stopPcuReceive = ar5212StopPcuReceive, 81 .ah_setMulticastFilter = ar5212SetMulticastFilter, 82 .ah_setMulticastFilterIndex = ar5212SetMulticastFilterIndex, 83 .ah_clrMulticastFilterIndex = ar5212ClrMulticastFilterIndex, 84 .ah_getRxFilter = ar5212GetRxFilter, 85 .ah_setRxFilter = ar5212SetRxFilter, 86 .ah_setupRxDesc = ar5212SetupRxDesc, 87 .ah_procRxDesc = ar5212ProcRxDesc, 88 .ah_rxMonitor = ar5212RxMonitor, 89 .ah_aniPoll = ar5212AniPoll, 90 .ah_procMibEvent = ar5212ProcessMibIntr, 91 92 /* Misc Functions */ 93 .ah_getCapability = ar5212GetCapability, 94 .ah_setCapability = ar5212SetCapability, 95 .ah_getDiagState = ar5212GetDiagState, 96 .ah_getMacAddress = ar5212GetMacAddress, 97 .ah_setMacAddress = ar5212SetMacAddress, 98 .ah_getBssIdMask = ar5212GetBssIdMask, 99 .ah_setBssIdMask = ar5212SetBssIdMask, 100 .ah_setRegulatoryDomain = ar5212SetRegulatoryDomain, 101 .ah_setLedState = ar5212SetLedState, 102 .ah_writeAssocid = ar5212WriteAssocid, 103 .ah_gpioCfgInput = ar5212GpioCfgInput, 104 .ah_gpioCfgOutput = ar5212GpioCfgOutput, 105 .ah_gpioGet = ar5212GpioGet, 106 .ah_gpioSet = ar5212GpioSet, 107 .ah_gpioSetIntr = ar5212GpioSetIntr, 108 .ah_getTsf32 = ar5212GetTsf32, 109 .ah_getTsf64 = ar5212GetTsf64, 110 .ah_resetTsf = ar5212ResetTsf, 111 .ah_detectCardPresent = ar5212DetectCardPresent, 112 .ah_updateMibCounters = ar5212UpdateMibCounters, 113 .ah_getRfGain = ar5212GetRfgain, 114 .ah_getDefAntenna = ar5212GetDefAntenna, 115 .ah_setDefAntenna = ar5212SetDefAntenna, 116 .ah_getAntennaSwitch = ar5212GetAntennaSwitch, 117 .ah_setAntennaSwitch = ar5212SetAntennaSwitch, 118 .ah_setSifsTime = ar5212SetSifsTime, 119 .ah_getSifsTime = ar5212GetSifsTime, 120 .ah_setSlotTime = ar5212SetSlotTime, 121 .ah_getSlotTime = ar5212GetSlotTime, 122 .ah_setAckTimeout = ar5212SetAckTimeout, 123 .ah_getAckTimeout = ar5212GetAckTimeout, 124 .ah_setAckCTSRate = ar5212SetAckCTSRate, 125 .ah_getAckCTSRate = ar5212GetAckCTSRate, 126 .ah_setCTSTimeout = ar5212SetCTSTimeout, 127 .ah_getCTSTimeout = ar5212GetCTSTimeout, 128 .ah_setDecompMask = ar5212SetDecompMask, 129 .ah_setCoverageClass = ar5212SetCoverageClass, 130 .ah_setQuiet = ar5212SetQuiet, 131 132 /* DFS Functions */ 133 .ah_enableDfs = ar5212EnableDfs, 134 .ah_getDfsThresh = ar5212GetDfsThresh, 135 .ah_procRadarEvent = ar5212ProcessRadarEvent, 136 .ah_isFastClockEnabled = ar5212IsFastClockEnabled, 137 .ah_get11nExtBusy = ar5212Get11nExtBusy, 138 139 /* Key Cache Functions */ 140 .ah_getKeyCacheSize = ar5212GetKeyCacheSize, 141 .ah_resetKeyCacheEntry = ar5212ResetKeyCacheEntry, 142 .ah_isKeyCacheEntryValid = ar5212IsKeyCacheEntryValid, 143 .ah_setKeyCacheEntry = ar5212SetKeyCacheEntry, 144 .ah_setKeyCacheEntryMac = ar5212SetKeyCacheEntryMac, 145 146 /* Power Management Functions */ 147 .ah_setPowerMode = ar5212SetPowerMode, 148 .ah_getPowerMode = ar5212GetPowerMode, 149 150 /* Beacon Functions */ 151 .ah_setBeaconTimers = ar5212SetBeaconTimers, 152 .ah_beaconInit = ar5212BeaconInit, 153 .ah_setStationBeaconTimers = ar5212SetStaBeaconTimers, 154 .ah_resetStationBeaconTimers = ar5212ResetStaBeaconTimers, 155 .ah_getNextTBTT = ar5212GetNextTBTT, 156 157 /* Interrupt Functions */ 158 .ah_isInterruptPending = ar5212IsInterruptPending, 159 .ah_getPendingInterrupts = ar5212GetPendingInterrupts, 160 .ah_getInterrupts = ar5212GetInterrupts, 161 .ah_setInterrupts = ar5212SetInterrupts }, 162 163 .ah_getChannelEdges = ar5212GetChannelEdges, 164 .ah_getWirelessModes = ar5212GetWirelessModes, 165 .ah_eepromRead = ar5212EepromRead, 166 #ifdef AH_SUPPORT_WRITE_EEPROM 167 .ah_eepromWrite = ar5212EepromWrite, 168 #endif 169 .ah_getChipPowerLimits = ar5212GetChipPowerLimits, 170 }; 171 172 uint32_t 173 ar5212GetRadioRev(struct ath_hal *ah) 174 { 175 uint32_t val; 176 int i; 177 178 /* Read Radio Chip Rev Extract */ 179 OS_REG_WRITE(ah, AR_PHY(0x34), 0x00001c16); 180 for (i = 0; i < 8; i++) 181 OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000); 182 val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; 183 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 184 return ath_hal_reverseBits(val, 8); 185 } 186 187 static void 188 ar5212AniSetup(struct ath_hal *ah) 189 { 190 static const struct ar5212AniParams aniparams = { 191 .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 192 .totalSizeDesired = { -55, -55, -55, -55, -62 }, 193 .coarseHigh = { -14, -14, -14, -14, -12 }, 194 .coarseLow = { -64, -64, -64, -64, -70 }, 195 .firpwr = { -78, -78, -78, -78, -80 }, 196 .maxSpurImmunityLevel = 2, /* NB: depends on chip rev */ 197 .cycPwrThr1 = { 2, 4, 6, 8, 10, 12, 14, 16 }, 198 .maxFirstepLevel = 2, /* levels 0..2 */ 199 .firstep = { 0, 4, 8 }, 200 .ofdmTrigHigh = 500, 201 .ofdmTrigLow = 200, 202 .cckTrigHigh = 200, 203 .cckTrigLow = 100, 204 .rssiThrHigh = 40, 205 .rssiThrLow = 7, 206 .period = 100, 207 }; 208 if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN) { 209 struct ar5212AniParams tmp; 210 OS_MEMCPY(&tmp, &aniparams, sizeof(struct ar5212AniParams)); 211 tmp.maxSpurImmunityLevel = 7; /* Venice and earlier */ 212 ar5212AniAttach(ah, &tmp, &tmp, AH_TRUE); 213 } else 214 ar5212AniAttach(ah, &aniparams, &aniparams, AH_TRUE); 215 216 /* Set overridable ANI methods */ 217 AH5212(ah)->ah_aniControl = ar5212AniControl; 218 } 219 220 /* 221 * Attach for an AR5212 part. 222 */ 223 void 224 ar5212InitState(struct ath_hal_5212 *ahp, uint16_t devid, HAL_SOFTC sc, 225 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status) 226 { 227 #define N(a) (sizeof(a)/sizeof(a[0])) 228 static const uint8_t defbssidmask[IEEE80211_ADDR_LEN] = 229 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 230 struct ath_hal *ah; 231 232 ah = &ahp->ah_priv.h; 233 /* set initial values */ 234 OS_MEMCPY(&ahp->ah_priv, &ar5212hal, sizeof(struct ath_hal_private)); 235 ah->ah_sc = sc; 236 ah->ah_st = st; 237 ah->ah_sh = sh; 238 239 ah->ah_devid = devid; /* NB: for alq */ 240 AH_PRIVATE(ah)->ah_devid = devid; 241 AH_PRIVATE(ah)->ah_subvendorid = 0; /* XXX */ 242 243 AH_PRIVATE(ah)->ah_powerLimit = MAX_RATE_POWER; 244 AH_PRIVATE(ah)->ah_tpScale = HAL_TP_SCALE_MAX; /* no scaling */ 245 246 ahp->ah_antControl = HAL_ANT_VARIABLE; 247 ahp->ah_diversity = AH_TRUE; 248 ahp->ah_bIQCalibration = AH_FALSE; 249 /* 250 * Enable MIC handling. 251 */ 252 ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE; 253 ahp->ah_rssiThr = INIT_RSSI_THR; 254 ahp->ah_tpcEnabled = AH_FALSE; /* disabled by default */ 255 ahp->ah_phyPowerOn = AH_FALSE; 256 ahp->ah_macTPC = SM(MAX_RATE_POWER, AR_TPC_ACK) 257 | SM(MAX_RATE_POWER, AR_TPC_CTS) 258 | SM(MAX_RATE_POWER, AR_TPC_CHIRP); 259 ahp->ah_beaconInterval = 100; /* XXX [20..1000] */ 260 ahp->ah_enable32kHzClock = DONT_USE_32KHZ;/* XXX */ 261 ahp->ah_slottime = (u_int) -1; 262 ahp->ah_acktimeout = (u_int) -1; 263 ahp->ah_ctstimeout = (u_int) -1; 264 ahp->ah_sifstime = (u_int) -1; 265 ahp->ah_txTrigLev = INIT_TX_FIFO_THRESHOLD, 266 ahp->ah_maxTxTrigLev = MAX_TX_FIFO_THRESHOLD, 267 268 OS_MEMCPY(&ahp->ah_bssidmask, defbssidmask, IEEE80211_ADDR_LEN); 269 #undef N 270 } 271 272 /* 273 * Validate MAC version and revision. 274 */ 275 static HAL_BOOL 276 ar5212IsMacSupported(uint8_t macVersion, uint8_t macRev) 277 { 278 #define N(a) (sizeof(a)/sizeof(a[0])) 279 static const struct { 280 uint8_t version; 281 uint8_t revMin, revMax; 282 } macs[] = { 283 { AR_SREV_VERSION_VENICE, 284 AR_SREV_D2PLUS, AR_SREV_REVISION_MAX }, 285 { AR_SREV_VERSION_GRIFFIN, 286 AR_SREV_D2PLUS, AR_SREV_REVISION_MAX }, 287 { AR_SREV_5413, 288 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 289 { AR_SREV_5424, 290 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 291 { AR_SREV_2425, 292 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 293 { AR_SREV_2417, 294 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 295 }; 296 int i; 297 298 for (i = 0; i < N(macs); i++) 299 if (macs[i].version == macVersion && 300 macs[i].revMin <= macRev && macRev <= macs[i].revMax) 301 return AH_TRUE; 302 return AH_FALSE; 303 #undef N 304 } 305 306 /* 307 * Attach for an AR5212 part. 308 */ 309 static struct ath_hal * 310 ar5212Attach(uint16_t devid, HAL_SOFTC sc, 311 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 312 HAL_STATUS *status) 313 { 314 #define AH_EEPROM_PROTECT(ah) \ 315 (AH_PRIVATE(ah)->ah_ispcie)? AR_EEPROM_PROTECT_PCIE : AR_EEPROM_PROTECT) 316 struct ath_hal_5212 *ahp; 317 struct ath_hal *ah; 318 struct ath_hal_rf *rf; 319 uint32_t val; 320 uint16_t eeval; 321 HAL_STATUS ecode; 322 323 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 324 __func__, sc, (void*) st, (void*) sh); 325 326 /* NB: memory is returned zero'd */ 327 ahp = ath_hal_malloc(sizeof (struct ath_hal_5212)); 328 if (ahp == AH_NULL) { 329 HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 330 "%s: cannot allocate memory for state block\n", __func__); 331 *status = HAL_ENOMEM; 332 return AH_NULL; 333 } 334 ar5212InitState(ahp, devid, sc, st, sh, status); 335 ah = &ahp->ah_priv.h; 336 337 if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 338 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", 339 __func__); 340 ecode = HAL_EIO; 341 goto bad; 342 } 343 /* Read Revisions from Chips before taking out of reset */ 344 val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID; 345 AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S; 346 AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION; 347 AH_PRIVATE(ah)->ah_ispcie = IS_5424(ah) || IS_2425(ah); 348 349 if (!ar5212IsMacSupported(AH_PRIVATE(ah)->ah_macVersion, AH_PRIVATE(ah)->ah_macRev)) { 350 HALDEBUG(ah, HAL_DEBUG_ANY, 351 "%s: Mac Chip Rev 0x%02x.%x not supported\n" , 352 __func__, AH_PRIVATE(ah)->ah_macVersion, 353 AH_PRIVATE(ah)->ah_macRev); 354 ecode = HAL_ENOTSUPP; 355 goto bad; 356 } 357 358 /* setup common ini data; rf backends handle remainder */ 359 HAL_INI_INIT(&ahp->ah_ini_modes, ar5212Modes, 6); 360 HAL_INI_INIT(&ahp->ah_ini_common, ar5212Common, 2); 361 362 if (!ar5212ChipReset(ah, AH_NULL)) { /* reset chip */ 363 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 364 ecode = HAL_EIO; 365 goto bad; 366 } 367 368 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 369 370 if (AH_PRIVATE(ah)->ah_ispcie) { 371 /* XXX: build flag to disable this? */ 372 ath_hal_configPCIE(ah, AH_FALSE); 373 } 374 375 if (!ar5212ChipTest(ah)) { 376 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 377 __func__); 378 ecode = HAL_ESELFTEST; 379 goto bad; 380 } 381 382 /* Enable PCI core retry fix in software for Hainan and up */ 383 if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_VENICE) 384 OS_REG_SET_BIT(ah, AR_PCICFG, AR_PCICFG_RETRYFIXEN); 385 386 /* 387 * Set correct Baseband to analog shift 388 * setting to access analog chips. 389 */ 390 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 391 392 /* Read Radio Chip Rev Extract */ 393 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah); 394 395 rf = ath_hal_rfprobe(ah, &ecode); 396 if (rf == AH_NULL) 397 goto bad; 398 399 /* NB: silently accept anything in release code per Atheros */ 400 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 401 case AR_RAD5111_SREV_MAJOR: 402 case AR_RAD5112_SREV_MAJOR: 403 case AR_RAD2112_SREV_MAJOR: 404 case AR_RAD2111_SREV_MAJOR: 405 case AR_RAD2413_SREV_MAJOR: 406 case AR_RAD5413_SREV_MAJOR: 407 case AR_RAD5424_SREV_MAJOR: 408 break; 409 default: 410 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 411 /* 412 * When RF_Silent is used, the 413 * analog chip is reset. So when the system boots 414 * up with the radio switch off we cannot determine 415 * the RF chip rev. To workaround this check the 416 * mac+phy revs and if Hainan, set the radio rev 417 * to Derby. 418 */ 419 if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE && 420 AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN && 421 AH_PRIVATE(ah)->ah_phyRev == AR_PHYREV_HAINAN) { 422 AH_PRIVATE(ah)->ah_analog5GhzRev = AR_ANALOG5REV_HAINAN; 423 break; 424 } 425 if (IS_2413(ah)) { /* Griffin */ 426 AH_PRIVATE(ah)->ah_analog5GhzRev = 427 AR_RAD2413_SREV_MAJOR | 0x1; 428 break; 429 } 430 if (IS_5413(ah)) { /* Eagle */ 431 AH_PRIVATE(ah)->ah_analog5GhzRev = 432 AR_RAD5413_SREV_MAJOR | 0x2; 433 break; 434 } 435 if (IS_2425(ah) || IS_2417(ah)) {/* Swan or Nala */ 436 AH_PRIVATE(ah)->ah_analog5GhzRev = 437 AR_RAD5424_SREV_MAJOR | 0x2; 438 break; 439 } 440 } 441 #ifdef AH_DEBUG 442 HALDEBUG(ah, HAL_DEBUG_ANY, 443 "%s: 5G Radio Chip Rev 0x%02X is not supported by " 444 "this driver\n", 445 __func__, AH_PRIVATE(ah)->ah_analog5GhzRev); 446 ecode = HAL_ENOTSUPP; 447 goto bad; 448 #endif 449 } 450 if (IS_RAD5112_REV1(ah)) { 451 HALDEBUG(ah, HAL_DEBUG_ANY, 452 "%s: 5112 Rev 1 is not supported by this " 453 "driver (analog5GhzRev 0x%x)\n", __func__, 454 AH_PRIVATE(ah)->ah_analog5GhzRev); 455 ecode = HAL_ENOTSUPP; 456 goto bad; 457 } 458 459 val = OS_REG_READ(ah, AR_PCICFG); 460 val = MS(val, AR_PCICFG_EEPROM_SIZE); 461 if (val == 0) { 462 if (!AH_PRIVATE(ah)->ah_ispcie) { 463 HALDEBUG(ah, HAL_DEBUG_ANY, 464 "%s: unsupported EEPROM size %u (0x%x) found\n", 465 __func__, val, val); 466 ecode = HAL_EESIZE; 467 goto bad; 468 } 469 /* XXX AH_PRIVATE(ah)->ah_isPciExpress = AH_TRUE; */ 470 } else if (val != AR_PCICFG_EEPROM_SIZE_16K) { 471 if (AR_PCICFG_EEPROM_SIZE_FAILED == val) { 472 HALDEBUG(ah, HAL_DEBUG_ANY, 473 "%s: unsupported EEPROM size %u (0x%x) found\n", 474 __func__, val, val); 475 ecode = HAL_EESIZE; 476 goto bad; 477 } 478 HALDEBUG(ah, HAL_DEBUG_ANY, 479 "%s: EEPROM size = %d. Must be %d (16k).\n", 480 __func__, val, AR_PCICFG_EEPROM_SIZE_16K); 481 ecode = HAL_EESIZE; 482 goto bad; 483 } 484 ecode = ath_hal_legacyEepromAttach(ah); 485 if (ecode != HAL_OK) { 486 goto bad; 487 } 488 ahp->ah_isHb63 = IS_2425(ah) && ath_hal_eepromGetFlag(ah, AR_EEP_ISTALON); 489 490 /* 491 * If Bmode and AR5212, verify 2.4 analog exists 492 */ 493 if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) && 494 (AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD5111_SREV_MAJOR) { 495 /* 496 * Set correct Baseband to analog shift 497 * setting to access analog chips. 498 */ 499 OS_REG_WRITE(ah, AR_PHY(0), 0x00004007); 500 OS_DELAY(2000); 501 AH_PRIVATE(ah)->ah_analog2GhzRev = ar5212GetRadioRev(ah); 502 503 /* Set baseband for 5GHz chip */ 504 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 505 OS_DELAY(2000); 506 if ((AH_PRIVATE(ah)->ah_analog2GhzRev & 0xF0) != AR_RAD2111_SREV_MAJOR) { 507 HALDEBUG(ah, HAL_DEBUG_ANY, 508 "%s: 2G Radio Chip Rev 0x%02X is not " 509 "supported by this driver\n", __func__, 510 AH_PRIVATE(ah)->ah_analog2GhzRev); 511 ecode = HAL_ENOTSUPP; 512 goto bad; 513 } 514 } 515 516 ecode = ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, &eeval); 517 if (ecode != HAL_OK) { 518 HALDEBUG(ah, HAL_DEBUG_ANY, 519 "%s: cannot read regulatory domain from EEPROM\n", 520 __func__); 521 goto bad; 522 } 523 AH_PRIVATE(ah)->ah_currentRD = eeval; 524 /* XXX record serial number */ 525 526 /* 527 * Got everything we need now to setup the capabilities. 528 */ 529 if (!ar5212FillCapabilityInfo(ah)) { 530 HALDEBUG(ah, HAL_DEBUG_ANY, 531 "%s: failed ar5212FillCapabilityInfo\n", __func__); 532 ecode = HAL_EEREAD; 533 goto bad; 534 } 535 536 if (!rf->attach(ah, &ecode)) { 537 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 538 __func__, ecode); 539 goto bad; 540 } 541 /* 542 * Set noise floor adjust method; we arrange a 543 * direct call instead of thunking. 544 */ 545 AH_PRIVATE(ah)->ah_getNfAdjust = ahp->ah_rfHal->getNfAdjust; 546 547 /* Initialize gain ladder thermal calibration structure */ 548 ar5212InitializeGainValues(ah); 549 550 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 551 if (ecode != HAL_OK) { 552 HALDEBUG(ah, HAL_DEBUG_ANY, 553 "%s: error getting mac address from EEPROM\n", __func__); 554 goto bad; 555 } 556 557 ar5212AniSetup(ah); 558 /* Setup of Radar/AR structures happens in ath_hal_initchannels*/ 559 ar5212InitNfCalHistBuffer(ah); 560 561 /* XXX EAR stuff goes here */ 562 563 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 564 565 return ah; 566 567 bad: 568 if (ahp) 569 ar5212Detach((struct ath_hal *) ahp); 570 if (status) 571 *status = ecode; 572 return AH_NULL; 573 #undef AH_EEPROM_PROTECT 574 } 575 576 void 577 ar5212Detach(struct ath_hal *ah) 578 { 579 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__); 580 581 HALASSERT(ah != AH_NULL); 582 HALASSERT(ah->ah_magic == AR5212_MAGIC); 583 584 ar5212AniDetach(ah); 585 ar5212RfDetach(ah); 586 ar5212Disable(ah); 587 ar5212SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); 588 589 ath_hal_eepromDetach(ah); 590 ath_hal_free(ah); 591 } 592 593 HAL_BOOL 594 ar5212ChipTest(struct ath_hal *ah) 595 { 596 uint32_t regAddr[2] = { AR_STA_ID0, AR_PHY_BASE+(8 << 2) }; 597 uint32_t regHold[2]; 598 uint32_t patternData[4] = 599 { 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 }; 600 int i, j; 601 602 /* Test PHY & MAC registers */ 603 for (i = 0; i < 2; i++) { 604 uint32_t addr = regAddr[i]; 605 uint32_t wrData, rdData; 606 607 regHold[i] = OS_REG_READ(ah, addr); 608 for (j = 0; j < 0x100; j++) { 609 wrData = (j << 16) | j; 610 OS_REG_WRITE(ah, addr, wrData); 611 rdData = OS_REG_READ(ah, addr); 612 if (rdData != wrData) { 613 HALDEBUG(ah, HAL_DEBUG_ANY, 614 "%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 615 __func__, addr, wrData, rdData); 616 return AH_FALSE; 617 } 618 } 619 for (j = 0; j < 4; j++) { 620 wrData = patternData[j]; 621 OS_REG_WRITE(ah, addr, wrData); 622 rdData = OS_REG_READ(ah, addr); 623 if (wrData != rdData) { 624 HALDEBUG(ah, HAL_DEBUG_ANY, 625 "%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 626 __func__, addr, wrData, rdData); 627 return AH_FALSE; 628 } 629 } 630 OS_REG_WRITE(ah, regAddr[i], regHold[i]); 631 } 632 OS_DELAY(100); 633 return AH_TRUE; 634 } 635 636 /* 637 * Store the channel edges for the requested operational mode 638 */ 639 HAL_BOOL 640 ar5212GetChannelEdges(struct ath_hal *ah, 641 uint16_t flags, uint16_t *low, uint16_t *high) 642 { 643 if (flags & IEEE80211_CHAN_5GHZ) { 644 *low = 4915; 645 *high = 6100; 646 return AH_TRUE; 647 } 648 if ((flags & IEEE80211_CHAN_2GHZ) && 649 (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) || 650 ath_hal_eepromGetFlag(ah, AR_EEP_GMODE))) { 651 *low = 2312; 652 *high = 2732; 653 return AH_TRUE; 654 } 655 return AH_FALSE; 656 } 657 658 /* 659 * Disable PLL when in L0s as well as receiver clock when in L1. 660 * This power saving option must be enabled through the Serdes. 661 * 662 * Programming the Serdes must go through the same 288 bit serial shift 663 * register as the other analog registers. Hence the 9 writes. 664 * 665 * XXX Clean up the magic numbers. 666 */ 667 static void 668 ar5212ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore) 669 { 670 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 671 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 672 673 /* RX shut off when elecidle is asserted */ 674 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039); 675 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824); 676 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579); 677 678 /* Shut off PLL and CLKREQ active in L1 */ 679 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff); 680 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 681 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 682 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007); 683 684 /* Load the new settings */ 685 OS_REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 686 } 687 688 static void 689 ar5212DisablePCIE(struct ath_hal *ah) 690 { 691 /* NB: fill in for 9100 */ 692 } 693 694 /* 695 * Fill all software cached or static hardware state information. 696 * Return failure if capabilities are to come from EEPROM and 697 * cannot be read. 698 */ 699 HAL_BOOL 700 ar5212FillCapabilityInfo(struct ath_hal *ah) 701 { 702 #define AR_KEYTABLE_SIZE 128 703 #define IS_GRIFFIN_LITE(ah) \ 704 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_GRIFFIN && \ 705 AH_PRIVATE(ah)->ah_macRev == AR_SREV_GRIFFIN_LITE) 706 #define IS_COBRA(ah) \ 707 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_COBRA) 708 #define IS_2112(ah) \ 709 ((AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD2112_SREV_MAJOR) 710 711 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 712 HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 713 uint16_t capField, val; 714 715 /* Read the capability EEPROM location */ 716 if (ath_hal_eepromGet(ah, AR_EEP_OPCAP, &capField) != HAL_OK) { 717 HALDEBUG(ah, HAL_DEBUG_ANY, 718 "%s: unable to read caps from eeprom\n", __func__); 719 return AH_FALSE; 720 } 721 if (IS_2112(ah)) 722 ath_hal_eepromSet(ah, AR_EEP_AMODE, AH_FALSE); 723 if (capField == 0 && IS_GRIFFIN_LITE(ah)) { 724 /* 725 * For griffin-lite cards with unprogrammed capabilities. 726 */ 727 ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE); 728 ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE); 729 ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE); 730 ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE); 731 HALDEBUG(ah, HAL_DEBUG_ATTACH, 732 "%s: override caps for griffin-lite, now 0x%x (+!turbo)\n", 733 __func__, capField); 734 } 735 736 /* Modify reg domain on newer cards that need to work with older sw */ 737 if (ahpriv->ah_opmode != HAL_M_HOSTAP && 738 ahpriv->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) { 739 if (ahpriv->ah_currentRD == 0x64 || 740 ahpriv->ah_currentRD == 0x65) 741 ahpriv->ah_currentRD += 5; 742 else if (ahpriv->ah_currentRD == 0x41) 743 ahpriv->ah_currentRD = 0x43; 744 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: regdomain mapped to 0x%x\n", 745 __func__, ahpriv->ah_currentRD); 746 } 747 748 if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2417 || 749 AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2425) { 750 HALDEBUG(ah, HAL_DEBUG_ATTACH, 751 "%s: enable Bmode and disable turbo for Swan/Nala\n", 752 __func__); 753 ath_hal_eepromSet(ah, AR_EEP_BMODE, AH_TRUE); 754 ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE); 755 ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE); 756 ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE); 757 ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE); 758 } 759 760 /* Construct wireless mode from EEPROM */ 761 pCap->halWirelessModes = 0; 762 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) { 763 pCap->halWirelessModes |= HAL_MODE_11A; 764 if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO5DISABLE)) 765 pCap->halWirelessModes |= HAL_MODE_TURBO; 766 } 767 if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE)) 768 pCap->halWirelessModes |= HAL_MODE_11B; 769 if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE) && 770 ahpriv->ah_subvendorid != AR_SUBVENDOR_ID_NOG) { 771 pCap->halWirelessModes |= HAL_MODE_11G; 772 if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO2DISABLE)) 773 pCap->halWirelessModes |= HAL_MODE_108G; 774 } 775 776 pCap->halLow2GhzChan = 2312; 777 /* XXX 2417 too? */ 778 if (IS_RAD5112_ANY(ah) || IS_5413(ah) || IS_2425(ah) || IS_2417(ah)) 779 pCap->halHigh2GhzChan = 2500; 780 else 781 pCap->halHigh2GhzChan = 2732; 782 783 pCap->halLow5GhzChan = 4915; 784 pCap->halHigh5GhzChan = 6100; 785 786 pCap->halCipherCkipSupport = AH_FALSE; 787 pCap->halCipherTkipSupport = AH_TRUE; 788 pCap->halCipherAesCcmSupport = 789 (ath_hal_eepromGetFlag(ah, AR_EEP_AES) && 790 ((AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE) || 791 ((AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE) && 792 (AH_PRIVATE(ah)->ah_macRev >= AR_SREV_VERSION_OAHU)))); 793 794 pCap->halMicCkipSupport = AH_FALSE; 795 pCap->halMicTkipSupport = AH_TRUE; 796 pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 797 /* 798 * Starting with Griffin TX+RX mic keys can be combined 799 * in one key cache slot. 800 */ 801 if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_GRIFFIN) 802 pCap->halTkipMicTxRxKeySupport = AH_TRUE; 803 else 804 pCap->halTkipMicTxRxKeySupport = AH_FALSE; 805 pCap->halChanSpreadSupport = AH_TRUE; 806 pCap->halSleepAfterBeaconBroken = AH_TRUE; 807 808 if (ahpriv->ah_macRev > 1 || IS_COBRA(ah)) { 809 pCap->halCompressSupport = 810 ath_hal_eepromGetFlag(ah, AR_EEP_COMPRESS) && 811 (pCap->halWirelessModes & (HAL_MODE_11A|HAL_MODE_11G)) != 0; 812 pCap->halBurstSupport = ath_hal_eepromGetFlag(ah, AR_EEP_BURST); 813 pCap->halFastFramesSupport = 814 ath_hal_eepromGetFlag(ah, AR_EEP_FASTFRAME) && 815 (pCap->halWirelessModes & (HAL_MODE_11A|HAL_MODE_11G)) != 0; 816 pCap->halChapTuningSupport = AH_TRUE; 817 pCap->halTurboPrimeSupport = AH_TRUE; 818 } 819 pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G; 820 821 pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */ 822 pCap->halVEOLSupport = AH_TRUE; 823 pCap->halBssIdMaskSupport = AH_TRUE; 824 pCap->halMcastKeySrchSupport = AH_TRUE; 825 if ((ahpriv->ah_macVersion == AR_SREV_VERSION_VENICE && 826 ahpriv->ah_macRev == 8) || 827 ahpriv->ah_macVersion > AR_SREV_VERSION_VENICE) 828 pCap->halTsfAddSupport = AH_TRUE; 829 830 if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK) 831 pCap->halTotalQueues = val; 832 else 833 pCap->halTotalQueues = HAL_NUM_TX_QUEUES; 834 835 if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK) 836 pCap->halKeyCacheSize = val; 837 else 838 pCap->halKeyCacheSize = AR_KEYTABLE_SIZE; 839 840 pCap->halChanHalfRate = AH_TRUE; 841 pCap->halChanQuarterRate = AH_TRUE; 842 843 /* 844 * RSSI uses the combined field; some 11n NICs may use 845 * the control chain RSSI. 846 */ 847 pCap->halUseCombinedRadarRssi = AH_TRUE; 848 849 if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) && 850 ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) { 851 /* NB: enabled by default */ 852 ahpriv->ah_rfkillEnabled = AH_TRUE; 853 pCap->halRfSilentSupport = AH_TRUE; 854 } 855 856 /* NB: this is a guess, noone seems to know the answer */ 857 ahpriv->ah_rxornIsFatal = 858 (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_VENICE); 859 860 /* enable features that first appeared in Hainan */ 861 if ((AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE && 862 AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN) || 863 AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE) { 864 /* h/w phy counters */ 865 pCap->halHwPhyCounterSupport = AH_TRUE; 866 /* bssid match disable */ 867 pCap->halBssidMatchSupport = AH_TRUE; 868 } 869 870 pCap->halTstampPrecision = 15; 871 pCap->halIntrMask = HAL_INT_COMMON 872 | HAL_INT_RX 873 | HAL_INT_TX 874 | HAL_INT_FATAL 875 | HAL_INT_BNR 876 | HAL_INT_BMISC 877 ; 878 if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN) 879 pCap->halIntrMask &= ~HAL_INT_TBTT; 880 881 pCap->hal4kbSplitTransSupport = AH_TRUE; 882 pCap->halHasRxSelfLinkedTail = AH_TRUE; 883 884 return AH_TRUE; 885 #undef IS_COBRA 886 #undef IS_GRIFFIN_LITE 887 #undef AR_KEYTABLE_SIZE 888 } 889 890 static const char* 891 ar5212Probe(uint16_t vendorid, uint16_t devid) 892 { 893 if (vendorid == ATHEROS_VENDOR_ID || 894 vendorid == ATHEROS_3COM_VENDOR_ID || 895 vendorid == ATHEROS_3COM2_VENDOR_ID) { 896 switch (devid) { 897 case AR5212_FPGA: 898 return "Atheros 5212 (FPGA)"; 899 case AR5212_DEVID: 900 case AR5212_DEVID_IBM: 901 case AR5212_DEFAULT: 902 return "Atheros 5212"; 903 case AR5212_AR2413: 904 return "Atheros 2413"; 905 case AR5212_AR2417: 906 return "Atheros 2417"; 907 case AR5212_AR5413: 908 return "Atheros 5413"; 909 case AR5212_AR5424: 910 return "Atheros 5424/2424"; 911 } 912 } 913 return AH_NULL; 914 } 915 AH_CHIP(AR5212, ar5212Probe, ar5212Attach); 916