1 /* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19 #include "opt_ah.h" 20 21 #include "ah.h" 22 #include "ah_internal.h" 23 #include "ah_devid.h" 24 25 #include "ar5212/ar5212.h" 26 #include "ar5212/ar5212reg.h" 27 #include "ar5212/ar5212phy.h" 28 29 #define AH_5212_COMMON 30 #include "ar5212/ar5212.ini" 31 32 static void ar5212ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore); 33 static void ar5212DisablePCIE(struct ath_hal *ah); 34 35 static const struct ath_hal_private ar5212hal = {{ 36 .ah_magic = AR5212_MAGIC, 37 38 .ah_getRateTable = ar5212GetRateTable, 39 .ah_detach = ar5212Detach, 40 41 /* Reset Functions */ 42 .ah_reset = ar5212Reset, 43 .ah_phyDisable = ar5212PhyDisable, 44 .ah_disable = ar5212Disable, 45 .ah_configPCIE = ar5212ConfigPCIE, 46 .ah_disablePCIE = ar5212DisablePCIE, 47 .ah_setPCUConfig = ar5212SetPCUConfig, 48 .ah_perCalibration = ar5212PerCalibration, 49 .ah_perCalibrationN = ar5212PerCalibrationN, 50 .ah_resetCalValid = ar5212ResetCalValid, 51 .ah_setTxPowerLimit = ar5212SetTxPowerLimit, 52 .ah_getChanNoise = ath_hal_getChanNoise, 53 54 /* Transmit functions */ 55 .ah_updateTxTrigLevel = ar5212UpdateTxTrigLevel, 56 .ah_setupTxQueue = ar5212SetupTxQueue, 57 .ah_setTxQueueProps = ar5212SetTxQueueProps, 58 .ah_getTxQueueProps = ar5212GetTxQueueProps, 59 .ah_releaseTxQueue = ar5212ReleaseTxQueue, 60 .ah_resetTxQueue = ar5212ResetTxQueue, 61 .ah_getTxDP = ar5212GetTxDP, 62 .ah_setTxDP = ar5212SetTxDP, 63 .ah_numTxPending = ar5212NumTxPending, 64 .ah_startTxDma = ar5212StartTxDma, 65 .ah_stopTxDma = ar5212StopTxDma, 66 .ah_setupTxDesc = ar5212SetupTxDesc, 67 .ah_setupXTxDesc = ar5212SetupXTxDesc, 68 .ah_fillTxDesc = ar5212FillTxDesc, 69 .ah_procTxDesc = ar5212ProcTxDesc, 70 .ah_getTxIntrQueue = ar5212GetTxIntrQueue, 71 .ah_reqTxIntrDesc = ar5212IntrReqTxDesc, 72 .ah_getTxCompletionRates = ar5212GetTxCompletionRates, 73 74 /* RX Functions */ 75 .ah_getRxDP = ar5212GetRxDP, 76 .ah_setRxDP = ar5212SetRxDP, 77 .ah_enableReceive = ar5212EnableReceive, 78 .ah_stopDmaReceive = ar5212StopDmaReceive, 79 .ah_startPcuReceive = ar5212StartPcuReceive, 80 .ah_stopPcuReceive = ar5212StopPcuReceive, 81 .ah_setMulticastFilter = ar5212SetMulticastFilter, 82 .ah_setMulticastFilterIndex = ar5212SetMulticastFilterIndex, 83 .ah_clrMulticastFilterIndex = ar5212ClrMulticastFilterIndex, 84 .ah_getRxFilter = ar5212GetRxFilter, 85 .ah_setRxFilter = ar5212SetRxFilter, 86 .ah_setupRxDesc = ar5212SetupRxDesc, 87 .ah_procRxDesc = ar5212ProcRxDesc, 88 .ah_rxMonitor = ar5212RxMonitor, 89 .ah_aniPoll = ar5212AniPoll, 90 .ah_procMibEvent = ar5212ProcessMibIntr, 91 92 /* Misc Functions */ 93 .ah_getCapability = ar5212GetCapability, 94 .ah_setCapability = ar5212SetCapability, 95 .ah_getDiagState = ar5212GetDiagState, 96 .ah_getMacAddress = ar5212GetMacAddress, 97 .ah_setMacAddress = ar5212SetMacAddress, 98 .ah_getBssIdMask = ar5212GetBssIdMask, 99 .ah_setBssIdMask = ar5212SetBssIdMask, 100 .ah_setRegulatoryDomain = ar5212SetRegulatoryDomain, 101 .ah_setLedState = ar5212SetLedState, 102 .ah_writeAssocid = ar5212WriteAssocid, 103 .ah_gpioCfgInput = ar5212GpioCfgInput, 104 .ah_gpioCfgOutput = ar5212GpioCfgOutput, 105 .ah_gpioGet = ar5212GpioGet, 106 .ah_gpioSet = ar5212GpioSet, 107 .ah_gpioSetIntr = ar5212GpioSetIntr, 108 .ah_getTsf32 = ar5212GetTsf32, 109 .ah_getTsf64 = ar5212GetTsf64, 110 .ah_resetTsf = ar5212ResetTsf, 111 .ah_detectCardPresent = ar5212DetectCardPresent, 112 .ah_updateMibCounters = ar5212UpdateMibCounters, 113 .ah_getRfGain = ar5212GetRfgain, 114 .ah_getDefAntenna = ar5212GetDefAntenna, 115 .ah_setDefAntenna = ar5212SetDefAntenna, 116 .ah_getAntennaSwitch = ar5212GetAntennaSwitch, 117 .ah_setAntennaSwitch = ar5212SetAntennaSwitch, 118 .ah_setSifsTime = ar5212SetSifsTime, 119 .ah_getSifsTime = ar5212GetSifsTime, 120 .ah_setSlotTime = ar5212SetSlotTime, 121 .ah_getSlotTime = ar5212GetSlotTime, 122 .ah_setAckTimeout = ar5212SetAckTimeout, 123 .ah_getAckTimeout = ar5212GetAckTimeout, 124 .ah_setAckCTSRate = ar5212SetAckCTSRate, 125 .ah_getAckCTSRate = ar5212GetAckCTSRate, 126 .ah_setCTSTimeout = ar5212SetCTSTimeout, 127 .ah_getCTSTimeout = ar5212GetCTSTimeout, 128 .ah_setDecompMask = ar5212SetDecompMask, 129 .ah_setCoverageClass = ar5212SetCoverageClass, 130 .ah_setQuiet = ar5212SetQuiet, 131 132 /* DFS Functions */ 133 .ah_enableDfs = ar5212EnableDfs, 134 .ah_getDfsThresh = ar5212GetDfsThresh, 135 136 /* Key Cache Functions */ 137 .ah_getKeyCacheSize = ar5212GetKeyCacheSize, 138 .ah_resetKeyCacheEntry = ar5212ResetKeyCacheEntry, 139 .ah_isKeyCacheEntryValid = ar5212IsKeyCacheEntryValid, 140 .ah_setKeyCacheEntry = ar5212SetKeyCacheEntry, 141 .ah_setKeyCacheEntryMac = ar5212SetKeyCacheEntryMac, 142 143 /* Power Management Functions */ 144 .ah_setPowerMode = ar5212SetPowerMode, 145 .ah_getPowerMode = ar5212GetPowerMode, 146 147 /* Beacon Functions */ 148 .ah_setBeaconTimers = ar5212SetBeaconTimers, 149 .ah_beaconInit = ar5212BeaconInit, 150 .ah_setStationBeaconTimers = ar5212SetStaBeaconTimers, 151 .ah_resetStationBeaconTimers = ar5212ResetStaBeaconTimers, 152 153 /* Interrupt Functions */ 154 .ah_isInterruptPending = ar5212IsInterruptPending, 155 .ah_getPendingInterrupts = ar5212GetPendingInterrupts, 156 .ah_getInterrupts = ar5212GetInterrupts, 157 .ah_setInterrupts = ar5212SetInterrupts }, 158 159 .ah_getChannelEdges = ar5212GetChannelEdges, 160 .ah_getWirelessModes = ar5212GetWirelessModes, 161 .ah_eepromRead = ar5212EepromRead, 162 #ifdef AH_SUPPORT_WRITE_EEPROM 163 .ah_eepromWrite = ar5212EepromWrite, 164 #endif 165 .ah_getChipPowerLimits = ar5212GetChipPowerLimits, 166 }; 167 168 uint32_t 169 ar5212GetRadioRev(struct ath_hal *ah) 170 { 171 uint32_t val; 172 int i; 173 174 /* Read Radio Chip Rev Extract */ 175 OS_REG_WRITE(ah, AR_PHY(0x34), 0x00001c16); 176 for (i = 0; i < 8; i++) 177 OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000); 178 val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; 179 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 180 return ath_hal_reverseBits(val, 8); 181 } 182 183 static void 184 ar5212AniSetup(struct ath_hal *ah) 185 { 186 static const struct ar5212AniParams aniparams = { 187 .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 188 .totalSizeDesired = { -55, -55, -55, -55, -62 }, 189 .coarseHigh = { -14, -14, -14, -14, -12 }, 190 .coarseLow = { -64, -64, -64, -64, -70 }, 191 .firpwr = { -78, -78, -78, -78, -80 }, 192 .maxSpurImmunityLevel = 2, /* NB: depends on chip rev */ 193 .cycPwrThr1 = { 2, 4, 6, 8, 10, 12, 14, 16 }, 194 .maxFirstepLevel = 2, /* levels 0..2 */ 195 .firstep = { 0, 4, 8 }, 196 .ofdmTrigHigh = 500, 197 .ofdmTrigLow = 200, 198 .cckTrigHigh = 200, 199 .cckTrigLow = 100, 200 .rssiThrHigh = 40, 201 .rssiThrLow = 7, 202 .period = 100, 203 }; 204 if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN) { 205 struct ar5212AniParams tmp; 206 OS_MEMCPY(&tmp, &aniparams, sizeof(struct ar5212AniParams)); 207 tmp.maxSpurImmunityLevel = 7; /* Venice and earlier */ 208 ar5212AniAttach(ah, &tmp, &tmp, AH_TRUE); 209 } else 210 ar5212AniAttach(ah, &aniparams, &aniparams, AH_TRUE); 211 212 /* Set overridable ANI methods */ 213 AH5212(ah)->ah_aniControl = ar5212AniControl; 214 } 215 216 /* 217 * Attach for an AR5212 part. 218 */ 219 void 220 ar5212InitState(struct ath_hal_5212 *ahp, uint16_t devid, HAL_SOFTC sc, 221 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status) 222 { 223 #define N(a) (sizeof(a)/sizeof(a[0])) 224 static const uint8_t defbssidmask[IEEE80211_ADDR_LEN] = 225 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 226 struct ath_hal *ah; 227 228 ah = &ahp->ah_priv.h; 229 /* set initial values */ 230 OS_MEMCPY(&ahp->ah_priv, &ar5212hal, sizeof(struct ath_hal_private)); 231 ah->ah_sc = sc; 232 ah->ah_st = st; 233 ah->ah_sh = sh; 234 235 ah->ah_devid = devid; /* NB: for alq */ 236 AH_PRIVATE(ah)->ah_devid = devid; 237 AH_PRIVATE(ah)->ah_subvendorid = 0; /* XXX */ 238 239 AH_PRIVATE(ah)->ah_powerLimit = MAX_RATE_POWER; 240 AH_PRIVATE(ah)->ah_tpScale = HAL_TP_SCALE_MAX; /* no scaling */ 241 242 ahp->ah_antControl = HAL_ANT_VARIABLE; 243 ahp->ah_diversity = AH_TRUE; 244 ahp->ah_bIQCalibration = AH_FALSE; 245 /* 246 * Enable MIC handling. 247 */ 248 ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE; 249 ahp->ah_rssiThr = INIT_RSSI_THR; 250 ahp->ah_tpcEnabled = AH_FALSE; /* disabled by default */ 251 ahp->ah_phyPowerOn = AH_FALSE; 252 ahp->ah_macTPC = SM(MAX_RATE_POWER, AR_TPC_ACK) 253 | SM(MAX_RATE_POWER, AR_TPC_CTS) 254 | SM(MAX_RATE_POWER, AR_TPC_CHIRP); 255 ahp->ah_beaconInterval = 100; /* XXX [20..1000] */ 256 ahp->ah_enable32kHzClock = DONT_USE_32KHZ;/* XXX */ 257 ahp->ah_slottime = (u_int) -1; 258 ahp->ah_acktimeout = (u_int) -1; 259 ahp->ah_ctstimeout = (u_int) -1; 260 ahp->ah_sifstime = (u_int) -1; 261 ahp->ah_txTrigLev = INIT_TX_FIFO_THRESHOLD, 262 ahp->ah_maxTxTrigLev = MAX_TX_FIFO_THRESHOLD, 263 264 OS_MEMCPY(&ahp->ah_bssidmask, defbssidmask, IEEE80211_ADDR_LEN); 265 #undef N 266 } 267 268 /* 269 * Validate MAC version and revision. 270 */ 271 static HAL_BOOL 272 ar5212IsMacSupported(uint8_t macVersion, uint8_t macRev) 273 { 274 #define N(a) (sizeof(a)/sizeof(a[0])) 275 static const struct { 276 uint8_t version; 277 uint8_t revMin, revMax; 278 } macs[] = { 279 { AR_SREV_VERSION_VENICE, 280 AR_SREV_D2PLUS, AR_SREV_REVISION_MAX }, 281 { AR_SREV_VERSION_GRIFFIN, 282 AR_SREV_D2PLUS, AR_SREV_REVISION_MAX }, 283 { AR_SREV_5413, 284 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 285 { AR_SREV_5424, 286 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 287 { AR_SREV_2425, 288 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 289 { AR_SREV_2417, 290 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 291 }; 292 int i; 293 294 for (i = 0; i < N(macs); i++) 295 if (macs[i].version == macVersion && 296 macs[i].revMin <= macRev && macRev <= macs[i].revMax) 297 return AH_TRUE; 298 return AH_FALSE; 299 #undef N 300 } 301 302 /* 303 * Attach for an AR5212 part. 304 */ 305 static struct ath_hal * 306 ar5212Attach(uint16_t devid, HAL_SOFTC sc, 307 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 308 HAL_STATUS *status) 309 { 310 #define AH_EEPROM_PROTECT(ah) \ 311 (AH_PRIVATE(ah)->ah_ispcie)? AR_EEPROM_PROTECT_PCIE : AR_EEPROM_PROTECT) 312 struct ath_hal_5212 *ahp; 313 struct ath_hal *ah; 314 struct ath_hal_rf *rf; 315 uint32_t val; 316 uint16_t eeval; 317 HAL_STATUS ecode; 318 319 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 320 __func__, sc, (void*) st, (void*) sh); 321 322 /* NB: memory is returned zero'd */ 323 ahp = ath_hal_malloc(sizeof (struct ath_hal_5212)); 324 if (ahp == AH_NULL) { 325 HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 326 "%s: cannot allocate memory for state block\n", __func__); 327 *status = HAL_ENOMEM; 328 return AH_NULL; 329 } 330 ar5212InitState(ahp, devid, sc, st, sh, status); 331 ah = &ahp->ah_priv.h; 332 333 if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 334 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", 335 __func__); 336 ecode = HAL_EIO; 337 goto bad; 338 } 339 /* Read Revisions from Chips before taking out of reset */ 340 val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID; 341 AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S; 342 AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION; 343 AH_PRIVATE(ah)->ah_ispcie = IS_5424(ah) || IS_2425(ah); 344 345 if (!ar5212IsMacSupported(AH_PRIVATE(ah)->ah_macVersion, AH_PRIVATE(ah)->ah_macRev)) { 346 HALDEBUG(ah, HAL_DEBUG_ANY, 347 "%s: Mac Chip Rev 0x%02x.%x not supported\n" , 348 __func__, AH_PRIVATE(ah)->ah_macVersion, 349 AH_PRIVATE(ah)->ah_macRev); 350 ecode = HAL_ENOTSUPP; 351 goto bad; 352 } 353 354 /* setup common ini data; rf backends handle remainder */ 355 HAL_INI_INIT(&ahp->ah_ini_modes, ar5212Modes, 6); 356 HAL_INI_INIT(&ahp->ah_ini_common, ar5212Common, 2); 357 358 if (!ar5212ChipReset(ah, AH_NULL)) { /* reset chip */ 359 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 360 ecode = HAL_EIO; 361 goto bad; 362 } 363 364 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 365 366 if (AH_PRIVATE(ah)->ah_ispcie) { 367 /* XXX: build flag to disable this? */ 368 ath_hal_configPCIE(ah, AH_FALSE); 369 } 370 371 if (!ar5212ChipTest(ah)) { 372 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 373 __func__); 374 ecode = HAL_ESELFTEST; 375 goto bad; 376 } 377 378 /* Enable PCI core retry fix in software for Hainan and up */ 379 if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_VENICE) 380 OS_REG_SET_BIT(ah, AR_PCICFG, AR_PCICFG_RETRYFIXEN); 381 382 /* 383 * Set correct Baseband to analog shift 384 * setting to access analog chips. 385 */ 386 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 387 388 /* Read Radio Chip Rev Extract */ 389 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah); 390 391 rf = ath_hal_rfprobe(ah, &ecode); 392 if (rf == AH_NULL) 393 goto bad; 394 395 /* NB: silently accept anything in release code per Atheros */ 396 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 397 case AR_RAD5111_SREV_MAJOR: 398 case AR_RAD5112_SREV_MAJOR: 399 case AR_RAD2112_SREV_MAJOR: 400 case AR_RAD2111_SREV_MAJOR: 401 case AR_RAD2413_SREV_MAJOR: 402 case AR_RAD5413_SREV_MAJOR: 403 case AR_RAD5424_SREV_MAJOR: 404 break; 405 default: 406 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 407 /* 408 * When RF_Silent is used, the 409 * analog chip is reset. So when the system boots 410 * up with the radio switch off we cannot determine 411 * the RF chip rev. To workaround this check the 412 * mac+phy revs and if Hainan, set the radio rev 413 * to Derby. 414 */ 415 if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE && 416 AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN && 417 AH_PRIVATE(ah)->ah_phyRev == AR_PHYREV_HAINAN) { 418 AH_PRIVATE(ah)->ah_analog5GhzRev = AR_ANALOG5REV_HAINAN; 419 break; 420 } 421 if (IS_2413(ah)) { /* Griffin */ 422 AH_PRIVATE(ah)->ah_analog5GhzRev = 423 AR_RAD2413_SREV_MAJOR | 0x1; 424 break; 425 } 426 if (IS_5413(ah)) { /* Eagle */ 427 AH_PRIVATE(ah)->ah_analog5GhzRev = 428 AR_RAD5413_SREV_MAJOR | 0x2; 429 break; 430 } 431 if (IS_2425(ah) || IS_2417(ah)) {/* Swan or Nala */ 432 AH_PRIVATE(ah)->ah_analog5GhzRev = 433 AR_RAD5424_SREV_MAJOR | 0x2; 434 break; 435 } 436 } 437 #ifdef AH_DEBUG 438 HALDEBUG(ah, HAL_DEBUG_ANY, 439 "%s: 5G Radio Chip Rev 0x%02X is not supported by " 440 "this driver\n", 441 __func__, AH_PRIVATE(ah)->ah_analog5GhzRev); 442 ecode = HAL_ENOTSUPP; 443 goto bad; 444 #endif 445 } 446 if (IS_RAD5112_REV1(ah)) { 447 HALDEBUG(ah, HAL_DEBUG_ANY, 448 "%s: 5112 Rev 1 is not supported by this " 449 "driver (analog5GhzRev 0x%x)\n", __func__, 450 AH_PRIVATE(ah)->ah_analog5GhzRev); 451 ecode = HAL_ENOTSUPP; 452 goto bad; 453 } 454 455 val = OS_REG_READ(ah, AR_PCICFG); 456 val = MS(val, AR_PCICFG_EEPROM_SIZE); 457 if (val == 0) { 458 if (!AH_PRIVATE(ah)->ah_ispcie) { 459 HALDEBUG(ah, HAL_DEBUG_ANY, 460 "%s: unsupported EEPROM size %u (0x%x) found\n", 461 __func__, val, val); 462 ecode = HAL_EESIZE; 463 goto bad; 464 } 465 /* XXX AH_PRIVATE(ah)->ah_isPciExpress = AH_TRUE; */ 466 } else if (val != AR_PCICFG_EEPROM_SIZE_16K) { 467 if (AR_PCICFG_EEPROM_SIZE_FAILED == val) { 468 HALDEBUG(ah, HAL_DEBUG_ANY, 469 "%s: unsupported EEPROM size %u (0x%x) found\n", 470 __func__, val, val); 471 ecode = HAL_EESIZE; 472 goto bad; 473 } 474 HALDEBUG(ah, HAL_DEBUG_ANY, 475 "%s: EEPROM size = %d. Must be %d (16k).\n", 476 __func__, val, AR_PCICFG_EEPROM_SIZE_16K); 477 ecode = HAL_EESIZE; 478 goto bad; 479 } 480 ecode = ath_hal_legacyEepromAttach(ah); 481 if (ecode != HAL_OK) { 482 goto bad; 483 } 484 ahp->ah_isHb63 = IS_2425(ah) && ath_hal_eepromGetFlag(ah, AR_EEP_ISTALON); 485 486 /* 487 * If Bmode and AR5212, verify 2.4 analog exists 488 */ 489 if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) && 490 (AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD5111_SREV_MAJOR) { 491 /* 492 * Set correct Baseband to analog shift 493 * setting to access analog chips. 494 */ 495 OS_REG_WRITE(ah, AR_PHY(0), 0x00004007); 496 OS_DELAY(2000); 497 AH_PRIVATE(ah)->ah_analog2GhzRev = ar5212GetRadioRev(ah); 498 499 /* Set baseband for 5GHz chip */ 500 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 501 OS_DELAY(2000); 502 if ((AH_PRIVATE(ah)->ah_analog2GhzRev & 0xF0) != AR_RAD2111_SREV_MAJOR) { 503 HALDEBUG(ah, HAL_DEBUG_ANY, 504 "%s: 2G Radio Chip Rev 0x%02X is not " 505 "supported by this driver\n", __func__, 506 AH_PRIVATE(ah)->ah_analog2GhzRev); 507 ecode = HAL_ENOTSUPP; 508 goto bad; 509 } 510 } 511 512 ecode = ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, &eeval); 513 if (ecode != HAL_OK) { 514 HALDEBUG(ah, HAL_DEBUG_ANY, 515 "%s: cannot read regulatory domain from EEPROM\n", 516 __func__); 517 goto bad; 518 } 519 AH_PRIVATE(ah)->ah_currentRD = eeval; 520 /* XXX record serial number */ 521 522 /* 523 * Got everything we need now to setup the capabilities. 524 */ 525 if (!ar5212FillCapabilityInfo(ah)) { 526 HALDEBUG(ah, HAL_DEBUG_ANY, 527 "%s: failed ar5212FillCapabilityInfo\n", __func__); 528 ecode = HAL_EEREAD; 529 goto bad; 530 } 531 532 if (!rf->attach(ah, &ecode)) { 533 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 534 __func__, ecode); 535 goto bad; 536 } 537 /* 538 * Set noise floor adjust method; we arrange a 539 * direct call instead of thunking. 540 */ 541 AH_PRIVATE(ah)->ah_getNfAdjust = ahp->ah_rfHal->getNfAdjust; 542 543 /* Initialize gain ladder thermal calibration structure */ 544 ar5212InitializeGainValues(ah); 545 546 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 547 if (ecode != HAL_OK) { 548 HALDEBUG(ah, HAL_DEBUG_ANY, 549 "%s: error getting mac address from EEPROM\n", __func__); 550 goto bad; 551 } 552 553 ar5212AniSetup(ah); 554 /* Setup of Radar/AR structures happens in ath_hal_initchannels*/ 555 ar5212InitNfCalHistBuffer(ah); 556 557 /* XXX EAR stuff goes here */ 558 559 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 560 561 return ah; 562 563 bad: 564 if (ahp) 565 ar5212Detach((struct ath_hal *) ahp); 566 if (status) 567 *status = ecode; 568 return AH_NULL; 569 #undef AH_EEPROM_PROTECT 570 } 571 572 void 573 ar5212Detach(struct ath_hal *ah) 574 { 575 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__); 576 577 HALASSERT(ah != AH_NULL); 578 HALASSERT(ah->ah_magic == AR5212_MAGIC); 579 580 ar5212AniDetach(ah); 581 ar5212RfDetach(ah); 582 ar5212Disable(ah); 583 ar5212SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); 584 585 ath_hal_eepromDetach(ah); 586 ath_hal_free(ah); 587 } 588 589 HAL_BOOL 590 ar5212ChipTest(struct ath_hal *ah) 591 { 592 uint32_t regAddr[2] = { AR_STA_ID0, AR_PHY_BASE+(8 << 2) }; 593 uint32_t regHold[2]; 594 uint32_t patternData[4] = 595 { 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 }; 596 int i, j; 597 598 /* Test PHY & MAC registers */ 599 for (i = 0; i < 2; i++) { 600 uint32_t addr = regAddr[i]; 601 uint32_t wrData, rdData; 602 603 regHold[i] = OS_REG_READ(ah, addr); 604 for (j = 0; j < 0x100; j++) { 605 wrData = (j << 16) | j; 606 OS_REG_WRITE(ah, addr, wrData); 607 rdData = OS_REG_READ(ah, addr); 608 if (rdData != wrData) { 609 HALDEBUG(ah, HAL_DEBUG_ANY, 610 "%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 611 __func__, addr, wrData, rdData); 612 return AH_FALSE; 613 } 614 } 615 for (j = 0; j < 4; j++) { 616 wrData = patternData[j]; 617 OS_REG_WRITE(ah, addr, wrData); 618 rdData = OS_REG_READ(ah, addr); 619 if (wrData != rdData) { 620 HALDEBUG(ah, HAL_DEBUG_ANY, 621 "%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 622 __func__, addr, wrData, rdData); 623 return AH_FALSE; 624 } 625 } 626 OS_REG_WRITE(ah, regAddr[i], regHold[i]); 627 } 628 OS_DELAY(100); 629 return AH_TRUE; 630 } 631 632 /* 633 * Store the channel edges for the requested operational mode 634 */ 635 HAL_BOOL 636 ar5212GetChannelEdges(struct ath_hal *ah, 637 uint16_t flags, uint16_t *low, uint16_t *high) 638 { 639 if (flags & IEEE80211_CHAN_5GHZ) { 640 *low = 4915; 641 *high = 6100; 642 return AH_TRUE; 643 } 644 if ((flags & IEEE80211_CHAN_2GHZ) && 645 (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) || 646 ath_hal_eepromGetFlag(ah, AR_EEP_GMODE))) { 647 *low = 2312; 648 *high = 2732; 649 return AH_TRUE; 650 } 651 return AH_FALSE; 652 } 653 654 /* 655 * Disable PLL when in L0s as well as receiver clock when in L1. 656 * This power saving option must be enabled through the Serdes. 657 * 658 * Programming the Serdes must go through the same 288 bit serial shift 659 * register as the other analog registers. Hence the 9 writes. 660 * 661 * XXX Clean up the magic numbers. 662 */ 663 static void 664 ar5212ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore) 665 { 666 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 667 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 668 669 /* RX shut off when elecidle is asserted */ 670 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039); 671 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824); 672 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579); 673 674 /* Shut off PLL and CLKREQ active in L1 */ 675 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff); 676 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 677 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 678 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007); 679 680 /* Load the new settings */ 681 OS_REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 682 } 683 684 static void 685 ar5212DisablePCIE(struct ath_hal *ah) 686 { 687 /* NB: fill in for 9100 */ 688 } 689 690 /* 691 * Fill all software cached or static hardware state information. 692 * Return failure if capabilities are to come from EEPROM and 693 * cannot be read. 694 */ 695 HAL_BOOL 696 ar5212FillCapabilityInfo(struct ath_hal *ah) 697 { 698 #define AR_KEYTABLE_SIZE 128 699 #define IS_GRIFFIN_LITE(ah) \ 700 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_GRIFFIN && \ 701 AH_PRIVATE(ah)->ah_macRev == AR_SREV_GRIFFIN_LITE) 702 #define IS_COBRA(ah) \ 703 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_COBRA) 704 #define IS_2112(ah) \ 705 ((AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD2112_SREV_MAJOR) 706 707 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 708 HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 709 uint16_t capField, val; 710 711 /* Read the capability EEPROM location */ 712 if (ath_hal_eepromGet(ah, AR_EEP_OPCAP, &capField) != HAL_OK) { 713 HALDEBUG(ah, HAL_DEBUG_ANY, 714 "%s: unable to read caps from eeprom\n", __func__); 715 return AH_FALSE; 716 } 717 if (IS_2112(ah)) 718 ath_hal_eepromSet(ah, AR_EEP_AMODE, AH_FALSE); 719 if (capField == 0 && IS_GRIFFIN_LITE(ah)) { 720 /* 721 * For griffin-lite cards with unprogrammed capabilities. 722 */ 723 ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE); 724 ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE); 725 ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE); 726 ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE); 727 HALDEBUG(ah, HAL_DEBUG_ATTACH, 728 "%s: override caps for griffin-lite, now 0x%x (+!turbo)\n", 729 __func__, capField); 730 } 731 732 /* Modify reg domain on newer cards that need to work with older sw */ 733 if (ahpriv->ah_opmode != HAL_M_HOSTAP && 734 ahpriv->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) { 735 if (ahpriv->ah_currentRD == 0x64 || 736 ahpriv->ah_currentRD == 0x65) 737 ahpriv->ah_currentRD += 5; 738 else if (ahpriv->ah_currentRD == 0x41) 739 ahpriv->ah_currentRD = 0x43; 740 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: regdomain mapped to 0x%x\n", 741 __func__, ahpriv->ah_currentRD); 742 } 743 744 if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2417 || 745 AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2425) { 746 HALDEBUG(ah, HAL_DEBUG_ATTACH, 747 "%s: enable Bmode and disable turbo for Swan/Nala\n", 748 __func__); 749 ath_hal_eepromSet(ah, AR_EEP_BMODE, AH_TRUE); 750 ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE); 751 ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE); 752 ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE); 753 ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE); 754 } 755 756 /* Construct wireless mode from EEPROM */ 757 pCap->halWirelessModes = 0; 758 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) { 759 pCap->halWirelessModes |= HAL_MODE_11A; 760 if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO5DISABLE)) 761 pCap->halWirelessModes |= HAL_MODE_TURBO; 762 } 763 if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE)) 764 pCap->halWirelessModes |= HAL_MODE_11B; 765 if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE) && 766 ahpriv->ah_subvendorid != AR_SUBVENDOR_ID_NOG) { 767 pCap->halWirelessModes |= HAL_MODE_11G; 768 if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO2DISABLE)) 769 pCap->halWirelessModes |= HAL_MODE_108G; 770 } 771 772 pCap->halLow2GhzChan = 2312; 773 /* XXX 2417 too? */ 774 if (IS_RAD5112_ANY(ah) || IS_5413(ah) || IS_2425(ah) || IS_2417(ah)) 775 pCap->halHigh2GhzChan = 2500; 776 else 777 pCap->halHigh2GhzChan = 2732; 778 779 pCap->halLow5GhzChan = 4915; 780 pCap->halHigh5GhzChan = 6100; 781 782 pCap->halCipherCkipSupport = AH_FALSE; 783 pCap->halCipherTkipSupport = AH_TRUE; 784 pCap->halCipherAesCcmSupport = 785 (ath_hal_eepromGetFlag(ah, AR_EEP_AES) && 786 ((AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE) || 787 ((AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE) && 788 (AH_PRIVATE(ah)->ah_macRev >= AR_SREV_VERSION_OAHU)))); 789 790 pCap->halMicCkipSupport = AH_FALSE; 791 pCap->halMicTkipSupport = AH_TRUE; 792 pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 793 /* 794 * Starting with Griffin TX+RX mic keys can be combined 795 * in one key cache slot. 796 */ 797 if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_GRIFFIN) 798 pCap->halTkipMicTxRxKeySupport = AH_TRUE; 799 else 800 pCap->halTkipMicTxRxKeySupport = AH_FALSE; 801 pCap->halChanSpreadSupport = AH_TRUE; 802 pCap->halSleepAfterBeaconBroken = AH_TRUE; 803 804 if (ahpriv->ah_macRev > 1 || IS_COBRA(ah)) { 805 pCap->halCompressSupport = 806 ath_hal_eepromGetFlag(ah, AR_EEP_COMPRESS) && 807 (pCap->halWirelessModes & (HAL_MODE_11A|HAL_MODE_11G)) != 0; 808 pCap->halBurstSupport = ath_hal_eepromGetFlag(ah, AR_EEP_BURST); 809 pCap->halFastFramesSupport = 810 ath_hal_eepromGetFlag(ah, AR_EEP_FASTFRAME) && 811 (pCap->halWirelessModes & (HAL_MODE_11A|HAL_MODE_11G)) != 0; 812 pCap->halChapTuningSupport = AH_TRUE; 813 pCap->halTurboPrimeSupport = AH_TRUE; 814 } 815 pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G; 816 817 pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */ 818 pCap->halVEOLSupport = AH_TRUE; 819 pCap->halBssIdMaskSupport = AH_TRUE; 820 pCap->halMcastKeySrchSupport = AH_TRUE; 821 if ((ahpriv->ah_macVersion == AR_SREV_VERSION_VENICE && 822 ahpriv->ah_macRev == 8) || 823 ahpriv->ah_macVersion > AR_SREV_VERSION_VENICE) 824 pCap->halTsfAddSupport = AH_TRUE; 825 826 if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK) 827 pCap->halTotalQueues = val; 828 else 829 pCap->halTotalQueues = HAL_NUM_TX_QUEUES; 830 831 if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK) 832 pCap->halKeyCacheSize = val; 833 else 834 pCap->halKeyCacheSize = AR_KEYTABLE_SIZE; 835 836 pCap->halChanHalfRate = AH_TRUE; 837 pCap->halChanQuarterRate = AH_TRUE; 838 839 if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) && 840 ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) { 841 /* NB: enabled by default */ 842 ahpriv->ah_rfkillEnabled = AH_TRUE; 843 pCap->halRfSilentSupport = AH_TRUE; 844 } 845 846 /* NB: this is a guess, noone seems to know the answer */ 847 ahpriv->ah_rxornIsFatal = 848 (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_VENICE); 849 850 /* enable features that first appeared in Hainan */ 851 if ((AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE && 852 AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN) || 853 AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE) { 854 /* h/w phy counters */ 855 pCap->halHwPhyCounterSupport = AH_TRUE; 856 /* bssid match disable */ 857 pCap->halBssidMatchSupport = AH_TRUE; 858 } 859 860 pCap->halTstampPrecision = 15; 861 pCap->halIntrMask = HAL_INT_COMMON 862 | HAL_INT_RX 863 | HAL_INT_TX 864 | HAL_INT_FATAL 865 | HAL_INT_BNR 866 | HAL_INT_BMISC 867 ; 868 if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN) 869 pCap->halIntrMask &= ~HAL_INT_TBTT; 870 871 pCap->hal4kbSplitTransSupport = AH_TRUE; 872 pCap->halHasRxSelfLinkedTail = AH_TRUE; 873 874 return AH_TRUE; 875 #undef IS_COBRA 876 #undef IS_GRIFFIN_LITE 877 #undef AR_KEYTABLE_SIZE 878 } 879 880 static const char* 881 ar5212Probe(uint16_t vendorid, uint16_t devid) 882 { 883 if (vendorid == ATHEROS_VENDOR_ID || 884 vendorid == ATHEROS_3COM_VENDOR_ID || 885 vendorid == ATHEROS_3COM2_VENDOR_ID) { 886 switch (devid) { 887 case AR5212_FPGA: 888 return "Atheros 5212 (FPGA)"; 889 case AR5212_DEVID: 890 case AR5212_DEVID_IBM: 891 case AR5212_DEFAULT: 892 return "Atheros 5212"; 893 case AR5212_AR2413: 894 return "Atheros 2413"; 895 case AR5212_AR2417: 896 return "Atheros 2417"; 897 case AR5212_AR5413: 898 return "Atheros 5413"; 899 case AR5212_AR5424: 900 return "Atheros 5424/2424"; 901 } 902 } 903 return AH_NULL; 904 } 905 AH_CHIP(AR5212, ar5212Probe, ar5212Attach); 906