1 /*- 2 * SPDX-License-Identifier: ISC 3 * 4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 5 * Copyright (c) 2002-2008 Atheros Communications, Inc. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 * 19 * $FreeBSD$ 20 */ 21 #ifndef _ATH_AR5212_H_ 22 #define _ATH_AR5212_H_ 23 24 #include "ah_eeprom.h" 25 26 #define AR5212_MAGIC 0x19541014 27 28 /* DCU Transmit Filter macros */ 29 #define CALC_MMR(dcu, idx) \ 30 ( (4 * dcu) + (idx < 32 ? 0 : (idx < 64 ? 1 : (idx < 96 ? 2 : 3))) ) 31 #define TXBLK_FROM_MMR(mmr) \ 32 (AR_D_TXBLK_BASE + ((mmr & 0x1f) << 6) + ((mmr & 0x20) >> 3)) 33 #define CALC_TXBLK_ADDR(dcu, idx) (TXBLK_FROM_MMR(CALC_MMR(dcu, idx))) 34 #define CALC_TXBLK_VALUE(idx) (1 << (idx & 0x1f)) 35 36 /* MAC register values */ 37 38 #define INIT_INTERRUPT_MASK \ 39 ( AR_IMR_TXERR | AR_IMR_TXOK | AR_IMR_RXORN | \ 40 AR_IMR_RXERR | AR_IMR_RXOK | AR_IMR_TXURN | \ 41 AR_IMR_HIUERR ) 42 #define INIT_BEACON_CONTROL \ 43 ((INIT_RESET_TSF << 24) | (INIT_BEACON_EN << 23) | \ 44 (INIT_TIM_OFFSET << 16) | INIT_BEACON_PERIOD) 45 46 #define INIT_CONFIG_STATUS 0x00000000 47 #define INIT_RSSI_THR 0x00000781 /* Missed beacon counter initialized to 0x7 (max is 0xff) */ 48 #define INIT_IQCAL_LOG_COUNT_MAX 0xF 49 #define INIT_BCON_CNTRL_REG 0x00000000 50 51 #define INIT_USEC 40 52 #define HALF_RATE_USEC 19 /* ((40 / 2) - 1 ) */ 53 #define QUARTER_RATE_USEC 9 /* ((40 / 4) - 1 ) */ 54 55 #define RX_NON_FULL_RATE_LATENCY 63 56 #define TX_HALF_RATE_LATENCY 108 57 #define TX_QUARTER_RATE_LATENCY 216 58 59 #define IFS_SLOT_FULL_RATE 0x168 /* 9 us half, 40 MHz core clock (9*40) */ 60 #define IFS_SLOT_HALF_RATE 0x104 /* 13 us half, 20 MHz core clock (13*20) */ 61 #define IFS_SLOT_QUARTER_RATE 0xD2 /* 21 us quarter, 10 MHz core clock (21*10) */ 62 #define IFS_EIFS_FULL_RATE 0xE60 /* (74 + (2 * 9)) * 40MHz core clock */ 63 #define IFS_EIFS_HALF_RATE 0xDAC /* (149 + (2 * 13)) * 20MHz core clock */ 64 #define IFS_EIFS_QUARTER_RATE 0xD48 /* (298 + (2 * 21)) * 10MHz core clock */ 65 66 #define ACK_CTS_TIMEOUT_11A 0x3E8 /* ACK timeout in 11a core clocks */ 67 68 /* Tx frame start to tx data start delay */ 69 #define TX_FRAME_D_START_HALF_RATE 0xc 70 #define TX_FRAME_D_START_QUARTER_RATE 0xd 71 72 /* 73 * Various fifo fill before Tx start, in 64-byte units 74 * i.e. put the frame in the air while still DMAing 75 */ 76 #define MIN_TX_FIFO_THRESHOLD 0x1 77 #define MAX_TX_FIFO_THRESHOLD ((IEEE80211_MAX_LEN / 64) + 1) 78 #define INIT_TX_FIFO_THRESHOLD MIN_TX_FIFO_THRESHOLD 79 80 #define HAL_DECOMP_MASK_SIZE 128 /* 1 byte per key */ 81 82 /* 83 * Gain support. 84 */ 85 #define NUM_CORNER_FIX_BITS 4 86 #define NUM_CORNER_FIX_BITS_5112 7 87 #define DYN_ADJ_UP_MARGIN 15 88 #define DYN_ADJ_LO_MARGIN 20 89 #define PHY_PROBE_CCK_CORRECTION 5 90 #define CCK_OFDM_GAIN_DELTA 15 91 92 enum GAIN_PARAMS { 93 GP_TXCLIP, 94 GP_PD90, 95 GP_PD84, 96 GP_GSEL, 97 }; 98 99 enum GAIN_PARAMS_5112 { 100 GP_MIXGAIN_OVR, 101 GP_PWD_138, 102 GP_PWD_137, 103 GP_PWD_136, 104 GP_PWD_132, 105 GP_PWD_131, 106 GP_PWD_130, 107 }; 108 109 typedef struct _gainOptStep { 110 int16_t paramVal[NUM_CORNER_FIX_BITS_5112]; 111 int32_t stepGain; 112 int8_t stepName[16]; 113 } GAIN_OPTIMIZATION_STEP; 114 115 typedef struct { 116 uint32_t numStepsInLadder; 117 uint32_t defaultStepNum; 118 GAIN_OPTIMIZATION_STEP optStep[10]; 119 } GAIN_OPTIMIZATION_LADDER; 120 121 typedef struct { 122 uint32_t currStepNum; 123 uint32_t currGain; 124 uint32_t targetGain; 125 uint32_t loTrig; 126 uint32_t hiTrig; 127 uint32_t active; 128 const GAIN_OPTIMIZATION_STEP *currStep; 129 } GAIN_VALUES; 130 131 /* RF HAL structures */ 132 typedef struct RfHalFuncs { 133 void *priv; /* private state */ 134 135 void (*rfDetach)(struct ath_hal *ah); 136 void (*writeRegs)(struct ath_hal *, 137 u_int modeIndex, u_int freqIndex, int regWrites); 138 uint32_t *(*getRfBank)(struct ath_hal *ah, int bank); 139 HAL_BOOL (*setChannel)(struct ath_hal *, 140 const struct ieee80211_channel *); 141 HAL_BOOL (*setRfRegs)(struct ath_hal *, 142 const struct ieee80211_channel *, uint16_t modesIndex, 143 uint16_t *rfXpdGain); 144 HAL_BOOL (*setPowerTable)(struct ath_hal *ah, 145 int16_t *minPower, int16_t *maxPower, 146 const struct ieee80211_channel *, uint16_t *rfXpdGain); 147 HAL_BOOL (*getChannelMaxMinPower)(struct ath_hal *ah, 148 const struct ieee80211_channel *, 149 int16_t *maxPow, int16_t *minPow); 150 int16_t (*getNfAdjust)(struct ath_hal *, const HAL_CHANNEL_INTERNAL*); 151 } RF_HAL_FUNCS; 152 153 struct ar5212AniParams { 154 int maxNoiseImmunityLevel; /* [0..4] */ 155 int totalSizeDesired[5]; 156 int coarseHigh[5]; 157 int coarseLow[5]; 158 int firpwr[5]; 159 160 int maxSpurImmunityLevel; /* [0..7] */ 161 int cycPwrThr1[8]; 162 163 int maxFirstepLevel; /* [0..2] */ 164 int firstep[3]; 165 166 uint32_t ofdmTrigHigh; 167 uint32_t ofdmTrigLow; 168 uint32_t cckTrigHigh; 169 uint32_t cckTrigLow; 170 int32_t rssiThrLow; 171 uint32_t rssiThrHigh; 172 173 int period; /* update listen period */ 174 175 /* NB: intentionally ordered so data exported to user space is first */ 176 uint32_t ofdmPhyErrBase; /* Base value for ofdm err counter */ 177 uint32_t cckPhyErrBase; /* Base value for cck err counters */ 178 }; 179 180 /* 181 * Per-channel ANI state private to the driver. 182 */ 183 struct ar5212AniState { 184 uint8_t noiseImmunityLevel; 185 uint8_t spurImmunityLevel; 186 uint8_t firstepLevel; 187 uint8_t ofdmWeakSigDetectOff; 188 uint8_t cckWeakSigThreshold; 189 uint32_t listenTime; 190 191 /* NB: intentionally ordered so data exported to user space is first */ 192 uint32_t txFrameCount; /* Last txFrameCount */ 193 uint32_t rxFrameCount; /* Last rx Frame count */ 194 uint32_t cycleCount; /* Last cycleCount 195 (to detect wrap-around) */ 196 uint32_t ofdmPhyErrCount;/* OFDM err count since last reset */ 197 uint32_t cckPhyErrCount; /* CCK err count since last reset */ 198 199 const struct ar5212AniParams *params; 200 }; 201 202 #define HAL_ANI_ENA 0x00000001 /* ANI operation enabled */ 203 #define HAL_RSSI_ANI_ENA 0x00000002 /* rssi-based processing ena'd*/ 204 205 #if 0 206 struct ar5212Stats { 207 uint32_t ast_ani_niup; /* ANI increased noise immunity */ 208 uint32_t ast_ani_nidown; /* ANI decreased noise immunity */ 209 uint32_t ast_ani_spurup; /* ANI increased spur immunity */ 210 uint32_t ast_ani_spurdown;/* ANI descreased spur immunity */ 211 uint32_t ast_ani_ofdmon; /* ANI OFDM weak signal detect on */ 212 uint32_t ast_ani_ofdmoff;/* ANI OFDM weak signal detect off */ 213 uint32_t ast_ani_cckhigh;/* ANI CCK weak signal threshold high */ 214 uint32_t ast_ani_ccklow; /* ANI CCK weak signal threshold low */ 215 uint32_t ast_ani_stepup; /* ANI increased first step level */ 216 uint32_t ast_ani_stepdown;/* ANI decreased first step level */ 217 uint32_t ast_ani_ofdmerrs;/* ANI cumulative ofdm phy err count */ 218 uint32_t ast_ani_cckerrs;/* ANI cumulative cck phy err count */ 219 uint32_t ast_ani_reset; /* ANI parameters zero'd for non-STA */ 220 uint32_t ast_ani_lzero; /* ANI listen time forced to zero */ 221 uint32_t ast_ani_lneg; /* ANI listen time calculated < 0 */ 222 HAL_MIB_STATS ast_mibstats; /* MIB counter stats */ 223 HAL_NODE_STATS ast_nodestats; /* Latest rssi stats from driver */ 224 }; 225 #endif 226 227 /* 228 * NF Cal history buffer 229 */ 230 #define AR5212_CCA_MAX_GOOD_VALUE -95 231 #define AR5212_CCA_MAX_HIGH_VALUE -62 232 #define AR5212_CCA_MIN_BAD_VALUE -125 233 234 #define AR512_NF_CAL_HIST_MAX 5 235 236 struct ar5212NfCalHist { 237 int16_t nfCalBuffer[AR512_NF_CAL_HIST_MAX]; 238 int16_t privNF; 239 uint8_t currIndex; 240 uint8_t first_run; 241 uint8_t invalidNFcount; 242 }; 243 244 struct ath_hal_5212 { 245 struct ath_hal_private ah_priv; /* base class */ 246 247 /* 248 * Per-chip common Initialization data. 249 * NB: RF backends have their own ini data. 250 */ 251 HAL_INI_ARRAY ah_ini_modes; 252 HAL_INI_ARRAY ah_ini_common; 253 254 GAIN_VALUES ah_gainValues; 255 256 uint8_t ah_macaddr[IEEE80211_ADDR_LEN]; 257 uint8_t ah_bssid[IEEE80211_ADDR_LEN]; 258 uint8_t ah_bssidmask[IEEE80211_ADDR_LEN]; 259 uint16_t ah_assocId; 260 261 /* 262 * Runtime state. 263 */ 264 uint32_t ah_maskReg; /* copy of AR_IMR */ 265 HAL_ANI_STATS ah_stats; /* various statistics */ 266 RF_HAL_FUNCS *ah_rfHal; 267 uint32_t ah_txDescMask; /* mask for TXDESC */ 268 uint32_t ah_txOkInterruptMask; 269 uint32_t ah_txErrInterruptMask; 270 uint32_t ah_txDescInterruptMask; 271 uint32_t ah_txEolInterruptMask; 272 uint32_t ah_txUrnInterruptMask; 273 HAL_TX_QUEUE_INFO ah_txq[HAL_NUM_TX_QUEUES]; 274 uint32_t ah_intrTxqs; /* tx q interrupt state */ 275 /* decomp mask array */ 276 uint8_t ah_decompMask[HAL_DECOMP_MASK_SIZE]; 277 HAL_ANT_SETTING ah_antControl; /* antenna setting */ 278 HAL_BOOL ah_diversity; /* fast diversity setting */ 279 enum { 280 IQ_CAL_INACTIVE, 281 IQ_CAL_RUNNING, 282 IQ_CAL_DONE 283 } ah_bIQCalibration; /* IQ calibrate state */ 284 HAL_RFGAIN ah_rfgainState; /* RF gain calibrartion state */ 285 uint32_t ah_tx6PowerInHalfDbm; /* power output for 6Mb tx */ 286 uint32_t ah_staId1Defaults; /* STA_ID1 default settings */ 287 uint32_t ah_miscMode; /* MISC_MODE settings */ 288 uint32_t ah_rssiThr; /* RSSI_THR settings */ 289 HAL_BOOL ah_cwCalRequire; /* for ap51 */ 290 HAL_BOOL ah_tpcEnabled; /* per-packet tpc enabled */ 291 HAL_BOOL ah_phyPowerOn; /* PHY power state */ 292 HAL_BOOL ah_isHb63; /* cached HB63 check */ 293 uint32_t ah_macTPC; /* tpc register */ 294 uint32_t ah_beaconInterval; /* XXX */ 295 enum { 296 AUTO_32KHZ, /* use it if 32kHz crystal present */ 297 USE_32KHZ, /* do it regardless */ 298 DONT_USE_32KHZ, /* don't use it regardless */ 299 } ah_enable32kHzClock; /* whether to sleep at 32kHz */ 300 uint32_t ah_ofdmTxPower; 301 int16_t ah_txPowerIndexOffset; 302 /* 303 * Noise floor cal histogram support. 304 */ 305 struct ar5212NfCalHist ah_nfCalHist; 306 307 u_int ah_slottime; /* user-specified slot time */ 308 u_int ah_acktimeout; /* user-specified ack timeout */ 309 u_int ah_ctstimeout; /* user-specified cts timeout */ 310 u_int ah_sifstime; /* user-specified sifs time */ 311 /* 312 * RF Silent handling; setup according to the EEPROM. 313 */ 314 uint32_t ah_gpioSelect; /* GPIO pin to use */ 315 uint32_t ah_polarity; /* polarity to disable RF */ 316 uint32_t ah_gpioBit; /* after init, prev value */ 317 /* 318 * ANI support. 319 */ 320 uint32_t ah_procPhyErr; /* Process Phy errs */ 321 HAL_BOOL ah_hasHwPhyCounters; /* Hardware has phy counters */ 322 struct ar5212AniParams ah_aniParams24; /* 2.4GHz parameters */ 323 struct ar5212AniParams ah_aniParams5; /* 5GHz parameters */ 324 struct ar5212AniState *ah_curani; /* cached last reference */ 325 struct ar5212AniState ah_ani[AH_MAXCHAN]; /* per-channel state */ 326 327 /* AR5416 uses some of the AR5212 ANI code; these are the ANI methods */ 328 HAL_BOOL (*ah_aniControl) (struct ath_hal *, HAL_ANI_CMD cmd, int param); 329 330 /* 331 * Transmit power state. Note these are maintained 332 * here so they can be retrieved by diagnostic tools. 333 */ 334 uint16_t *ah_pcdacTable; 335 u_int ah_pcdacTableSize; 336 uint16_t ah_ratesArray[37]; 337 338 uint8_t ah_txTrigLev; /* current Tx trigger level */ 339 uint8_t ah_maxTxTrigLev; /* max tx trigger level */ 340 341 /* 342 * Channel Tx, Rx, Rx Clear State 343 */ 344 uint32_t ah_cycleCount; 345 uint32_t ah_ctlBusy; 346 uint32_t ah_rxBusy; 347 uint32_t ah_txBusy; 348 uint32_t ah_rx_chainmask; 349 uint32_t ah_tx_chainmask; 350 351 /* Used to return ANI statistics to the diagnostic API */ 352 HAL_ANI_STATS ext_ani_stats; 353 }; 354 #define AH5212(_ah) ((struct ath_hal_5212 *)(_ah)) 355 356 /* 357 * IS_XXXX macros test the MAC version 358 * IS_RADXXX macros test the radio/RF version (matching both 2G-only and 2/5G) 359 * 360 * Some single chip radios have equivalent radio/RF (e.g. 5112) 361 * for those use IS_RADXXX_ANY macros. 362 */ 363 #define IS_2317(ah) \ 364 ((AH_PRIVATE(ah)->ah_devid == AR5212_AR2317_REV1) || \ 365 (AH_PRIVATE(ah)->ah_devid == AR5212_AR2317_REV2)) 366 #define IS_2316(ah) \ 367 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2415) 368 #define IS_2413(ah) \ 369 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2413 || IS_2316(ah)) 370 #define IS_5424(ah) \ 371 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5424 || \ 372 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5413 && \ 373 AH_PRIVATE(ah)->ah_macRev <= AR_SREV_D2PLUS_MS)) 374 #define IS_5413(ah) \ 375 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5413 || IS_5424(ah)) 376 #define IS_2425(ah) \ 377 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2425) 378 #define IS_2417(ah) \ 379 ((AH_PRIVATE(ah)->ah_macVersion) == AR_SREV_2417) 380 #define IS_HB63(ah) (AH5212(ah)->ah_isHb63 == AH_TRUE) 381 382 #define AH_RADIO_MAJOR(ah) \ 383 (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) 384 #define AH_RADIO_MINOR(ah) \ 385 (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MINOR) 386 #define IS_RAD5111(ah) \ 387 (AH_RADIO_MAJOR(ah) == AR_RAD5111_SREV_MAJOR || \ 388 AH_RADIO_MAJOR(ah) == AR_RAD2111_SREV_MAJOR) 389 #define IS_RAD5112(ah) \ 390 (AH_RADIO_MAJOR(ah) == AR_RAD5112_SREV_MAJOR || \ 391 AH_RADIO_MAJOR(ah) == AR_RAD2112_SREV_MAJOR) 392 /* NB: does not include 5413 as Atheros' IS_5112 macro does */ 393 #define IS_RAD5112_ANY(ah) \ 394 (AR_RAD5112_SREV_MAJOR <= AH_RADIO_MAJOR(ah) && \ 395 AH_RADIO_MAJOR(ah) <= AR_RAD2413_SREV_MAJOR) 396 #define IS_RAD5112_REV1(ah) \ 397 (IS_RAD5112(ah) && \ 398 AH_RADIO_MINOR(ah) < (AR_RAD5112_SREV_2_0 & AR_RADIO_SREV_MINOR)) 399 #define IS_RADX112_REV2(ah) \ 400 (AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD5112_SREV_2_0 || \ 401 AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD2112_SREV_2_0 || \ 402 AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD2112_SREV_2_1 || \ 403 AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD5112_SREV_2_1) 404 405 #define ar5212RfDetach(ah) do { \ 406 if (AH5212(ah)->ah_rfHal != AH_NULL) \ 407 AH5212(ah)->ah_rfHal->rfDetach(ah); \ 408 } while (0) 409 #define ar5212GetRfBank(ah, b) \ 410 AH5212(ah)->ah_rfHal->getRfBank(ah, b) 411 412 /* 413 * Hack macros for Nala/San: 11b is handled 414 * using 11g; flip the channel flags to accomplish this. 415 */ 416 #define SAVE_CCK(_ah, _chan, _flag) do { \ 417 if ((IS_2425(_ah) || IS_2417(_ah)) && \ 418 (((_chan)->ic_flags) & IEEE80211_CHAN_CCK)) { \ 419 (_chan)->ic_flags &= ~IEEE80211_CHAN_CCK; \ 420 (_chan)->ic_flags |= IEEE80211_CHAN_DYN; \ 421 (_flag) = AH_TRUE; \ 422 } else \ 423 (_flag) = AH_FALSE; \ 424 } while (0) 425 #define RESTORE_CCK(_ah, _chan, _flag) do { \ 426 if ((_flag) && (IS_2425(_ah) || IS_2417(_ah))) { \ 427 (_chan)->ic_flags &= ~IEEE80211_CHAN_DYN; \ 428 (_chan)->ic_flags |= IEEE80211_CHAN_CCK; \ 429 } \ 430 } while (0) 431 432 struct ath_hal; 433 434 extern uint32_t ar5212GetRadioRev(struct ath_hal *ah); 435 extern void ar5212InitState(struct ath_hal_5212 *, uint16_t devid, HAL_SOFTC, 436 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status); 437 extern void ar5212Detach(struct ath_hal *ah); 438 extern HAL_BOOL ar5212ChipTest(struct ath_hal *ah); 439 extern HAL_BOOL ar5212GetChannelEdges(struct ath_hal *ah, 440 uint16_t flags, uint16_t *low, uint16_t *high); 441 extern HAL_BOOL ar5212FillCapabilityInfo(struct ath_hal *ah); 442 443 extern void ar5212SetBeaconTimers(struct ath_hal *ah, 444 const HAL_BEACON_TIMERS *); 445 extern void ar5212BeaconInit(struct ath_hal *ah, 446 uint32_t next_beacon, uint32_t beacon_period); 447 extern void ar5212ResetStaBeaconTimers(struct ath_hal *ah); 448 extern void ar5212SetStaBeaconTimers(struct ath_hal *ah, 449 const HAL_BEACON_STATE *); 450 extern uint64_t ar5212GetNextTBTT(struct ath_hal *); 451 452 extern HAL_BOOL ar5212IsInterruptPending(struct ath_hal *ah); 453 extern HAL_BOOL ar5212GetPendingInterrupts(struct ath_hal *ah, HAL_INT *); 454 extern HAL_INT ar5212GetInterrupts(struct ath_hal *ah); 455 extern HAL_INT ar5212SetInterrupts(struct ath_hal *ah, HAL_INT ints); 456 457 extern uint32_t ar5212GetKeyCacheSize(struct ath_hal *); 458 extern HAL_BOOL ar5212IsKeyCacheEntryValid(struct ath_hal *, uint16_t entry); 459 extern HAL_BOOL ar5212ResetKeyCacheEntry(struct ath_hal *ah, uint16_t entry); 460 extern HAL_BOOL ar5212SetKeyCacheEntryMac(struct ath_hal *, 461 uint16_t entry, const uint8_t *mac); 462 extern HAL_BOOL ar5212SetKeyCacheEntry(struct ath_hal *ah, uint16_t entry, 463 const HAL_KEYVAL *k, const uint8_t *mac, int xorKey); 464 465 extern void ar5212GetMacAddress(struct ath_hal *ah, uint8_t *mac); 466 extern HAL_BOOL ar5212SetMacAddress(struct ath_hal *ah, const uint8_t *); 467 extern void ar5212GetBssIdMask(struct ath_hal *ah, uint8_t *mac); 468 extern HAL_BOOL ar5212SetBssIdMask(struct ath_hal *, const uint8_t *); 469 extern HAL_BOOL ar5212EepromRead(struct ath_hal *, u_int off, uint16_t *data); 470 extern HAL_BOOL ar5212EepromWrite(struct ath_hal *, u_int off, uint16_t data); 471 extern HAL_BOOL ar5212SetRegulatoryDomain(struct ath_hal *ah, 472 uint16_t regDomain, HAL_STATUS *stats); 473 extern u_int ar5212GetWirelessModes(struct ath_hal *ah); 474 extern void ar5212EnableRfKill(struct ath_hal *); 475 extern HAL_BOOL ar5212GpioCfgOutput(struct ath_hal *, uint32_t gpio, 476 HAL_GPIO_MUX_TYPE); 477 extern HAL_BOOL ar5212GpioCfgInput(struct ath_hal *, uint32_t gpio); 478 extern HAL_BOOL ar5212GpioSet(struct ath_hal *, uint32_t gpio, uint32_t val); 479 extern uint32_t ar5212GpioGet(struct ath_hal *ah, uint32_t gpio); 480 extern void ar5212GpioSetIntr(struct ath_hal *ah, u_int, uint32_t ilevel); 481 extern void ar5212SetLedState(struct ath_hal *ah, HAL_LED_STATE state); 482 extern void ar5212WriteAssocid(struct ath_hal *ah, const uint8_t *bssid, 483 uint16_t assocId); 484 extern uint32_t ar5212GetTsf32(struct ath_hal *ah); 485 extern uint64_t ar5212GetTsf64(struct ath_hal *ah); 486 extern void ar5212SetTsf64(struct ath_hal *ah, uint64_t tsf64); 487 extern void ar5212ResetTsf(struct ath_hal *ah); 488 extern void ar5212SetBasicRate(struct ath_hal *ah, HAL_RATE_SET *pSet); 489 extern uint32_t ar5212GetRandomSeed(struct ath_hal *ah); 490 extern HAL_BOOL ar5212DetectCardPresent(struct ath_hal *ah); 491 extern void ar5212EnableMibCounters(struct ath_hal *); 492 extern void ar5212DisableMibCounters(struct ath_hal *); 493 extern void ar5212UpdateMibCounters(struct ath_hal *ah, HAL_MIB_STATS* stats); 494 extern HAL_BOOL ar5212IsJapanChannelSpreadSupported(struct ath_hal *ah); 495 extern uint32_t ar5212GetCurRssi(struct ath_hal *ah); 496 extern u_int ar5212GetDefAntenna(struct ath_hal *ah); 497 extern void ar5212SetDefAntenna(struct ath_hal *ah, u_int antenna); 498 extern HAL_ANT_SETTING ar5212GetAntennaSwitch(struct ath_hal *); 499 extern HAL_BOOL ar5212SetAntennaSwitch(struct ath_hal *, HAL_ANT_SETTING); 500 extern HAL_BOOL ar5212IsSleepAfterBeaconBroken(struct ath_hal *ah); 501 extern HAL_BOOL ar5212SetSifsTime(struct ath_hal *, u_int); 502 extern u_int ar5212GetSifsTime(struct ath_hal *); 503 extern HAL_BOOL ar5212SetSlotTime(struct ath_hal *, u_int); 504 extern u_int ar5212GetSlotTime(struct ath_hal *); 505 extern HAL_BOOL ar5212SetAckTimeout(struct ath_hal *, u_int); 506 extern u_int ar5212GetAckTimeout(struct ath_hal *); 507 extern HAL_BOOL ar5212SetAckCTSRate(struct ath_hal *, u_int); 508 extern u_int ar5212GetAckCTSRate(struct ath_hal *); 509 extern HAL_BOOL ar5212SetCTSTimeout(struct ath_hal *, u_int); 510 extern u_int ar5212GetCTSTimeout(struct ath_hal *); 511 extern HAL_BOOL ar5212SetDecompMask(struct ath_hal *, uint16_t, int); 512 void ar5212SetCoverageClass(struct ath_hal *, uint8_t, int); 513 extern void ar5212SetPCUConfig(struct ath_hal *); 514 extern HAL_BOOL ar5212Use32KHzclock(struct ath_hal *ah, HAL_OPMODE opmode); 515 extern void ar5212SetupClock(struct ath_hal *ah, HAL_OPMODE opmode); 516 extern void ar5212RestoreClock(struct ath_hal *ah, HAL_OPMODE opmode); 517 extern int16_t ar5212GetNfAdjust(struct ath_hal *, 518 const HAL_CHANNEL_INTERNAL *); 519 extern void ar5212SetCompRegs(struct ath_hal *ah); 520 extern HAL_STATUS ar5212GetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE, 521 uint32_t, uint32_t *); 522 extern HAL_BOOL ar5212SetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE, 523 uint32_t, uint32_t, HAL_STATUS *); 524 extern HAL_BOOL ar5212GetDiagState(struct ath_hal *ah, int request, 525 const void *args, uint32_t argsize, 526 void **result, uint32_t *resultsize); 527 extern HAL_STATUS ar5212SetQuiet(struct ath_hal *ah, uint32_t period, 528 uint32_t duration, uint32_t nextStart, HAL_QUIET_FLAG flag); 529 extern HAL_BOOL ar5212GetMibCycleCounts(struct ath_hal *, 530 HAL_SURVEY_SAMPLE *); 531 extern void ar5212SetChainMasks(struct ath_hal *, uint32_t, uint32_t); 532 533 extern HAL_BOOL ar5212SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode, 534 int setChip); 535 extern HAL_POWER_MODE ar5212GetPowerMode(struct ath_hal *ah); 536 extern HAL_BOOL ar5212GetPowerStatus(struct ath_hal *ah); 537 538 extern uint32_t ar5212GetRxDP(struct ath_hal *ath, HAL_RX_QUEUE); 539 extern void ar5212SetRxDP(struct ath_hal *ah, uint32_t rxdp, HAL_RX_QUEUE); 540 extern void ar5212EnableReceive(struct ath_hal *ah); 541 extern HAL_BOOL ar5212StopDmaReceive(struct ath_hal *ah); 542 extern void ar5212StartPcuReceive(struct ath_hal *ah, HAL_BOOL); 543 extern void ar5212StopPcuReceive(struct ath_hal *ah); 544 extern void ar5212SetMulticastFilter(struct ath_hal *ah, 545 uint32_t filter0, uint32_t filter1); 546 extern HAL_BOOL ar5212ClrMulticastFilterIndex(struct ath_hal *, uint32_t ix); 547 extern HAL_BOOL ar5212SetMulticastFilterIndex(struct ath_hal *, uint32_t ix); 548 extern uint32_t ar5212GetRxFilter(struct ath_hal *ah); 549 extern void ar5212SetRxFilter(struct ath_hal *ah, uint32_t bits); 550 extern HAL_BOOL ar5212SetupRxDesc(struct ath_hal *, 551 struct ath_desc *, uint32_t size, u_int flags); 552 extern HAL_STATUS ar5212ProcRxDesc(struct ath_hal *ah, struct ath_desc *, 553 uint32_t, struct ath_desc *, uint64_t, 554 struct ath_rx_status *); 555 556 extern HAL_BOOL ar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode, 557 struct ieee80211_channel *chan, HAL_BOOL bChannelChange, 558 HAL_RESET_TYPE, HAL_STATUS *status); 559 extern HAL_BOOL ar5212SetChannel(struct ath_hal *, 560 const struct ieee80211_channel *); 561 extern void ar5212SetOperatingMode(struct ath_hal *ah, int opmode); 562 extern HAL_BOOL ar5212PhyDisable(struct ath_hal *ah); 563 extern HAL_BOOL ar5212Disable(struct ath_hal *ah); 564 extern HAL_BOOL ar5212ChipReset(struct ath_hal *ah, 565 const struct ieee80211_channel *); 566 extern HAL_BOOL ar5212PerCalibration(struct ath_hal *ah, 567 struct ieee80211_channel *chan, HAL_BOOL *isIQdone); 568 extern HAL_BOOL ar5212PerCalibrationN(struct ath_hal *ah, 569 struct ieee80211_channel *chan, u_int chainMask, 570 HAL_BOOL longCal, HAL_BOOL *isCalDone); 571 extern HAL_BOOL ar5212ResetCalValid(struct ath_hal *ah, 572 const struct ieee80211_channel *); 573 extern int16_t ar5212GetNoiseFloor(struct ath_hal *ah); 574 extern void ar5212InitNfCalHistBuffer(struct ath_hal *); 575 extern int16_t ar5212GetNfHistMid(const int16_t calData[]); 576 extern void ar5212SetSpurMitigation(struct ath_hal *, 577 const struct ieee80211_channel *); 578 extern HAL_BOOL ar5212SetAntennaSwitchInternal(struct ath_hal *ah, 579 HAL_ANT_SETTING settings, const struct ieee80211_channel *); 580 extern HAL_BOOL ar5212SetTxPowerLimit(struct ath_hal *ah, uint32_t limit); 581 extern HAL_BOOL ar5212GetChipPowerLimits(struct ath_hal *ah, 582 struct ieee80211_channel *chan); 583 extern void ar5212InitializeGainValues(struct ath_hal *); 584 extern HAL_RFGAIN ar5212GetRfgain(struct ath_hal *ah); 585 extern void ar5212RequestRfgain(struct ath_hal *); 586 587 extern HAL_BOOL ar5212UpdateTxTrigLevel(struct ath_hal *, 588 HAL_BOOL IncTrigLevel); 589 extern HAL_BOOL ar5212SetTxQueueProps(struct ath_hal *ah, int q, 590 const HAL_TXQ_INFO *qInfo); 591 extern HAL_BOOL ar5212GetTxQueueProps(struct ath_hal *ah, int q, 592 HAL_TXQ_INFO *qInfo); 593 extern int ar5212SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type, 594 const HAL_TXQ_INFO *qInfo); 595 extern HAL_BOOL ar5212ReleaseTxQueue(struct ath_hal *ah, u_int q); 596 extern HAL_BOOL ar5212ResetTxQueue(struct ath_hal *ah, u_int q); 597 extern uint32_t ar5212GetTxDP(struct ath_hal *ah, u_int q); 598 extern HAL_BOOL ar5212SetTxDP(struct ath_hal *ah, u_int q, uint32_t txdp); 599 extern HAL_BOOL ar5212StartTxDma(struct ath_hal *ah, u_int q); 600 extern uint32_t ar5212NumTxPending(struct ath_hal *ah, u_int q); 601 extern HAL_BOOL ar5212StopTxDma(struct ath_hal *ah, u_int q); 602 extern HAL_BOOL ar5212SetupTxDesc(struct ath_hal *ah, struct ath_desc *ds, 603 u_int pktLen, u_int hdrLen, HAL_PKT_TYPE type, u_int txPower, 604 u_int txRate0, u_int txTries0, 605 u_int keyIx, u_int antMode, u_int flags, 606 u_int rtsctsRate, u_int rtsctsDuration, 607 u_int compicvLen, u_int compivLen, u_int comp); 608 extern HAL_BOOL ar5212SetupXTxDesc(struct ath_hal *, struct ath_desc *, 609 u_int txRate1, u_int txRetries1, 610 u_int txRate2, u_int txRetries2, 611 u_int txRate3, u_int txRetries3); 612 extern HAL_BOOL ar5212FillTxDesc(struct ath_hal *ah, struct ath_desc *ds, 613 HAL_DMA_ADDR *bufAddrList, uint32_t *segLenList, 614 u_int descId, u_int qcuId, HAL_BOOL firstSeg, HAL_BOOL lastSeg, 615 const struct ath_desc *ds0); 616 extern HAL_STATUS ar5212ProcTxDesc(struct ath_hal *ah, 617 struct ath_desc *, struct ath_tx_status *); 618 extern void ar5212GetTxIntrQueue(struct ath_hal *ah, uint32_t *); 619 extern void ar5212IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *); 620 extern HAL_BOOL ar5212GetTxCompletionRates(struct ath_hal *ah, 621 const struct ath_desc *ds0, int *rates, int *tries); 622 extern void ar5212SetTxDescLink(struct ath_hal *ah, void *ds, 623 uint32_t link); 624 extern void ar5212GetTxDescLink(struct ath_hal *ah, void *ds, 625 uint32_t *link); 626 extern void ar5212GetTxDescLinkPtr(struct ath_hal *ah, void *ds, 627 uint32_t **linkptr); 628 629 extern const HAL_RATE_TABLE *ar5212GetRateTable(struct ath_hal *, u_int mode); 630 631 extern void ar5212AniAttach(struct ath_hal *, const struct ar5212AniParams *, 632 const struct ar5212AniParams *, HAL_BOOL ena); 633 extern void ar5212AniDetach(struct ath_hal *); 634 extern struct ar5212AniState *ar5212AniGetCurrentState(struct ath_hal *); 635 extern HAL_ANI_STATS *ar5212AniGetCurrentStats(struct ath_hal *); 636 extern HAL_BOOL ar5212AniControl(struct ath_hal *, HAL_ANI_CMD cmd, int param); 637 extern HAL_BOOL ar5212AniSetParams(struct ath_hal *, 638 const struct ar5212AniParams *, const struct ar5212AniParams *); 639 struct ath_rx_status; 640 extern void ar5212AniPhyErrReport(struct ath_hal *ah, 641 const struct ath_rx_status *rs); 642 extern void ar5212ProcessMibIntr(struct ath_hal *, const HAL_NODE_STATS *); 643 extern void ar5212RxMonitor(struct ath_hal *, const HAL_NODE_STATS *, 644 const struct ieee80211_channel *); 645 extern void ar5212AniPoll(struct ath_hal *, const struct ieee80211_channel *); 646 extern void ar5212AniReset(struct ath_hal *, const struct ieee80211_channel *, 647 HAL_OPMODE, int); 648 649 extern HAL_BOOL ar5212IsNFCalInProgress(struct ath_hal *ah); 650 extern HAL_BOOL ar5212WaitNFCalComplete(struct ath_hal *ah, int i); 651 extern void ar5212EnableDfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe); 652 extern HAL_BOOL ar5212GetDfsDefaultThresh(struct ath_hal *ah, 653 HAL_PHYERR_PARAM *pe); 654 extern void ar5212GetDfsThresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe); 655 extern HAL_BOOL ar5212ProcessRadarEvent(struct ath_hal *ah, 656 struct ath_rx_status *rxs, uint64_t fulltsf, const char *buf, 657 HAL_DFS_EVENT *event); 658 extern HAL_BOOL ar5212IsFastClockEnabled(struct ath_hal *ah); 659 extern uint32_t ar5212Get11nExtBusy(struct ath_hal *ah); 660 661 #endif /* _ATH_AR5212_H_ */ 662