xref: /freebsd/sys/dev/ath/ath_hal/ar5211/ar5211phy.h (revision d485c77f203fb0f4cdc08dea5ff81631b51d8809)
1 /*-
2  * SPDX-License-Identifier: ISC
3  *
4  * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5  * Copyright (c) 2002-2006 Atheros Communications, Inc.
6  *
7  * Permission to use, copy, modify, and/or distribute this software for any
8  * purpose with or without fee is hereby granted, provided that the above
9  * copyright notice and this permission notice appear in all copies.
10  *
11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18  *
19  * $FreeBSD$
20  */
21 #ifndef _DEV_ATH_AR5211PHY_H
22 #define _DEV_ATH_AR5211PHY_H
23 
24 /*
25  * Definitions for the PHY on the Atheros AR5211/5311 chipset.
26  */
27 
28 /* PHY registers */
29 #define	AR_PHY_BASE	0x9800	/* PHY registers base address */
30 #define	AR_PHY(_n)	(AR_PHY_BASE + ((_n)<<2))
31 
32 #define	AR_PHY_TURBO	0x9804	/* PHY frame control register */
33 #define	AR_PHY_FC_TURBO_MODE	0x00000001	/* Set turbo mode bits */
34 #define	AR_PHY_FC_TURBO_SHORT	0x00000002	/* Set short symbols to turbo mode setting */
35 
36 #define	AR_PHY_CHIP_ID	0x9818	/* PHY chip revision ID */
37 
38 #define	AR_PHY_ACTIVE	0x981C	/* PHY activation register */
39 #define	AR_PHY_ACTIVE_EN	0x00000001	/* Activate PHY chips */
40 #define	AR_PHY_ACTIVE_DIS	0x00000000	/* Deactivate PHY chips */
41 
42 #define	AR_PHY_AGC_CONTROL	0x9860	/* PHY chip calibration and noise floor setting */
43 #define	AR_PHY_AGC_CONTROL_CAL	0x00000001	/* Perform PHY chip internal calibration */
44 #define	AR_PHY_AGC_CONTROL_NF	0x00000002	/* Perform PHY chip noise-floor calculation */
45 
46 #define	AR_PHY_PLL_CTL	0x987c	/* PLL control register */
47 #define	AR_PHY_PLL_CTL_44	0x19	/* 44 MHz for 11b channels and FPGA */
48 #define	AR_PHY_PLL_CTL_40	0x18	/* 40 MHz */
49 #define	AR_PHY_PLL_CTL_20	0x13	/* 20 MHz half rate 11a for emulation */
50 
51 #define	AR_PHY_RX_DELAY	0x9914	/* PHY analog_power_on_time, in 100ns increments */
52 #define	AR_PHY_RX_DELAY_M	0x00003FFF	/* Mask for delay from active assertion (wake up) */
53 				/* to enable_receiver */
54 
55 #define	AR_PHY_TIMING_CTRL4	0x9920	/* PHY */
56 #define	AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_M	0x0000001F	/* Mask for kcos_theta-1 for q correction */
57 #define	AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_M	0x000007E0	/* Mask for sin_theta for i correction */
58 #define	AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S	5         	/* Shift for sin_theta for i correction */
59 #define	AR_PHY_TIMING_CTRL4_IQCORR_ENABLE	0x00000800	/* enable IQ correction */
60 #define	AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_M	0x0000F000	/* Mask for max number of samples (logarithmic) */
61 #define	AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S	12        	/* Shift for max number of samples */
62 #define	AR_PHY_TIMING_CTRL4_DO_IQCAL	0x00010000	/* perform IQ calibration */
63 
64 #define	AR_PHY_PAPD_PROBE	0x9930
65 #define	AR_PHY_PAPD_PROBE_POWERTX	0x00007E00
66 #define	AR_PHY_PAPD_PROBE_POWERTX_S	9
67 #define	AR_PHY_PAPD_PROBE_NEXT_TX	0x00008000	/* command to take next reading */
68 #define	AR_PHY_PAPD_PROBE_GAINF	0xFE000000
69 #define	AR_PHY_PAPD_PROBE_GAINF_S	25
70 
71 #define	AR_PHY_POWER_TX_RATE1		0x9934
72 #define	AR_PHY_POWER_TX_RATE2		0x9938
73 #define	AR_PHY_POWER_TX_RATE_MAX	0x993c
74 
75 #define	AR_PHY_FRAME_CTL	0x9944
76 #define	AR_PHY_FRAME_CTL_TX_CLIP	0x00000038
77 #define	AR_PHY_FRAME_CTL_TX_CLIP_S	3
78 #define AR_PHY_FRAME_CTL_ERR_SERV	0x20000000
79 #define AR_PHY_FRAME_CTL_ERR_SERV_S	29
80 
81 #define	AR_PHY_RADAR_0	0x9954	/* PHY radar detection settings */
82 #define	AR_PHY_RADAR_0_ENA	0x00000001	/* Enable radar detection */
83 
84 #define	AR_PHY_IQCAL_RES_PWR_MEAS_I	0x9c10	/*PHY IQ calibration results - power measurement for I */
85 #define	AR_PHY_IQCAL_RES_PWR_MEAS_Q	0x9c14	/*PHY IQ calibration results - power measurement for Q */
86 #define	AR_PHY_IQCAL_RES_IQ_CORR_MEAS	0x9c18	/*PHY IQ calibration results - IQ correlation measurement */
87 #define	AR_PHY_CURRENT_RSSI	0x9c1c	/* rssi of current frame being received */
88 
89 #define	AR5211_PHY_MODE	0xA200	/* Mode register */
90 #define	AR5211_PHY_MODE_OFDM	0x0	/* bit 0 = 0 for OFDM */
91 #define	AR5211_PHY_MODE_CCK	0x1	/* bit 0 = 1 for CCK */
92 #define	AR5211_PHY_MODE_RF5GHZ	0x0	/* bit 1 = 0 for 5 GHz */
93 #define	AR5211_PHY_MODE_RF2GHZ	0x2	/* bit 1 = 1 for 2.4 GHz */
94 
95 #endif /* _DEV_ATH_AR5211PHY_H */
96