1 /*- 2 * SPDX-License-Identifier: ISC 3 * 4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 5 * Copyright (c) 2002-2006 Atheros Communications, Inc. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 #include "opt_ah.h" 20 21 #include "ah.h" 22 #include "ah_internal.h" 23 24 #include "ar5211/ar5211.h" 25 #include "ar5211/ar5211reg.h" 26 #include "ar5211/ar5211desc.h" 27 28 /* 29 * Routines used to initialize and generated beacons for the AR5211/AR5311. 30 */ 31 32 /* 33 * Return the hardware NextTBTT in TSF 34 */ 35 uint64_t 36 ar5211GetNextTBTT(struct ath_hal *ah) 37 { 38 #define TU_TO_TSF(_tu) (((uint64_t)(_tu)) << 10) 39 return TU_TO_TSF(OS_REG_READ(ah, AR_TIMER0)); 40 #undef TU_TO_TSF 41 } 42 43 /* 44 * Initialize all of the hardware registers used to send beacons. 45 */ 46 void 47 ar5211SetBeaconTimers(struct ath_hal *ah, const HAL_BEACON_TIMERS *bt) 48 { 49 50 OS_REG_WRITE(ah, AR_TIMER0, bt->bt_nexttbtt); 51 OS_REG_WRITE(ah, AR_TIMER1, bt->bt_nextdba); 52 OS_REG_WRITE(ah, AR_TIMER2, bt->bt_nextswba); 53 OS_REG_WRITE(ah, AR_TIMER3, bt->bt_nextatim); 54 /* 55 * Set the Beacon register after setting all timers. 56 */ 57 OS_REG_WRITE(ah, AR_BEACON, bt->bt_intval); 58 } 59 60 /* 61 * Legacy api to initialize all of the beacon registers. 62 */ 63 void 64 ar5211BeaconInit(struct ath_hal *ah, 65 uint32_t next_beacon, uint32_t beacon_period) 66 { 67 HAL_BEACON_TIMERS bt; 68 69 bt.bt_nexttbtt = next_beacon; 70 /* 71 * TIMER1: in AP/adhoc mode this controls the DMA beacon 72 * alert timer; otherwise it controls the next wakeup time. 73 * TIMER2: in AP mode, it controls the SBA beacon alert 74 * interrupt; otherwise it sets the start of the next CFP. 75 */ 76 switch (AH_PRIVATE(ah)->ah_opmode) { 77 case HAL_M_STA: 78 case HAL_M_MONITOR: 79 bt.bt_nextdba = 0xffff; 80 bt.bt_nextswba = 0x7ffff; 81 break; 82 case HAL_M_IBSS: 83 case HAL_M_HOSTAP: 84 bt.bt_nextdba = (next_beacon - 85 ah->ah_config.ah_dma_beacon_response_time) << 3; /* 1/8 TU */ 86 bt.bt_nextswba = (next_beacon - 87 ah->ah_config.ah_sw_beacon_response_time) << 3; /* 1/8 TU */ 88 break; 89 } 90 /* 91 * Set the ATIM window 92 * Our hardware does not support an ATIM window of 0 93 * (beacons will not work). If the ATIM windows is 0, 94 * force it to 1. 95 */ 96 bt.bt_nextatim = next_beacon + 1; 97 bt.bt_intval = beacon_period & 98 (AR_BEACON_PERIOD | AR_BEACON_RESET_TSF | AR_BEACON_EN); 99 ar5211SetBeaconTimers(ah, &bt); 100 } 101 102 void 103 ar5211ResetStaBeaconTimers(struct ath_hal *ah) 104 { 105 uint32_t val; 106 107 OS_REG_WRITE(ah, AR_TIMER0, 0); /* no beacons */ 108 val = OS_REG_READ(ah, AR_STA_ID1); 109 val |= AR_STA_ID1_PWR_SAV; /* XXX */ 110 /* tell the h/w that the associated AP is not PCF capable */ 111 OS_REG_WRITE(ah, AR_STA_ID1, 112 val & ~(AR_STA_ID1_DEFAULT_ANTENNA | AR_STA_ID1_PCF)); 113 OS_REG_WRITE(ah, AR_BEACON, AR_BEACON_PERIOD); 114 } 115 116 /* 117 * Set all the beacon related bits on the h/w for stations 118 * i.e. initializes the corresponding h/w timers; 119 * also tells the h/w whether to anticipate PCF beacons 120 */ 121 void 122 ar5211SetStaBeaconTimers(struct ath_hal *ah, const HAL_BEACON_STATE *bs) 123 { 124 struct ath_hal_5211 *ahp = AH5211(ah); 125 126 HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: setting beacon timers\n", __func__); 127 128 HALASSERT(bs->bs_intval != 0); 129 /* if the AP will do PCF */ 130 if (bs->bs_cfpmaxduration != 0) { 131 /* tell the h/w that the associated AP is PCF capable */ 132 OS_REG_WRITE(ah, AR_STA_ID1, 133 OS_REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PCF); 134 135 /* set CFP_PERIOD(1.024ms) register */ 136 OS_REG_WRITE(ah, AR_CFP_PERIOD, bs->bs_cfpperiod); 137 138 /* set CFP_DUR(1.024ms) register to max cfp duration */ 139 OS_REG_WRITE(ah, AR_CFP_DUR, bs->bs_cfpmaxduration); 140 141 /* set TIMER2(128us) to anticipated time of next CFP */ 142 OS_REG_WRITE(ah, AR_TIMER2, bs->bs_cfpnext << 3); 143 } else { 144 /* tell the h/w that the associated AP is not PCF capable */ 145 OS_REG_WRITE(ah, AR_STA_ID1, 146 OS_REG_READ(ah, AR_STA_ID1) &~ AR_STA_ID1_PCF); 147 } 148 149 /* 150 * Set TIMER0(1.024ms) to the anticipated time of the next beacon. 151 */ 152 OS_REG_WRITE(ah, AR_TIMER0, bs->bs_nexttbtt); 153 154 /* 155 * Start the beacon timers by setting the BEACON register 156 * to the beacon interval; also write the tim offset which 157 * we should know by now. The code, in ar5211WriteAssocid, 158 * also sets the tim offset once the AID is known which can 159 * be left as such for now. 160 */ 161 OS_REG_WRITE(ah, AR_BEACON, 162 (OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_PERIOD|AR_BEACON_TIM)) 163 | SM(bs->bs_intval, AR_BEACON_PERIOD) 164 | SM(bs->bs_timoffset ? bs->bs_timoffset + 4 : 0, AR_BEACON_TIM) 165 ); 166 167 /* 168 * Configure the BMISS interrupt. Note that we 169 * assume the caller blocks interrupts while enabling 170 * the threshold. 171 */ 172 HALASSERT(bs->bs_bmissthreshold <= MS(0xffffffff, AR_RSSI_THR_BM_THR)); 173 ahp->ah_rssiThr = (ahp->ah_rssiThr &~ AR_RSSI_THR_BM_THR) 174 | SM(bs->bs_bmissthreshold, AR_RSSI_THR_BM_THR); 175 OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr); 176 177 /* 178 * Set the sleep duration in 1/8 TU's. 179 */ 180 #define SLEEP_SLOP 3 181 OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLDUR, 182 (bs->bs_sleepduration - SLEEP_SLOP) << 3); 183 #undef SLEEP_SLOP 184 } 185