1 /* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2006 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19 #include "opt_ah.h" 20 21 #include "ah.h" 22 #include "ah_internal.h" 23 #include "ah_devid.h" 24 25 #include "ar5211/ar5211.h" 26 #include "ar5211/ar5211reg.h" 27 #include "ar5211/ar5211phy.h" 28 29 #include "ah_eeprom_v3.h" 30 31 static HAL_BOOL ar5211GetChannelEdges(struct ath_hal *ah, 32 uint16_t flags, uint16_t *low, uint16_t *high); 33 static HAL_BOOL ar5211GetChipPowerLimits(struct ath_hal *ah, 34 struct ieee80211_channel *chan); 35 36 static void ar5211ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, 37 HAL_BOOL power_off); 38 static void ar5211DisablePCIE(struct ath_hal *ah); 39 40 static const struct ath_hal_private ar5211hal = {{ 41 .ah_magic = AR5211_MAGIC, 42 43 .ah_getRateTable = ar5211GetRateTable, 44 .ah_detach = ar5211Detach, 45 46 /* Reset Functions */ 47 .ah_reset = ar5211Reset, 48 .ah_phyDisable = ar5211PhyDisable, 49 .ah_disable = ar5211Disable, 50 .ah_configPCIE = ar5211ConfigPCIE, 51 .ah_disablePCIE = ar5211DisablePCIE, 52 .ah_setPCUConfig = ar5211SetPCUConfig, 53 .ah_perCalibration = ar5211PerCalibration, 54 .ah_perCalibrationN = ar5211PerCalibrationN, 55 .ah_resetCalValid = ar5211ResetCalValid, 56 .ah_setTxPowerLimit = ar5211SetTxPowerLimit, 57 .ah_getChanNoise = ath_hal_getChanNoise, 58 59 /* Transmit functions */ 60 .ah_updateTxTrigLevel = ar5211UpdateTxTrigLevel, 61 .ah_setupTxQueue = ar5211SetupTxQueue, 62 .ah_setTxQueueProps = ar5211SetTxQueueProps, 63 .ah_getTxQueueProps = ar5211GetTxQueueProps, 64 .ah_releaseTxQueue = ar5211ReleaseTxQueue, 65 .ah_resetTxQueue = ar5211ResetTxQueue, 66 .ah_getTxDP = ar5211GetTxDP, 67 .ah_setTxDP = ar5211SetTxDP, 68 .ah_numTxPending = ar5211NumTxPending, 69 .ah_startTxDma = ar5211StartTxDma, 70 .ah_stopTxDma = ar5211StopTxDma, 71 .ah_setupTxDesc = ar5211SetupTxDesc, 72 .ah_setupXTxDesc = ar5211SetupXTxDesc, 73 .ah_fillTxDesc = ar5211FillTxDesc, 74 .ah_procTxDesc = ar5211ProcTxDesc, 75 .ah_getTxIntrQueue = ar5211GetTxIntrQueue, 76 .ah_reqTxIntrDesc = ar5211IntrReqTxDesc, 77 .ah_getTxCompletionRates = ar5211GetTxCompletionRates, 78 .ah_setTxDescLink = ar5211SetTxDescLink, 79 .ah_getTxDescLink = ar5211GetTxDescLink, 80 .ah_getTxDescLinkPtr = ar5211GetTxDescLinkPtr, 81 82 /* RX Functions */ 83 .ah_getRxDP = ar5211GetRxDP, 84 .ah_setRxDP = ar5211SetRxDP, 85 .ah_enableReceive = ar5211EnableReceive, 86 .ah_stopDmaReceive = ar5211StopDmaReceive, 87 .ah_startPcuReceive = ar5211StartPcuReceive, 88 .ah_stopPcuReceive = ar5211StopPcuReceive, 89 .ah_setMulticastFilter = ar5211SetMulticastFilter, 90 .ah_setMulticastFilterIndex = ar5211SetMulticastFilterIndex, 91 .ah_clrMulticastFilterIndex = ar5211ClrMulticastFilterIndex, 92 .ah_getRxFilter = ar5211GetRxFilter, 93 .ah_setRxFilter = ar5211SetRxFilter, 94 .ah_setupRxDesc = ar5211SetupRxDesc, 95 .ah_procRxDesc = ar5211ProcRxDesc, 96 .ah_rxMonitor = ar5211RxMonitor, 97 .ah_aniPoll = ar5211AniPoll, 98 .ah_procMibEvent = ar5211MibEvent, 99 100 /* Misc Functions */ 101 .ah_getCapability = ar5211GetCapability, 102 .ah_setCapability = ar5211SetCapability, 103 .ah_getDiagState = ar5211GetDiagState, 104 .ah_getMacAddress = ar5211GetMacAddress, 105 .ah_setMacAddress = ar5211SetMacAddress, 106 .ah_getBssIdMask = ar5211GetBssIdMask, 107 .ah_setBssIdMask = ar5211SetBssIdMask, 108 .ah_setRegulatoryDomain = ar5211SetRegulatoryDomain, 109 .ah_setLedState = ar5211SetLedState, 110 .ah_writeAssocid = ar5211WriteAssocid, 111 .ah_gpioCfgInput = ar5211GpioCfgInput, 112 .ah_gpioCfgOutput = ar5211GpioCfgOutput, 113 .ah_gpioGet = ar5211GpioGet, 114 .ah_gpioSet = ar5211GpioSet, 115 .ah_gpioSetIntr = ar5211GpioSetIntr, 116 .ah_getTsf32 = ar5211GetTsf32, 117 .ah_getTsf64 = ar5211GetTsf64, 118 .ah_resetTsf = ar5211ResetTsf, 119 .ah_detectCardPresent = ar5211DetectCardPresent, 120 .ah_updateMibCounters = ar5211UpdateMibCounters, 121 .ah_getRfGain = ar5211GetRfgain, 122 .ah_getDefAntenna = ar5211GetDefAntenna, 123 .ah_setDefAntenna = ar5211SetDefAntenna, 124 .ah_getAntennaSwitch = ar5211GetAntennaSwitch, 125 .ah_setAntennaSwitch = ar5211SetAntennaSwitch, 126 .ah_setSifsTime = ar5211SetSifsTime, 127 .ah_getSifsTime = ar5211GetSifsTime, 128 .ah_setSlotTime = ar5211SetSlotTime, 129 .ah_getSlotTime = ar5211GetSlotTime, 130 .ah_setAckTimeout = ar5211SetAckTimeout, 131 .ah_getAckTimeout = ar5211GetAckTimeout, 132 .ah_setAckCTSRate = ar5211SetAckCTSRate, 133 .ah_getAckCTSRate = ar5211GetAckCTSRate, 134 .ah_setCTSTimeout = ar5211SetCTSTimeout, 135 .ah_getCTSTimeout = ar5211GetCTSTimeout, 136 .ah_setDecompMask = ar5211SetDecompMask, 137 .ah_setCoverageClass = ar5211SetCoverageClass, 138 .ah_setQuiet = ar5211SetQuiet, 139 .ah_get11nExtBusy = ar5211Get11nExtBusy, 140 .ah_getMibCycleCounts = ar5211GetMibCycleCounts, 141 .ah_setChainMasks = ar5211SetChainMasks, 142 .ah_enableDfs = ar5211EnableDfs, 143 .ah_getDfsThresh = ar5211GetDfsThresh, 144 /* XXX procRadarEvent */ 145 /* XXX isFastClockEnabled */ 146 147 /* Key Cache Functions */ 148 .ah_getKeyCacheSize = ar5211GetKeyCacheSize, 149 .ah_resetKeyCacheEntry = ar5211ResetKeyCacheEntry, 150 .ah_isKeyCacheEntryValid = ar5211IsKeyCacheEntryValid, 151 .ah_setKeyCacheEntry = ar5211SetKeyCacheEntry, 152 .ah_setKeyCacheEntryMac = ar5211SetKeyCacheEntryMac, 153 154 /* Power Management Functions */ 155 .ah_setPowerMode = ar5211SetPowerMode, 156 .ah_getPowerMode = ar5211GetPowerMode, 157 158 /* Beacon Functions */ 159 .ah_setBeaconTimers = ar5211SetBeaconTimers, 160 .ah_beaconInit = ar5211BeaconInit, 161 .ah_setStationBeaconTimers = ar5211SetStaBeaconTimers, 162 .ah_resetStationBeaconTimers = ar5211ResetStaBeaconTimers, 163 .ah_getNextTBTT = ar5211GetNextTBTT, 164 165 /* Interrupt Functions */ 166 .ah_isInterruptPending = ar5211IsInterruptPending, 167 .ah_getPendingInterrupts = ar5211GetPendingInterrupts, 168 .ah_getInterrupts = ar5211GetInterrupts, 169 .ah_setInterrupts = ar5211SetInterrupts }, 170 171 .ah_getChannelEdges = ar5211GetChannelEdges, 172 .ah_getWirelessModes = ar5211GetWirelessModes, 173 .ah_eepromRead = ar5211EepromRead, 174 #ifdef AH_SUPPORT_WRITE_EEPROM 175 .ah_eepromWrite = ar5211EepromWrite, 176 #endif 177 .ah_getChipPowerLimits = ar5211GetChipPowerLimits, 178 }; 179 180 static HAL_BOOL ar5211ChipTest(struct ath_hal *); 181 static HAL_BOOL ar5211FillCapabilityInfo(struct ath_hal *ah); 182 183 /* 184 * Return the revsion id for the radio chip. This 185 * fetched via the PHY. 186 */ 187 static uint32_t 188 ar5211GetRadioRev(struct ath_hal *ah) 189 { 190 uint32_t val; 191 int i; 192 193 OS_REG_WRITE(ah, (AR_PHY_BASE + (0x34 << 2)), 0x00001c16); 194 for (i = 0; i < 8; i++) 195 OS_REG_WRITE(ah, (AR_PHY_BASE + (0x20 << 2)), 0x00010000); 196 val = (OS_REG_READ(ah, AR_PHY_BASE + (256 << 2)) >> 24) & 0xff; 197 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 198 return ath_hal_reverseBits(val, 8); 199 } 200 201 /* 202 * Attach for an AR5211 part. 203 */ 204 static struct ath_hal * 205 ar5211Attach(uint16_t devid, HAL_SOFTC sc, 206 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 207 HAL_OPS_CONFIG *ah_config, HAL_STATUS *status) 208 { 209 #define N(a) (sizeof(a)/sizeof(a[0])) 210 struct ath_hal_5211 *ahp; 211 struct ath_hal *ah; 212 uint32_t val; 213 uint16_t eeval; 214 HAL_STATUS ecode; 215 216 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 217 __func__, sc, (void*) st, (void*) sh); 218 219 /* NB: memory is returned zero'd */ 220 ahp = ath_hal_malloc(sizeof (struct ath_hal_5211)); 221 if (ahp == AH_NULL) { 222 HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 223 "%s: cannot allocate memory for state block\n", __func__); 224 ecode = HAL_ENOMEM; 225 goto bad; 226 } 227 ah = &ahp->ah_priv.h; 228 /* set initial values */ 229 OS_MEMCPY(&ahp->ah_priv, &ar5211hal, sizeof(struct ath_hal_private)); 230 ah->ah_sc = sc; 231 ah->ah_st = st; 232 ah->ah_sh = sh; 233 234 ah->ah_devid = devid; /* NB: for AH_DEBUG_ALQ */ 235 AH_PRIVATE(ah)->ah_devid = devid; 236 AH_PRIVATE(ah)->ah_subvendorid = 0; /* XXX */ 237 238 AH_PRIVATE(ah)->ah_powerLimit = MAX_RATE_POWER; 239 AH_PRIVATE(ah)->ah_tpScale = HAL_TP_SCALE_MAX; /* no scaling */ 240 241 ahp->ah_diversityControl = HAL_ANT_VARIABLE; 242 ahp->ah_staId1Defaults = 0; 243 ahp->ah_rssiThr = INIT_RSSI_THR; 244 ahp->ah_sifstime = (u_int) -1; 245 ahp->ah_slottime = (u_int) -1; 246 ahp->ah_acktimeout = (u_int) -1; 247 ahp->ah_ctstimeout = (u_int) -1; 248 249 if (!ar5211ChipReset(ah, AH_NULL)) { /* reset chip */ 250 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 251 ecode = HAL_EIO; 252 goto bad; 253 } 254 if (AH_PRIVATE(ah)->ah_devid == AR5211_FPGA11B) { 255 /* set it back to OFDM mode to be able to read analog rev id */ 256 OS_REG_WRITE(ah, AR5211_PHY_MODE, AR5211_PHY_MODE_OFDM); 257 OS_REG_WRITE(ah, AR_PHY_PLL_CTL, AR_PHY_PLL_CTL_44); 258 OS_DELAY(1000); 259 } 260 261 /* Read Revisions from Chips */ 262 val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID_M; 263 AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S; 264 AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION_M; 265 266 if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_MAUI_2 || 267 AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_OAHU) { 268 HALDEBUG(ah, HAL_DEBUG_ANY, 269 "%s: Mac Chip Rev 0x%x is not supported by this driver\n", 270 __func__, AH_PRIVATE(ah)->ah_macVersion); 271 ecode = HAL_ENOTSUPP; 272 goto bad; 273 } 274 275 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 276 277 if (!ar5211ChipTest(ah)) { 278 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 279 __func__); 280 ecode = HAL_ESELFTEST; 281 goto bad; 282 } 283 284 /* Set correct Baseband to analog shift setting to access analog chips. */ 285 if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_OAHU) { 286 OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000007); 287 } else { 288 OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000047); 289 } 290 OS_DELAY(2000); 291 292 /* Read Radio Chip Rev Extract */ 293 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5211GetRadioRev(ah); 294 if ((AH_PRIVATE(ah)->ah_analog5GhzRev & 0xf0) != RAD5_SREV_MAJOR) { 295 HALDEBUG(ah, HAL_DEBUG_ANY, 296 "%s: 5G Radio Chip Rev 0x%02X is not supported by this " 297 "driver\n", __func__, AH_PRIVATE(ah)->ah_analog5GhzRev); 298 ecode = HAL_ENOTSUPP; 299 goto bad; 300 } 301 302 val = (OS_REG_READ(ah, AR_PCICFG) & AR_PCICFG_EEPROM_SIZE_M) >> 303 AR_PCICFG_EEPROM_SIZE_S; 304 if (val != AR_PCICFG_EEPROM_SIZE_16K) { 305 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unsupported EEPROM size " 306 "%u (0x%x) found\n", __func__, val, val); 307 ecode = HAL_EESIZE; 308 goto bad; 309 } 310 ecode = ath_hal_legacyEepromAttach(ah); 311 if (ecode != HAL_OK) { 312 goto bad; 313 } 314 315 /* If Bmode and AR5211, verify 2.4 analog exists */ 316 if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_OAHU && 317 ath_hal_eepromGetFlag(ah, AR_EEP_BMODE)) { 318 /* Set correct Baseband to analog shift setting to access analog chips. */ 319 OS_REG_WRITE(ah, AR_PHY_BASE, 0x00004007); 320 OS_DELAY(2000); 321 AH_PRIVATE(ah)->ah_analog2GhzRev = ar5211GetRadioRev(ah); 322 323 /* Set baseband for 5GHz chip */ 324 OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000007); 325 OS_DELAY(2000); 326 if ((AH_PRIVATE(ah)->ah_analog2GhzRev & 0xF0) != RAD2_SREV_MAJOR) { 327 HALDEBUG(ah, HAL_DEBUG_ANY, 328 "%s: 2G Radio Chip Rev 0x%x is not supported by " 329 "this driver\n", __func__, 330 AH_PRIVATE(ah)->ah_analog2GhzRev); 331 ecode = HAL_ENOTSUPP; 332 goto bad; 333 } 334 } else { 335 ath_hal_eepromSet(ah, AR_EEP_BMODE, AH_FALSE); 336 } 337 338 ecode = ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, &eeval); 339 if (ecode != HAL_OK) { 340 HALDEBUG(ah, HAL_DEBUG_ANY, 341 "%s: cannot read regulatory domain from EEPROM\n", 342 __func__); 343 goto bad; 344 } 345 AH_PRIVATE(ah)->ah_currentRD = eeval; 346 AH_PRIVATE(ah)->ah_getNfAdjust = ar5211GetNfAdjust; 347 348 /* 349 * Got everything we need now to setup the capabilities. 350 */ 351 (void) ar5211FillCapabilityInfo(ah); 352 353 /* Initialize gain ladder thermal calibration structure */ 354 ar5211InitializeGainValues(ah); 355 356 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 357 if (ecode != HAL_OK) { 358 HALDEBUG(ah, HAL_DEBUG_ANY, 359 "%s: error getting mac address from EEPROM\n", __func__); 360 goto bad; 361 } 362 363 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 364 365 return ah; 366 bad: 367 if (ahp) 368 ar5211Detach((struct ath_hal *) ahp); 369 if (status) 370 *status = ecode; 371 return AH_NULL; 372 #undef N 373 } 374 375 void 376 ar5211Detach(struct ath_hal *ah) 377 { 378 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__); 379 380 HALASSERT(ah != AH_NULL); 381 HALASSERT(ah->ah_magic == AR5211_MAGIC); 382 383 ath_hal_eepromDetach(ah); 384 ath_hal_free(ah); 385 } 386 387 static HAL_BOOL 388 ar5211ChipTest(struct ath_hal *ah) 389 { 390 uint32_t regAddr[2] = { AR_STA_ID0, AR_PHY_BASE+(8 << 2) }; 391 uint32_t regHold[2]; 392 uint32_t patternData[4] = 393 { 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 }; 394 int i, j; 395 396 /* Test PHY & MAC registers */ 397 for (i = 0; i < 2; i++) { 398 uint32_t addr = regAddr[i]; 399 uint32_t wrData, rdData; 400 401 regHold[i] = OS_REG_READ(ah, addr); 402 for (j = 0; j < 0x100; j++) { 403 wrData = (j << 16) | j; 404 OS_REG_WRITE(ah, addr, wrData); 405 rdData = OS_REG_READ(ah, addr); 406 if (rdData != wrData) { 407 HALDEBUG(ah, HAL_DEBUG_ANY, 408 "%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 409 __func__, addr, wrData, rdData); 410 return AH_FALSE; 411 } 412 } 413 for (j = 0; j < 4; j++) { 414 wrData = patternData[j]; 415 OS_REG_WRITE(ah, addr, wrData); 416 rdData = OS_REG_READ(ah, addr); 417 if (wrData != rdData) { 418 HALDEBUG(ah, HAL_DEBUG_ANY, 419 "%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 420 __func__, addr, wrData, rdData); 421 return AH_FALSE; 422 } 423 } 424 OS_REG_WRITE(ah, regAddr[i], regHold[i]); 425 } 426 OS_DELAY(100); 427 return AH_TRUE; 428 } 429 430 /* 431 * Store the channel edges for the requested operational mode 432 */ 433 static HAL_BOOL 434 ar5211GetChannelEdges(struct ath_hal *ah, 435 uint16_t flags, uint16_t *low, uint16_t *high) 436 { 437 if (flags & IEEE80211_CHAN_5GHZ) { 438 *low = 4920; 439 *high = 6100; 440 return AH_TRUE; 441 } 442 if (flags & IEEE80211_CHAN_2GHZ && 443 ath_hal_eepromGetFlag(ah, AR_EEP_BMODE)) { 444 *low = 2312; 445 *high = 2732; 446 return AH_TRUE; 447 } 448 return AH_FALSE; 449 } 450 451 static HAL_BOOL 452 ar5211GetChipPowerLimits(struct ath_hal *ah, struct ieee80211_channel *chan) 453 { 454 /* XXX fill in, this is just a placeholder */ 455 HALDEBUG(ah, HAL_DEBUG_ATTACH, 456 "%s: no min/max power for %u/0x%x\n", 457 __func__, chan->ic_freq, chan->ic_flags); 458 chan->ic_maxpower = MAX_RATE_POWER; 459 chan->ic_minpower = 0; 460 return AH_TRUE; 461 } 462 463 static void 464 ar5211ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off) 465 { 466 } 467 468 static void 469 ar5211DisablePCIE(struct ath_hal *ah) 470 { 471 } 472 473 /* 474 * Fill all software cached or static hardware state information. 475 */ 476 static HAL_BOOL 477 ar5211FillCapabilityInfo(struct ath_hal *ah) 478 { 479 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 480 HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 481 482 /* Construct wireless mode from EEPROM */ 483 pCap->halWirelessModes = 0; 484 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) { 485 pCap->halWirelessModes |= HAL_MODE_11A; 486 if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO5DISABLE)) 487 pCap->halWirelessModes |= HAL_MODE_TURBO; 488 } 489 if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE)) 490 pCap->halWirelessModes |= HAL_MODE_11B; 491 492 pCap->halLow2GhzChan = 2312; 493 pCap->halHigh2GhzChan = 2732; 494 pCap->halLow5GhzChan = 4920; 495 pCap->halHigh5GhzChan = 6100; 496 497 pCap->halChanSpreadSupport = AH_TRUE; 498 pCap->halSleepAfterBeaconBroken = AH_TRUE; 499 pCap->halPSPollBroken = AH_TRUE; 500 pCap->halVEOLSupport = AH_TRUE; 501 pCap->halNumMRRetries = 1; /* No hardware MRR support */ 502 pCap->halNumTxMaps = 1; /* Single TX ptr per descr */ 503 504 pCap->halTotalQueues = HAL_NUM_TX_QUEUES; 505 pCap->halKeyCacheSize = 128; 506 507 /* XXX not needed */ 508 pCap->halChanHalfRate = AH_FALSE; 509 pCap->halChanQuarterRate = AH_FALSE; 510 511 /* 512 * RSSI uses the combined field; some 11n NICs may use 513 * the control chain RSSI. 514 */ 515 pCap->halUseCombinedRadarRssi = AH_TRUE; 516 517 if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) && 518 ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) { 519 /* NB: enabled by default */ 520 ahpriv->ah_rfkillEnabled = AH_TRUE; 521 pCap->halRfSilentSupport = AH_TRUE; 522 } 523 524 pCap->halRxTstampPrecision = 13; 525 pCap->halTxTstampPrecision = 16; 526 pCap->halIntrMask = HAL_INT_COMMON 527 | HAL_INT_RX 528 | HAL_INT_TX 529 | HAL_INT_FATAL 530 | HAL_INT_BNR 531 | HAL_INT_TIM 532 ; 533 534 pCap->hal4kbSplitTransSupport = AH_TRUE; 535 pCap->halHasRxSelfLinkedTail = AH_TRUE; 536 537 /* XXX might be ok w/ some chip revs */ 538 ahpriv->ah_rxornIsFatal = AH_TRUE; 539 return AH_TRUE; 540 } 541 542 static const char* 543 ar5211Probe(uint16_t vendorid, uint16_t devid) 544 { 545 if (vendorid == ATHEROS_VENDOR_ID) { 546 if (devid == AR5211_DEVID || devid == AR5311_DEVID || 547 devid == AR5211_DEFAULT) 548 return "Atheros 5211"; 549 if (devid == AR5211_FPGA11B) 550 return "Atheros 5211 (FPGA)"; 551 } 552 return AH_NULL; 553 } 554 AH_CHIP(AR5211, ar5211Probe, ar5211Attach); 555