1 /*- 2 * SPDX-License-Identifier: ISC 3 * 4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 5 * Copyright (c) 2002-2006 Atheros Communications, Inc. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 * 19 * $FreeBSD$ 20 */ 21 #include "opt_ah.h" 22 23 #include "ah.h" 24 #include "ah_internal.h" 25 #include "ah_devid.h" 26 27 #include "ar5211/ar5211.h" 28 #include "ar5211/ar5211reg.h" 29 #include "ar5211/ar5211phy.h" 30 31 #include "ah_eeprom_v3.h" 32 33 static HAL_BOOL ar5211GetChannelEdges(struct ath_hal *ah, 34 uint16_t flags, uint16_t *low, uint16_t *high); 35 static HAL_BOOL ar5211GetChipPowerLimits(struct ath_hal *ah, 36 struct ieee80211_channel *chan); 37 38 static void ar5211ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, 39 HAL_BOOL power_off); 40 static void ar5211DisablePCIE(struct ath_hal *ah); 41 42 static const struct ath_hal_private ar5211hal = {{ 43 .ah_magic = AR5211_MAGIC, 44 45 .ah_getRateTable = ar5211GetRateTable, 46 .ah_detach = ar5211Detach, 47 48 /* Reset Functions */ 49 .ah_reset = ar5211Reset, 50 .ah_phyDisable = ar5211PhyDisable, 51 .ah_disable = ar5211Disable, 52 .ah_configPCIE = ar5211ConfigPCIE, 53 .ah_disablePCIE = ar5211DisablePCIE, 54 .ah_setPCUConfig = ar5211SetPCUConfig, 55 .ah_perCalibration = ar5211PerCalibration, 56 .ah_perCalibrationN = ar5211PerCalibrationN, 57 .ah_resetCalValid = ar5211ResetCalValid, 58 .ah_setTxPowerLimit = ar5211SetTxPowerLimit, 59 .ah_getChanNoise = ath_hal_getChanNoise, 60 61 /* Transmit functions */ 62 .ah_updateTxTrigLevel = ar5211UpdateTxTrigLevel, 63 .ah_setupTxQueue = ar5211SetupTxQueue, 64 .ah_setTxQueueProps = ar5211SetTxQueueProps, 65 .ah_getTxQueueProps = ar5211GetTxQueueProps, 66 .ah_releaseTxQueue = ar5211ReleaseTxQueue, 67 .ah_resetTxQueue = ar5211ResetTxQueue, 68 .ah_getTxDP = ar5211GetTxDP, 69 .ah_setTxDP = ar5211SetTxDP, 70 .ah_numTxPending = ar5211NumTxPending, 71 .ah_startTxDma = ar5211StartTxDma, 72 .ah_stopTxDma = ar5211StopTxDma, 73 .ah_setupTxDesc = ar5211SetupTxDesc, 74 .ah_setupXTxDesc = ar5211SetupXTxDesc, 75 .ah_fillTxDesc = ar5211FillTxDesc, 76 .ah_procTxDesc = ar5211ProcTxDesc, 77 .ah_getTxIntrQueue = ar5211GetTxIntrQueue, 78 .ah_reqTxIntrDesc = ar5211IntrReqTxDesc, 79 .ah_getTxCompletionRates = ar5211GetTxCompletionRates, 80 .ah_setTxDescLink = ar5211SetTxDescLink, 81 .ah_getTxDescLink = ar5211GetTxDescLink, 82 .ah_getTxDescLinkPtr = ar5211GetTxDescLinkPtr, 83 84 /* RX Functions */ 85 .ah_getRxDP = ar5211GetRxDP, 86 .ah_setRxDP = ar5211SetRxDP, 87 .ah_enableReceive = ar5211EnableReceive, 88 .ah_stopDmaReceive = ar5211StopDmaReceive, 89 .ah_startPcuReceive = ar5211StartPcuReceive, 90 .ah_stopPcuReceive = ar5211StopPcuReceive, 91 .ah_setMulticastFilter = ar5211SetMulticastFilter, 92 .ah_setMulticastFilterIndex = ar5211SetMulticastFilterIndex, 93 .ah_clrMulticastFilterIndex = ar5211ClrMulticastFilterIndex, 94 .ah_getRxFilter = ar5211GetRxFilter, 95 .ah_setRxFilter = ar5211SetRxFilter, 96 .ah_setupRxDesc = ar5211SetupRxDesc, 97 .ah_procRxDesc = ar5211ProcRxDesc, 98 .ah_rxMonitor = ar5211RxMonitor, 99 .ah_aniPoll = ar5211AniPoll, 100 .ah_procMibEvent = ar5211MibEvent, 101 102 /* Misc Functions */ 103 .ah_getCapability = ar5211GetCapability, 104 .ah_setCapability = ar5211SetCapability, 105 .ah_getDiagState = ar5211GetDiagState, 106 .ah_getMacAddress = ar5211GetMacAddress, 107 .ah_setMacAddress = ar5211SetMacAddress, 108 .ah_getBssIdMask = ar5211GetBssIdMask, 109 .ah_setBssIdMask = ar5211SetBssIdMask, 110 .ah_setRegulatoryDomain = ar5211SetRegulatoryDomain, 111 .ah_setLedState = ar5211SetLedState, 112 .ah_writeAssocid = ar5211WriteAssocid, 113 .ah_gpioCfgInput = ar5211GpioCfgInput, 114 .ah_gpioCfgOutput = ar5211GpioCfgOutput, 115 .ah_gpioGet = ar5211GpioGet, 116 .ah_gpioSet = ar5211GpioSet, 117 .ah_gpioSetIntr = ar5211GpioSetIntr, 118 .ah_getTsf32 = ar5211GetTsf32, 119 .ah_getTsf64 = ar5211GetTsf64, 120 .ah_resetTsf = ar5211ResetTsf, 121 .ah_detectCardPresent = ar5211DetectCardPresent, 122 .ah_updateMibCounters = ar5211UpdateMibCounters, 123 .ah_getRfGain = ar5211GetRfgain, 124 .ah_getDefAntenna = ar5211GetDefAntenna, 125 .ah_setDefAntenna = ar5211SetDefAntenna, 126 .ah_getAntennaSwitch = ar5211GetAntennaSwitch, 127 .ah_setAntennaSwitch = ar5211SetAntennaSwitch, 128 .ah_setSifsTime = ar5211SetSifsTime, 129 .ah_getSifsTime = ar5211GetSifsTime, 130 .ah_setSlotTime = ar5211SetSlotTime, 131 .ah_getSlotTime = ar5211GetSlotTime, 132 .ah_setAckTimeout = ar5211SetAckTimeout, 133 .ah_getAckTimeout = ar5211GetAckTimeout, 134 .ah_setAckCTSRate = ar5211SetAckCTSRate, 135 .ah_getAckCTSRate = ar5211GetAckCTSRate, 136 .ah_setCTSTimeout = ar5211SetCTSTimeout, 137 .ah_getCTSTimeout = ar5211GetCTSTimeout, 138 .ah_setDecompMask = ar5211SetDecompMask, 139 .ah_setCoverageClass = ar5211SetCoverageClass, 140 .ah_setQuiet = ar5211SetQuiet, 141 .ah_get11nExtBusy = ar5211Get11nExtBusy, 142 .ah_getMibCycleCounts = ar5211GetMibCycleCounts, 143 .ah_setChainMasks = ar5211SetChainMasks, 144 .ah_enableDfs = ar5211EnableDfs, 145 .ah_getDfsThresh = ar5211GetDfsThresh, 146 /* XXX procRadarEvent */ 147 /* XXX isFastClockEnabled */ 148 149 /* Key Cache Functions */ 150 .ah_getKeyCacheSize = ar5211GetKeyCacheSize, 151 .ah_resetKeyCacheEntry = ar5211ResetKeyCacheEntry, 152 .ah_isKeyCacheEntryValid = ar5211IsKeyCacheEntryValid, 153 .ah_setKeyCacheEntry = ar5211SetKeyCacheEntry, 154 .ah_setKeyCacheEntryMac = ar5211SetKeyCacheEntryMac, 155 156 /* Power Management Functions */ 157 .ah_setPowerMode = ar5211SetPowerMode, 158 .ah_getPowerMode = ar5211GetPowerMode, 159 160 /* Beacon Functions */ 161 .ah_setBeaconTimers = ar5211SetBeaconTimers, 162 .ah_beaconInit = ar5211BeaconInit, 163 .ah_setStationBeaconTimers = ar5211SetStaBeaconTimers, 164 .ah_resetStationBeaconTimers = ar5211ResetStaBeaconTimers, 165 .ah_getNextTBTT = ar5211GetNextTBTT, 166 167 /* Interrupt Functions */ 168 .ah_isInterruptPending = ar5211IsInterruptPending, 169 .ah_getPendingInterrupts = ar5211GetPendingInterrupts, 170 .ah_getInterrupts = ar5211GetInterrupts, 171 .ah_setInterrupts = ar5211SetInterrupts }, 172 173 .ah_getChannelEdges = ar5211GetChannelEdges, 174 .ah_getWirelessModes = ar5211GetWirelessModes, 175 .ah_eepromRead = ar5211EepromRead, 176 #ifdef AH_SUPPORT_WRITE_EEPROM 177 .ah_eepromWrite = ar5211EepromWrite, 178 #endif 179 .ah_getChipPowerLimits = ar5211GetChipPowerLimits, 180 }; 181 182 static HAL_BOOL ar5211ChipTest(struct ath_hal *); 183 static HAL_BOOL ar5211FillCapabilityInfo(struct ath_hal *ah); 184 185 /* 186 * Return the revsion id for the radio chip. This 187 * fetched via the PHY. 188 */ 189 static uint32_t 190 ar5211GetRadioRev(struct ath_hal *ah) 191 { 192 uint32_t val; 193 int i; 194 195 OS_REG_WRITE(ah, (AR_PHY_BASE + (0x34 << 2)), 0x00001c16); 196 for (i = 0; i < 8; i++) 197 OS_REG_WRITE(ah, (AR_PHY_BASE + (0x20 << 2)), 0x00010000); 198 val = (OS_REG_READ(ah, AR_PHY_BASE + (256 << 2)) >> 24) & 0xff; 199 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 200 return ath_hal_reverseBits(val, 8); 201 } 202 203 /* 204 * Attach for an AR5211 part. 205 */ 206 static struct ath_hal * 207 ar5211Attach(uint16_t devid, HAL_SOFTC sc, 208 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 209 HAL_OPS_CONFIG *ah_config, HAL_STATUS *status) 210 { 211 #define N(a) (sizeof(a)/sizeof(a[0])) 212 struct ath_hal_5211 *ahp; 213 struct ath_hal *ah; 214 uint32_t val; 215 uint16_t eeval; 216 HAL_STATUS ecode; 217 218 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 219 __func__, sc, (void*) st, (void*) sh); 220 221 /* NB: memory is returned zero'd */ 222 ahp = ath_hal_malloc(sizeof (struct ath_hal_5211)); 223 if (ahp == AH_NULL) { 224 HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 225 "%s: cannot allocate memory for state block\n", __func__); 226 ecode = HAL_ENOMEM; 227 goto bad; 228 } 229 ah = &ahp->ah_priv.h; 230 /* set initial values */ 231 OS_MEMCPY(&ahp->ah_priv, &ar5211hal, sizeof(struct ath_hal_private)); 232 ah->ah_sc = sc; 233 ah->ah_st = st; 234 ah->ah_sh = sh; 235 236 ah->ah_devid = devid; /* NB: for AH_DEBUG_ALQ */ 237 AH_PRIVATE(ah)->ah_devid = devid; 238 AH_PRIVATE(ah)->ah_subvendorid = 0; /* XXX */ 239 240 AH_PRIVATE(ah)->ah_powerLimit = MAX_RATE_POWER; 241 AH_PRIVATE(ah)->ah_tpScale = HAL_TP_SCALE_MAX; /* no scaling */ 242 243 ahp->ah_diversityControl = HAL_ANT_VARIABLE; 244 ahp->ah_staId1Defaults = 0; 245 ahp->ah_rssiThr = INIT_RSSI_THR; 246 ahp->ah_sifstime = (u_int) -1; 247 ahp->ah_slottime = (u_int) -1; 248 ahp->ah_acktimeout = (u_int) -1; 249 ahp->ah_ctstimeout = (u_int) -1; 250 251 if (!ar5211ChipReset(ah, AH_NULL)) { /* reset chip */ 252 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 253 ecode = HAL_EIO; 254 goto bad; 255 } 256 if (AH_PRIVATE(ah)->ah_devid == AR5211_FPGA11B) { 257 /* set it back to OFDM mode to be able to read analog rev id */ 258 OS_REG_WRITE(ah, AR5211_PHY_MODE, AR5211_PHY_MODE_OFDM); 259 OS_REG_WRITE(ah, AR_PHY_PLL_CTL, AR_PHY_PLL_CTL_44); 260 OS_DELAY(1000); 261 } 262 263 /* Read Revisions from Chips */ 264 val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID_M; 265 AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S; 266 AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION_M; 267 268 if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_MAUI_2 || 269 AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_OAHU) { 270 HALDEBUG(ah, HAL_DEBUG_ANY, 271 "%s: Mac Chip Rev 0x%x is not supported by this driver\n", 272 __func__, AH_PRIVATE(ah)->ah_macVersion); 273 ecode = HAL_ENOTSUPP; 274 goto bad; 275 } 276 277 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 278 279 if (!ar5211ChipTest(ah)) { 280 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 281 __func__); 282 ecode = HAL_ESELFTEST; 283 goto bad; 284 } 285 286 /* Set correct Baseband to analog shift setting to access analog chips. */ 287 if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_OAHU) { 288 OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000007); 289 } else { 290 OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000047); 291 } 292 OS_DELAY(2000); 293 294 /* Read Radio Chip Rev Extract */ 295 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5211GetRadioRev(ah); 296 if ((AH_PRIVATE(ah)->ah_analog5GhzRev & 0xf0) != RAD5_SREV_MAJOR) { 297 HALDEBUG(ah, HAL_DEBUG_ANY, 298 "%s: 5G Radio Chip Rev 0x%02X is not supported by this " 299 "driver\n", __func__, AH_PRIVATE(ah)->ah_analog5GhzRev); 300 ecode = HAL_ENOTSUPP; 301 goto bad; 302 } 303 304 val = (OS_REG_READ(ah, AR_PCICFG) & AR_PCICFG_EEPROM_SIZE_M) >> 305 AR_PCICFG_EEPROM_SIZE_S; 306 if (val != AR_PCICFG_EEPROM_SIZE_16K) { 307 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unsupported EEPROM size " 308 "%u (0x%x) found\n", __func__, val, val); 309 ecode = HAL_EESIZE; 310 goto bad; 311 } 312 ecode = ath_hal_legacyEepromAttach(ah); 313 if (ecode != HAL_OK) { 314 goto bad; 315 } 316 317 /* If Bmode and AR5211, verify 2.4 analog exists */ 318 if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_OAHU && 319 ath_hal_eepromGetFlag(ah, AR_EEP_BMODE)) { 320 /* Set correct Baseband to analog shift setting to access analog chips. */ 321 OS_REG_WRITE(ah, AR_PHY_BASE, 0x00004007); 322 OS_DELAY(2000); 323 AH_PRIVATE(ah)->ah_analog2GhzRev = ar5211GetRadioRev(ah); 324 325 /* Set baseband for 5GHz chip */ 326 OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000007); 327 OS_DELAY(2000); 328 if ((AH_PRIVATE(ah)->ah_analog2GhzRev & 0xF0) != RAD2_SREV_MAJOR) { 329 HALDEBUG(ah, HAL_DEBUG_ANY, 330 "%s: 2G Radio Chip Rev 0x%x is not supported by " 331 "this driver\n", __func__, 332 AH_PRIVATE(ah)->ah_analog2GhzRev); 333 ecode = HAL_ENOTSUPP; 334 goto bad; 335 } 336 } else { 337 ath_hal_eepromSet(ah, AR_EEP_BMODE, AH_FALSE); 338 } 339 340 ecode = ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, &eeval); 341 if (ecode != HAL_OK) { 342 HALDEBUG(ah, HAL_DEBUG_ANY, 343 "%s: cannot read regulatory domain from EEPROM\n", 344 __func__); 345 goto bad; 346 } 347 AH_PRIVATE(ah)->ah_currentRD = eeval; 348 AH_PRIVATE(ah)->ah_getNfAdjust = ar5211GetNfAdjust; 349 350 /* 351 * Got everything we need now to setup the capabilities. 352 */ 353 (void) ar5211FillCapabilityInfo(ah); 354 355 /* Initialize gain ladder thermal calibration structure */ 356 ar5211InitializeGainValues(ah); 357 358 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 359 if (ecode != HAL_OK) { 360 HALDEBUG(ah, HAL_DEBUG_ANY, 361 "%s: error getting mac address from EEPROM\n", __func__); 362 goto bad; 363 } 364 365 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 366 367 return ah; 368 bad: 369 if (ahp) 370 ar5211Detach((struct ath_hal *) ahp); 371 if (status) 372 *status = ecode; 373 return AH_NULL; 374 #undef N 375 } 376 377 void 378 ar5211Detach(struct ath_hal *ah) 379 { 380 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__); 381 382 HALASSERT(ah != AH_NULL); 383 HALASSERT(ah->ah_magic == AR5211_MAGIC); 384 385 ath_hal_eepromDetach(ah); 386 ath_hal_free(ah); 387 } 388 389 static HAL_BOOL 390 ar5211ChipTest(struct ath_hal *ah) 391 { 392 uint32_t regAddr[2] = { AR_STA_ID0, AR_PHY_BASE+(8 << 2) }; 393 uint32_t regHold[2]; 394 uint32_t patternData[4] = 395 { 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 }; 396 int i, j; 397 398 /* Test PHY & MAC registers */ 399 for (i = 0; i < 2; i++) { 400 uint32_t addr = regAddr[i]; 401 uint32_t wrData, rdData; 402 403 regHold[i] = OS_REG_READ(ah, addr); 404 for (j = 0; j < 0x100; j++) { 405 wrData = (j << 16) | j; 406 OS_REG_WRITE(ah, addr, wrData); 407 rdData = OS_REG_READ(ah, addr); 408 if (rdData != wrData) { 409 HALDEBUG(ah, HAL_DEBUG_ANY, 410 "%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 411 __func__, addr, wrData, rdData); 412 return AH_FALSE; 413 } 414 } 415 for (j = 0; j < 4; j++) { 416 wrData = patternData[j]; 417 OS_REG_WRITE(ah, addr, wrData); 418 rdData = OS_REG_READ(ah, addr); 419 if (wrData != rdData) { 420 HALDEBUG(ah, HAL_DEBUG_ANY, 421 "%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 422 __func__, addr, wrData, rdData); 423 return AH_FALSE; 424 } 425 } 426 OS_REG_WRITE(ah, regAddr[i], regHold[i]); 427 } 428 OS_DELAY(100); 429 return AH_TRUE; 430 } 431 432 /* 433 * Store the channel edges for the requested operational mode 434 */ 435 static HAL_BOOL 436 ar5211GetChannelEdges(struct ath_hal *ah, 437 uint16_t flags, uint16_t *low, uint16_t *high) 438 { 439 if (flags & IEEE80211_CHAN_5GHZ) { 440 *low = 4920; 441 *high = 6100; 442 return AH_TRUE; 443 } 444 if (flags & IEEE80211_CHAN_2GHZ && 445 ath_hal_eepromGetFlag(ah, AR_EEP_BMODE)) { 446 *low = 2312; 447 *high = 2732; 448 return AH_TRUE; 449 } 450 return AH_FALSE; 451 } 452 453 static HAL_BOOL 454 ar5211GetChipPowerLimits(struct ath_hal *ah, struct ieee80211_channel *chan) 455 { 456 /* XXX fill in, this is just a placeholder */ 457 HALDEBUG(ah, HAL_DEBUG_ATTACH, 458 "%s: no min/max power for %u/0x%x\n", 459 __func__, chan->ic_freq, chan->ic_flags); 460 chan->ic_maxpower = MAX_RATE_POWER; 461 chan->ic_minpower = 0; 462 return AH_TRUE; 463 } 464 465 static void 466 ar5211ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off) 467 { 468 } 469 470 static void 471 ar5211DisablePCIE(struct ath_hal *ah) 472 { 473 } 474 475 /* 476 * Fill all software cached or static hardware state information. 477 */ 478 static HAL_BOOL 479 ar5211FillCapabilityInfo(struct ath_hal *ah) 480 { 481 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 482 HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 483 484 /* Construct wireless mode from EEPROM */ 485 pCap->halWirelessModes = 0; 486 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) { 487 pCap->halWirelessModes |= HAL_MODE_11A; 488 if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO5DISABLE)) 489 pCap->halWirelessModes |= HAL_MODE_TURBO; 490 } 491 if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE)) 492 pCap->halWirelessModes |= HAL_MODE_11B; 493 494 pCap->halLow2GhzChan = 2312; 495 pCap->halHigh2GhzChan = 2732; 496 pCap->halLow5GhzChan = 4920; 497 pCap->halHigh5GhzChan = 6100; 498 499 pCap->halChanSpreadSupport = AH_TRUE; 500 pCap->halSleepAfterBeaconBroken = AH_TRUE; 501 pCap->halPSPollBroken = AH_TRUE; 502 pCap->halVEOLSupport = AH_TRUE; 503 pCap->halNumMRRetries = 1; /* No hardware MRR support */ 504 pCap->halNumTxMaps = 1; /* Single TX ptr per descr */ 505 506 pCap->halTotalQueues = HAL_NUM_TX_QUEUES; 507 pCap->halKeyCacheSize = 128; 508 509 /* XXX not needed */ 510 pCap->halChanHalfRate = AH_FALSE; 511 pCap->halChanQuarterRate = AH_FALSE; 512 513 /* 514 * RSSI uses the combined field; some 11n NICs may use 515 * the control chain RSSI. 516 */ 517 pCap->halUseCombinedRadarRssi = AH_TRUE; 518 519 if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) && 520 ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) { 521 /* NB: enabled by default */ 522 ahpriv->ah_rfkillEnabled = AH_TRUE; 523 pCap->halRfSilentSupport = AH_TRUE; 524 } 525 526 pCap->halRxTstampPrecision = 13; 527 pCap->halTxTstampPrecision = 16; 528 pCap->halIntrMask = HAL_INT_COMMON 529 | HAL_INT_RX 530 | HAL_INT_TX 531 | HAL_INT_FATAL 532 | HAL_INT_BNR 533 | HAL_INT_TIM 534 ; 535 536 pCap->hal4kbSplitTransSupport = AH_TRUE; 537 pCap->halHasRxSelfLinkedTail = AH_TRUE; 538 539 /* XXX might be ok w/ some chip revs */ 540 ahpriv->ah_rxornIsFatal = AH_TRUE; 541 return AH_TRUE; 542 } 543 544 static const char* 545 ar5211Probe(uint16_t vendorid, uint16_t devid) 546 { 547 if (vendorid == ATHEROS_VENDOR_ID) { 548 if (devid == AR5211_DEVID || devid == AR5311_DEVID || 549 devid == AR5211_DEFAULT) 550 return "Atheros 5211"; 551 if (devid == AR5211_FPGA11B) 552 return "Atheros 5211 (FPGA)"; 553 } 554 return AH_NULL; 555 } 556 AH_CHIP(AR5211, ar5211Probe, ar5211Attach); 557