1 /* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2006 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19 #include "opt_ah.h" 20 21 #include "ah.h" 22 #include "ah_internal.h" 23 #include "ah_devid.h" 24 25 #include "ar5211/ar5211.h" 26 #include "ar5211/ar5211reg.h" 27 #include "ar5211/ar5211phy.h" 28 29 #include "ah_eeprom_v3.h" 30 31 static HAL_BOOL ar5211GetChannelEdges(struct ath_hal *ah, 32 uint16_t flags, uint16_t *low, uint16_t *high); 33 static HAL_BOOL ar5211GetChipPowerLimits(struct ath_hal *ah, 34 struct ieee80211_channel *chan); 35 36 static void ar5211ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, 37 HAL_BOOL power_off); 38 static void ar5211DisablePCIE(struct ath_hal *ah); 39 40 static const struct ath_hal_private ar5211hal = {{ 41 .ah_magic = AR5211_MAGIC, 42 43 .ah_getRateTable = ar5211GetRateTable, 44 .ah_detach = ar5211Detach, 45 46 /* Reset Functions */ 47 .ah_reset = ar5211Reset, 48 .ah_phyDisable = ar5211PhyDisable, 49 .ah_disable = ar5211Disable, 50 .ah_configPCIE = ar5211ConfigPCIE, 51 .ah_disablePCIE = ar5211DisablePCIE, 52 .ah_setPCUConfig = ar5211SetPCUConfig, 53 .ah_perCalibration = ar5211PerCalibration, 54 .ah_perCalibrationN = ar5211PerCalibrationN, 55 .ah_resetCalValid = ar5211ResetCalValid, 56 .ah_setTxPowerLimit = ar5211SetTxPowerLimit, 57 .ah_getChanNoise = ath_hal_getChanNoise, 58 59 /* Transmit functions */ 60 .ah_updateTxTrigLevel = ar5211UpdateTxTrigLevel, 61 .ah_setupTxQueue = ar5211SetupTxQueue, 62 .ah_setTxQueueProps = ar5211SetTxQueueProps, 63 .ah_getTxQueueProps = ar5211GetTxQueueProps, 64 .ah_releaseTxQueue = ar5211ReleaseTxQueue, 65 .ah_resetTxQueue = ar5211ResetTxQueue, 66 .ah_getTxDP = ar5211GetTxDP, 67 .ah_setTxDP = ar5211SetTxDP, 68 .ah_numTxPending = ar5211NumTxPending, 69 .ah_startTxDma = ar5211StartTxDma, 70 .ah_stopTxDma = ar5211StopTxDma, 71 .ah_setupTxDesc = ar5211SetupTxDesc, 72 .ah_setupXTxDesc = ar5211SetupXTxDesc, 73 .ah_fillTxDesc = ar5211FillTxDesc, 74 .ah_procTxDesc = ar5211ProcTxDesc, 75 .ah_getTxIntrQueue = ar5211GetTxIntrQueue, 76 .ah_reqTxIntrDesc = ar5211IntrReqTxDesc, 77 .ah_getTxCompletionRates = ar5211GetTxCompletionRates, 78 .ah_setTxDescLink = ar5211SetTxDescLink, 79 .ah_getTxDescLink = ar5211GetTxDescLink, 80 .ah_getTxDescLinkPtr = ar5211GetTxDescLinkPtr, 81 82 /* RX Functions */ 83 .ah_getRxDP = ar5211GetRxDP, 84 .ah_setRxDP = ar5211SetRxDP, 85 .ah_enableReceive = ar5211EnableReceive, 86 .ah_stopDmaReceive = ar5211StopDmaReceive, 87 .ah_startPcuReceive = ar5211StartPcuReceive, 88 .ah_stopPcuReceive = ar5211StopPcuReceive, 89 .ah_setMulticastFilter = ar5211SetMulticastFilter, 90 .ah_setMulticastFilterIndex = ar5211SetMulticastFilterIndex, 91 .ah_clrMulticastFilterIndex = ar5211ClrMulticastFilterIndex, 92 .ah_getRxFilter = ar5211GetRxFilter, 93 .ah_setRxFilter = ar5211SetRxFilter, 94 .ah_setupRxDesc = ar5211SetupRxDesc, 95 .ah_procRxDesc = ar5211ProcRxDesc, 96 .ah_rxMonitor = ar5211RxMonitor, 97 .ah_aniPoll = ar5211AniPoll, 98 .ah_procMibEvent = ar5211MibEvent, 99 100 /* Misc Functions */ 101 .ah_getCapability = ar5211GetCapability, 102 .ah_setCapability = ar5211SetCapability, 103 .ah_getDiagState = ar5211GetDiagState, 104 .ah_getMacAddress = ar5211GetMacAddress, 105 .ah_setMacAddress = ar5211SetMacAddress, 106 .ah_getBssIdMask = ar5211GetBssIdMask, 107 .ah_setBssIdMask = ar5211SetBssIdMask, 108 .ah_setRegulatoryDomain = ar5211SetRegulatoryDomain, 109 .ah_setLedState = ar5211SetLedState, 110 .ah_writeAssocid = ar5211WriteAssocid, 111 .ah_gpioCfgInput = ar5211GpioCfgInput, 112 .ah_gpioCfgOutput = ar5211GpioCfgOutput, 113 .ah_gpioGet = ar5211GpioGet, 114 .ah_gpioSet = ar5211GpioSet, 115 .ah_gpioSetIntr = ar5211GpioSetIntr, 116 .ah_getTsf32 = ar5211GetTsf32, 117 .ah_getTsf64 = ar5211GetTsf64, 118 .ah_resetTsf = ar5211ResetTsf, 119 .ah_detectCardPresent = ar5211DetectCardPresent, 120 .ah_updateMibCounters = ar5211UpdateMibCounters, 121 .ah_getRfGain = ar5211GetRfgain, 122 .ah_getDefAntenna = ar5211GetDefAntenna, 123 .ah_setDefAntenna = ar5211SetDefAntenna, 124 .ah_getAntennaSwitch = ar5211GetAntennaSwitch, 125 .ah_setAntennaSwitch = ar5211SetAntennaSwitch, 126 .ah_setSifsTime = ar5211SetSifsTime, 127 .ah_getSifsTime = ar5211GetSifsTime, 128 .ah_setSlotTime = ar5211SetSlotTime, 129 .ah_getSlotTime = ar5211GetSlotTime, 130 .ah_setAckTimeout = ar5211SetAckTimeout, 131 .ah_getAckTimeout = ar5211GetAckTimeout, 132 .ah_setAckCTSRate = ar5211SetAckCTSRate, 133 .ah_getAckCTSRate = ar5211GetAckCTSRate, 134 .ah_setCTSTimeout = ar5211SetCTSTimeout, 135 .ah_getCTSTimeout = ar5211GetCTSTimeout, 136 .ah_setDecompMask = ar5211SetDecompMask, 137 .ah_setCoverageClass = ar5211SetCoverageClass, 138 .ah_get11nExtBusy = ar5211Get11nExtBusy, 139 .ah_getMibCycleCounts = ar5211GetMibCycleCounts, 140 .ah_setChainMasks = ar5211SetChainMasks, 141 .ah_enableDfs = ar5211EnableDfs, 142 .ah_getDfsThresh = ar5211GetDfsThresh, 143 /* XXX procRadarEvent */ 144 /* XXX isFastClockEnabled */ 145 146 /* Key Cache Functions */ 147 .ah_getKeyCacheSize = ar5211GetKeyCacheSize, 148 .ah_resetKeyCacheEntry = ar5211ResetKeyCacheEntry, 149 .ah_isKeyCacheEntryValid = ar5211IsKeyCacheEntryValid, 150 .ah_setKeyCacheEntry = ar5211SetKeyCacheEntry, 151 .ah_setKeyCacheEntryMac = ar5211SetKeyCacheEntryMac, 152 153 /* Power Management Functions */ 154 .ah_setPowerMode = ar5211SetPowerMode, 155 .ah_getPowerMode = ar5211GetPowerMode, 156 157 /* Beacon Functions */ 158 .ah_setBeaconTimers = ar5211SetBeaconTimers, 159 .ah_beaconInit = ar5211BeaconInit, 160 .ah_setStationBeaconTimers = ar5211SetStaBeaconTimers, 161 .ah_resetStationBeaconTimers = ar5211ResetStaBeaconTimers, 162 .ah_getNextTBTT = ar5211GetNextTBTT, 163 164 /* Interrupt Functions */ 165 .ah_isInterruptPending = ar5211IsInterruptPending, 166 .ah_getPendingInterrupts = ar5211GetPendingInterrupts, 167 .ah_getInterrupts = ar5211GetInterrupts, 168 .ah_setInterrupts = ar5211SetInterrupts }, 169 170 .ah_getChannelEdges = ar5211GetChannelEdges, 171 .ah_getWirelessModes = ar5211GetWirelessModes, 172 .ah_eepromRead = ar5211EepromRead, 173 #ifdef AH_SUPPORT_WRITE_EEPROM 174 .ah_eepromWrite = ar5211EepromWrite, 175 #endif 176 .ah_getChipPowerLimits = ar5211GetChipPowerLimits, 177 }; 178 179 static HAL_BOOL ar5211ChipTest(struct ath_hal *); 180 static HAL_BOOL ar5211FillCapabilityInfo(struct ath_hal *ah); 181 182 /* 183 * Return the revsion id for the radio chip. This 184 * fetched via the PHY. 185 */ 186 static uint32_t 187 ar5211GetRadioRev(struct ath_hal *ah) 188 { 189 uint32_t val; 190 int i; 191 192 OS_REG_WRITE(ah, (AR_PHY_BASE + (0x34 << 2)), 0x00001c16); 193 for (i = 0; i < 8; i++) 194 OS_REG_WRITE(ah, (AR_PHY_BASE + (0x20 << 2)), 0x00010000); 195 val = (OS_REG_READ(ah, AR_PHY_BASE + (256 << 2)) >> 24) & 0xff; 196 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 197 return ath_hal_reverseBits(val, 8); 198 } 199 200 /* 201 * Attach for an AR5211 part. 202 */ 203 static struct ath_hal * 204 ar5211Attach(uint16_t devid, HAL_SOFTC sc, 205 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 206 HAL_OPS_CONFIG *ah_config, HAL_STATUS *status) 207 { 208 #define N(a) (sizeof(a)/sizeof(a[0])) 209 struct ath_hal_5211 *ahp; 210 struct ath_hal *ah; 211 uint32_t val; 212 uint16_t eeval; 213 HAL_STATUS ecode; 214 215 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 216 __func__, sc, (void*) st, (void*) sh); 217 218 /* NB: memory is returned zero'd */ 219 ahp = ath_hal_malloc(sizeof (struct ath_hal_5211)); 220 if (ahp == AH_NULL) { 221 HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 222 "%s: cannot allocate memory for state block\n", __func__); 223 ecode = HAL_ENOMEM; 224 goto bad; 225 } 226 ah = &ahp->ah_priv.h; 227 /* set initial values */ 228 OS_MEMCPY(&ahp->ah_priv, &ar5211hal, sizeof(struct ath_hal_private)); 229 ah->ah_sc = sc; 230 ah->ah_st = st; 231 ah->ah_sh = sh; 232 233 ah->ah_devid = devid; /* NB: for AH_DEBUG_ALQ */ 234 AH_PRIVATE(ah)->ah_devid = devid; 235 AH_PRIVATE(ah)->ah_subvendorid = 0; /* XXX */ 236 237 AH_PRIVATE(ah)->ah_powerLimit = MAX_RATE_POWER; 238 AH_PRIVATE(ah)->ah_tpScale = HAL_TP_SCALE_MAX; /* no scaling */ 239 240 ahp->ah_diversityControl = HAL_ANT_VARIABLE; 241 ahp->ah_staId1Defaults = 0; 242 ahp->ah_rssiThr = INIT_RSSI_THR; 243 ahp->ah_sifstime = (u_int) -1; 244 ahp->ah_slottime = (u_int) -1; 245 ahp->ah_acktimeout = (u_int) -1; 246 ahp->ah_ctstimeout = (u_int) -1; 247 248 if (!ar5211ChipReset(ah, AH_NULL)) { /* reset chip */ 249 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 250 ecode = HAL_EIO; 251 goto bad; 252 } 253 if (AH_PRIVATE(ah)->ah_devid == AR5211_FPGA11B) { 254 /* set it back to OFDM mode to be able to read analog rev id */ 255 OS_REG_WRITE(ah, AR5211_PHY_MODE, AR5211_PHY_MODE_OFDM); 256 OS_REG_WRITE(ah, AR_PHY_PLL_CTL, AR_PHY_PLL_CTL_44); 257 OS_DELAY(1000); 258 } 259 260 /* Read Revisions from Chips */ 261 val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID_M; 262 AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S; 263 AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION_M; 264 265 if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_MAUI_2 || 266 AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_OAHU) { 267 HALDEBUG(ah, HAL_DEBUG_ANY, 268 "%s: Mac Chip Rev 0x%x is not supported by this driver\n", 269 __func__, AH_PRIVATE(ah)->ah_macVersion); 270 ecode = HAL_ENOTSUPP; 271 goto bad; 272 } 273 274 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 275 276 if (!ar5211ChipTest(ah)) { 277 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 278 __func__); 279 ecode = HAL_ESELFTEST; 280 goto bad; 281 } 282 283 /* Set correct Baseband to analog shift setting to access analog chips. */ 284 if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_OAHU) { 285 OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000007); 286 } else { 287 OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000047); 288 } 289 OS_DELAY(2000); 290 291 /* Read Radio Chip Rev Extract */ 292 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5211GetRadioRev(ah); 293 if ((AH_PRIVATE(ah)->ah_analog5GhzRev & 0xf0) != RAD5_SREV_MAJOR) { 294 HALDEBUG(ah, HAL_DEBUG_ANY, 295 "%s: 5G Radio Chip Rev 0x%02X is not supported by this " 296 "driver\n", __func__, AH_PRIVATE(ah)->ah_analog5GhzRev); 297 ecode = HAL_ENOTSUPP; 298 goto bad; 299 } 300 301 val = (OS_REG_READ(ah, AR_PCICFG) & AR_PCICFG_EEPROM_SIZE_M) >> 302 AR_PCICFG_EEPROM_SIZE_S; 303 if (val != AR_PCICFG_EEPROM_SIZE_16K) { 304 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unsupported EEPROM size " 305 "%u (0x%x) found\n", __func__, val, val); 306 ecode = HAL_EESIZE; 307 goto bad; 308 } 309 ecode = ath_hal_legacyEepromAttach(ah); 310 if (ecode != HAL_OK) { 311 goto bad; 312 } 313 314 /* If Bmode and AR5211, verify 2.4 analog exists */ 315 if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_OAHU && 316 ath_hal_eepromGetFlag(ah, AR_EEP_BMODE)) { 317 /* Set correct Baseband to analog shift setting to access analog chips. */ 318 OS_REG_WRITE(ah, AR_PHY_BASE, 0x00004007); 319 OS_DELAY(2000); 320 AH_PRIVATE(ah)->ah_analog2GhzRev = ar5211GetRadioRev(ah); 321 322 /* Set baseband for 5GHz chip */ 323 OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000007); 324 OS_DELAY(2000); 325 if ((AH_PRIVATE(ah)->ah_analog2GhzRev & 0xF0) != RAD2_SREV_MAJOR) { 326 HALDEBUG(ah, HAL_DEBUG_ANY, 327 "%s: 2G Radio Chip Rev 0x%x is not supported by " 328 "this driver\n", __func__, 329 AH_PRIVATE(ah)->ah_analog2GhzRev); 330 ecode = HAL_ENOTSUPP; 331 goto bad; 332 } 333 } else { 334 ath_hal_eepromSet(ah, AR_EEP_BMODE, AH_FALSE); 335 } 336 337 ecode = ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, &eeval); 338 if (ecode != HAL_OK) { 339 HALDEBUG(ah, HAL_DEBUG_ANY, 340 "%s: cannot read regulatory domain from EEPROM\n", 341 __func__); 342 goto bad; 343 } 344 AH_PRIVATE(ah)->ah_currentRD = eeval; 345 AH_PRIVATE(ah)->ah_getNfAdjust = ar5211GetNfAdjust; 346 347 /* 348 * Got everything we need now to setup the capabilities. 349 */ 350 (void) ar5211FillCapabilityInfo(ah); 351 352 /* Initialize gain ladder thermal calibration structure */ 353 ar5211InitializeGainValues(ah); 354 355 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 356 if (ecode != HAL_OK) { 357 HALDEBUG(ah, HAL_DEBUG_ANY, 358 "%s: error getting mac address from EEPROM\n", __func__); 359 goto bad; 360 } 361 362 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 363 364 return ah; 365 bad: 366 if (ahp) 367 ar5211Detach((struct ath_hal *) ahp); 368 if (status) 369 *status = ecode; 370 return AH_NULL; 371 #undef N 372 } 373 374 void 375 ar5211Detach(struct ath_hal *ah) 376 { 377 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__); 378 379 HALASSERT(ah != AH_NULL); 380 HALASSERT(ah->ah_magic == AR5211_MAGIC); 381 382 ath_hal_eepromDetach(ah); 383 ath_hal_free(ah); 384 } 385 386 static HAL_BOOL 387 ar5211ChipTest(struct ath_hal *ah) 388 { 389 uint32_t regAddr[2] = { AR_STA_ID0, AR_PHY_BASE+(8 << 2) }; 390 uint32_t regHold[2]; 391 uint32_t patternData[4] = 392 { 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 }; 393 int i, j; 394 395 /* Test PHY & MAC registers */ 396 for (i = 0; i < 2; i++) { 397 uint32_t addr = regAddr[i]; 398 uint32_t wrData, rdData; 399 400 regHold[i] = OS_REG_READ(ah, addr); 401 for (j = 0; j < 0x100; j++) { 402 wrData = (j << 16) | j; 403 OS_REG_WRITE(ah, addr, wrData); 404 rdData = OS_REG_READ(ah, addr); 405 if (rdData != wrData) { 406 HALDEBUG(ah, HAL_DEBUG_ANY, 407 "%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 408 __func__, addr, wrData, rdData); 409 return AH_FALSE; 410 } 411 } 412 for (j = 0; j < 4; j++) { 413 wrData = patternData[j]; 414 OS_REG_WRITE(ah, addr, wrData); 415 rdData = OS_REG_READ(ah, addr); 416 if (wrData != rdData) { 417 HALDEBUG(ah, HAL_DEBUG_ANY, 418 "%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 419 __func__, addr, wrData, rdData); 420 return AH_FALSE; 421 } 422 } 423 OS_REG_WRITE(ah, regAddr[i], regHold[i]); 424 } 425 OS_DELAY(100); 426 return AH_TRUE; 427 } 428 429 /* 430 * Store the channel edges for the requested operational mode 431 */ 432 static HAL_BOOL 433 ar5211GetChannelEdges(struct ath_hal *ah, 434 uint16_t flags, uint16_t *low, uint16_t *high) 435 { 436 if (flags & IEEE80211_CHAN_5GHZ) { 437 *low = 4920; 438 *high = 6100; 439 return AH_TRUE; 440 } 441 if (flags & IEEE80211_CHAN_2GHZ && 442 ath_hal_eepromGetFlag(ah, AR_EEP_BMODE)) { 443 *low = 2312; 444 *high = 2732; 445 return AH_TRUE; 446 } 447 return AH_FALSE; 448 } 449 450 static HAL_BOOL 451 ar5211GetChipPowerLimits(struct ath_hal *ah, struct ieee80211_channel *chan) 452 { 453 /* XXX fill in, this is just a placeholder */ 454 HALDEBUG(ah, HAL_DEBUG_ATTACH, 455 "%s: no min/max power for %u/0x%x\n", 456 __func__, chan->ic_freq, chan->ic_flags); 457 chan->ic_maxpower = MAX_RATE_POWER; 458 chan->ic_minpower = 0; 459 return AH_TRUE; 460 } 461 462 static void 463 ar5211ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off) 464 { 465 } 466 467 static void 468 ar5211DisablePCIE(struct ath_hal *ah) 469 { 470 } 471 472 /* 473 * Fill all software cached or static hardware state information. 474 */ 475 static HAL_BOOL 476 ar5211FillCapabilityInfo(struct ath_hal *ah) 477 { 478 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 479 HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 480 481 /* Construct wireless mode from EEPROM */ 482 pCap->halWirelessModes = 0; 483 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) { 484 pCap->halWirelessModes |= HAL_MODE_11A; 485 if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO5DISABLE)) 486 pCap->halWirelessModes |= HAL_MODE_TURBO; 487 } 488 if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE)) 489 pCap->halWirelessModes |= HAL_MODE_11B; 490 491 pCap->halLow2GhzChan = 2312; 492 pCap->halHigh2GhzChan = 2732; 493 pCap->halLow5GhzChan = 4920; 494 pCap->halHigh5GhzChan = 6100; 495 496 pCap->halChanSpreadSupport = AH_TRUE; 497 pCap->halSleepAfterBeaconBroken = AH_TRUE; 498 pCap->halPSPollBroken = AH_TRUE; 499 pCap->halVEOLSupport = AH_TRUE; 500 pCap->halNumMRRetries = 1; /* No hardware MRR support */ 501 pCap->halNumTxMaps = 1; /* Single TX ptr per descr */ 502 503 pCap->halTotalQueues = HAL_NUM_TX_QUEUES; 504 pCap->halKeyCacheSize = 128; 505 506 /* XXX not needed */ 507 pCap->halChanHalfRate = AH_FALSE; 508 pCap->halChanQuarterRate = AH_FALSE; 509 510 /* 511 * RSSI uses the combined field; some 11n NICs may use 512 * the control chain RSSI. 513 */ 514 pCap->halUseCombinedRadarRssi = AH_TRUE; 515 516 if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) && 517 ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) { 518 /* NB: enabled by default */ 519 ahpriv->ah_rfkillEnabled = AH_TRUE; 520 pCap->halRfSilentSupport = AH_TRUE; 521 } 522 523 pCap->halTstampPrecision = 13; 524 pCap->halIntrMask = HAL_INT_COMMON 525 | HAL_INT_RX 526 | HAL_INT_TX 527 | HAL_INT_FATAL 528 | HAL_INT_BNR 529 | HAL_INT_TIM 530 ; 531 532 pCap->hal4kbSplitTransSupport = AH_TRUE; 533 pCap->halHasRxSelfLinkedTail = AH_TRUE; 534 535 /* XXX might be ok w/ some chip revs */ 536 ahpriv->ah_rxornIsFatal = AH_TRUE; 537 return AH_TRUE; 538 } 539 540 static const char* 541 ar5211Probe(uint16_t vendorid, uint16_t devid) 542 { 543 if (vendorid == ATHEROS_VENDOR_ID) { 544 if (devid == AR5211_DEVID || devid == AR5311_DEVID || 545 devid == AR5211_DEFAULT) 546 return "Atheros 5211"; 547 if (devid == AR5211_FPGA11B) 548 return "Atheros 5211 (FPGA)"; 549 } 550 return AH_NULL; 551 } 552 AH_CHIP(AR5211, ar5211Probe, ar5211Attach); 553