1 /*- 2 * SPDX-License-Identifier: ISC 3 * 4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 5 * Copyright (c) 2002-2004 Atheros Communications, Inc. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 * 19 * $FreeBSD$ 20 */ 21 #include "opt_ah.h" 22 23 #include "ah.h" 24 #include "ah_internal.h" 25 26 #include "ar5210/ar5210.h" 27 #include "ar5210/ar5210reg.h" 28 #include "ar5210/ar5210phy.h" 29 30 #include "ah_eeprom_v1.h" 31 32 typedef struct { 33 uint32_t Offset; 34 uint32_t Value; 35 } REGISTER_VAL; 36 37 static const REGISTER_VAL ar5k0007_init[] = { 38 #include "ar5210/ar5k_0007.ini" 39 }; 40 41 /* Default Power Settings for channels outside of EEPROM range */ 42 static const uint8_t ar5k0007_pwrSettings[17] = { 43 /* gain delta pc dac */ 44 /* 54 48 36 24 18 12 9 54 48 36 24 18 12 9 6 ob db */ 45 9, 9, 0, 0, 0, 0, 0, 2, 2, 6, 6, 6, 6, 6, 6, 2, 2 46 }; 47 48 /* 49 * The delay, in usecs, between writing AR_RC with a reset 50 * request and waiting for the chip to settle. If this is 51 * too short then the chip does not come out of sleep state. 52 * Note this value was empirically derived and may be dependent 53 * on the host machine (don't know--the problem was identified 54 * on an IBM 570e laptop; 10us delays worked on other systems). 55 */ 56 #define AR_RC_SETTLE_TIME 20000 57 58 static HAL_BOOL ar5210SetResetReg(struct ath_hal *, 59 uint32_t resetMask, u_int delay); 60 static HAL_BOOL ar5210SetChannel(struct ath_hal *, struct ieee80211_channel *); 61 static void ar5210SetOperatingMode(struct ath_hal *, int opmode); 62 63 /* 64 * Places the device in and out of reset and then places sane 65 * values in the registers based on EEPROM config, initialization 66 * vectors (as determined by the mode), and station configuration 67 * 68 * bChannelChange is used to preserve DMA/PCU registers across 69 * a HW Reset during channel change. 70 */ 71 HAL_BOOL 72 ar5210Reset(struct ath_hal *ah, HAL_OPMODE opmode, 73 struct ieee80211_channel *chan, HAL_BOOL bChannelChange, 74 HAL_RESET_TYPE resetType, 75 HAL_STATUS *status) 76 { 77 #define N(a) (sizeof (a) /sizeof (a[0])) 78 #define FAIL(_code) do { ecode = _code; goto bad; } while (0) 79 struct ath_hal_5210 *ahp = AH5210(ah); 80 const HAL_EEPROM_v1 *ee = AH_PRIVATE(ah)->ah_eeprom; 81 HAL_CHANNEL_INTERNAL *ichan; 82 HAL_STATUS ecode; 83 uint32_t ledstate; 84 int i, q; 85 86 HALDEBUG(ah, HAL_DEBUG_RESET, 87 "%s: opmode %u channel %u/0x%x %s channel\n", __func__, 88 opmode, chan->ic_freq, chan->ic_flags, 89 bChannelChange ? "change" : "same"); 90 91 if (!IEEE80211_IS_CHAN_5GHZ(chan)) { 92 /* Only 11a mode */ 93 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: channel not 5GHz\n", __func__); 94 FAIL(HAL_EINVAL); 95 } 96 /* 97 * Map public channel to private. 98 */ 99 ichan = ath_hal_checkchannel(ah, chan); 100 if (ichan == AH_NULL) { 101 HALDEBUG(ah, HAL_DEBUG_ANY, 102 "%s: invalid channel %u/0x%x; no mapping\n", 103 __func__, chan->ic_freq, chan->ic_flags); 104 FAIL(HAL_EINVAL); 105 } 106 switch (opmode) { 107 case HAL_M_STA: 108 case HAL_M_IBSS: 109 case HAL_M_HOSTAP: 110 case HAL_M_MONITOR: 111 break; 112 default: 113 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid operating mode %u\n", 114 __func__, opmode); 115 FAIL(HAL_EINVAL); 116 break; 117 } 118 119 ledstate = OS_REG_READ(ah, AR_PCICFG) & 120 (AR_PCICFG_LED_PEND | AR_PCICFG_LED_ACT); 121 122 if (!ar5210ChipReset(ah, chan)) { 123 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", 124 __func__); 125 FAIL(HAL_EIO); 126 } 127 128 OS_REG_WRITE(ah, AR_STA_ID0, LE_READ_4(ahp->ah_macaddr)); 129 OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4)); 130 ar5210SetOperatingMode(ah, opmode); 131 132 switch (opmode) { 133 case HAL_M_HOSTAP: 134 OS_REG_WRITE(ah, AR_BCR, INIT_BCON_CNTRL_REG); 135 OS_REG_WRITE(ah, AR_PCICFG, 136 AR_PCICFG_LED_ACT | AR_PCICFG_LED_BCTL); 137 break; 138 case HAL_M_IBSS: 139 OS_REG_WRITE(ah, AR_BCR, INIT_BCON_CNTRL_REG | AR_BCR_BCMD); 140 OS_REG_WRITE(ah, AR_PCICFG, 141 AR_PCICFG_CLKRUNEN | AR_PCICFG_LED_PEND | AR_PCICFG_LED_BCTL); 142 break; 143 case HAL_M_STA: 144 OS_REG_WRITE(ah, AR_BCR, INIT_BCON_CNTRL_REG); 145 OS_REG_WRITE(ah, AR_PCICFG, 146 AR_PCICFG_CLKRUNEN | AR_PCICFG_LED_PEND | AR_PCICFG_LED_BCTL); 147 break; 148 case HAL_M_MONITOR: 149 OS_REG_WRITE(ah, AR_BCR, INIT_BCON_CNTRL_REG); 150 OS_REG_WRITE(ah, AR_PCICFG, 151 AR_PCICFG_LED_ACT | AR_PCICFG_LED_BCTL); 152 break; 153 } 154 155 /* Restore previous led state */ 156 OS_REG_WRITE(ah, AR_PCICFG, OS_REG_READ(ah, AR_PCICFG) | ledstate); 157 158 #if 0 159 OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid)); 160 OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4)); 161 #endif 162 /* BSSID, association id, ps-poll */ 163 ar5210WriteAssocid(ah, ahp->ah_bssid, ahp->ah_associd); 164 165 OS_REG_WRITE(ah, AR_TXDP0, 0); 166 OS_REG_WRITE(ah, AR_TXDP1, 0); 167 OS_REG_WRITE(ah, AR_RXDP, 0); 168 169 /* 170 * Initialize interrupt state. 171 */ 172 (void) OS_REG_READ(ah, AR_ISR); /* cleared on read */ 173 OS_REG_WRITE(ah, AR_IMR, 0); 174 OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE); 175 ahp->ah_maskReg = 0; 176 177 (void) OS_REG_READ(ah, AR_BSR); /* cleared on read */ 178 OS_REG_WRITE(ah, AR_TXCFG, AR_DMASIZE_128B); 179 OS_REG_WRITE(ah, AR_RXCFG, AR_DMASIZE_128B); 180 181 OS_REG_WRITE(ah, AR_TOPS, 8); /* timeout prescale */ 182 OS_REG_WRITE(ah, AR_RXNOFRM, 8); /* RX no frame timeout */ 183 OS_REG_WRITE(ah, AR_RPGTO, 0); /* RX frame gap timeout */ 184 OS_REG_WRITE(ah, AR_TXNOFRM, 0); /* TX no frame timeout */ 185 186 OS_REG_WRITE(ah, AR_SFR, 0); 187 OS_REG_WRITE(ah, AR_MIBC, 0); /* unfreeze ctrs + clr state */ 188 OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr); 189 OS_REG_WRITE(ah, AR_CFP_DUR, 0); 190 191 ar5210SetRxFilter(ah, 0); /* nothing for now */ 192 OS_REG_WRITE(ah, AR_MCAST_FIL0, 0); /* multicast filter */ 193 OS_REG_WRITE(ah, AR_MCAST_FIL1, 0); /* XXX was 2 */ 194 195 OS_REG_WRITE(ah, AR_TX_MASK0, 0); 196 OS_REG_WRITE(ah, AR_TX_MASK1, 0); 197 OS_REG_WRITE(ah, AR_CLR_TMASK, 1); 198 OS_REG_WRITE(ah, AR_TRIG_LEV, 1); /* minimum */ 199 200 ar5210UpdateDiagReg(ah, 0); 201 202 OS_REG_WRITE(ah, AR_CFP_PERIOD, 0); 203 OS_REG_WRITE(ah, AR_TIMER0, 0); /* next beacon time */ 204 OS_REG_WRITE(ah, AR_TSF_L32, 0); /* local clock */ 205 OS_REG_WRITE(ah, AR_TIMER1, ~0); /* next DMA beacon alert */ 206 OS_REG_WRITE(ah, AR_TIMER2, ~0); /* next SW beacon alert */ 207 OS_REG_WRITE(ah, AR_TIMER3, 1); /* next ATIM window */ 208 209 /* Write the INI values for PHYreg initialization */ 210 for (i = 0; i < N(ar5k0007_init); i++) { 211 uint32_t reg = ar5k0007_init[i].Offset; 212 /* On channel change, don't reset the PCU registers */ 213 if (!(bChannelChange && (0x8000 <= reg && reg < 0x9000))) 214 OS_REG_WRITE(ah, reg, ar5k0007_init[i].Value); 215 } 216 217 /* Setup the transmit power values for cards since 0x0[0-2]05 */ 218 if (!ar5210SetTransmitPower(ah, chan)) { 219 HALDEBUG(ah, HAL_DEBUG_ANY, 220 "%s: error init'ing transmit power\n", __func__); 221 FAIL(HAL_EIO); 222 } 223 224 OS_REG_WRITE(ah, AR_PHY(10), 225 (OS_REG_READ(ah, AR_PHY(10)) & 0xFFFF00FF) | 226 (ee->ee_xlnaOn << 8)); 227 OS_REG_WRITE(ah, AR_PHY(13), 228 (ee->ee_xpaOff << 24) | (ee->ee_xpaOff << 16) | 229 (ee->ee_xpaOn << 8) | ee->ee_xpaOn); 230 OS_REG_WRITE(ah, AR_PHY(17), 231 (OS_REG_READ(ah, AR_PHY(17)) & 0xFFFFC07F) | 232 ((ee->ee_antenna >> 1) & 0x3F80)); 233 OS_REG_WRITE(ah, AR_PHY(18), 234 (OS_REG_READ(ah, AR_PHY(18)) & 0xFFFC0FFF) | 235 ((ee->ee_antenna << 10) & 0x3F000)); 236 OS_REG_WRITE(ah, AR_PHY(25), 237 (OS_REG_READ(ah, AR_PHY(25)) & 0xFFF80FFF) | 238 ((ee->ee_thresh62 << 12) & 0x7F000)); 239 OS_REG_WRITE(ah, AR_PHY(68), 240 (OS_REG_READ(ah, AR_PHY(68)) & 0xFFFFFFFC) | 241 (ee->ee_antenna & 0x3)); 242 243 if (!ar5210SetChannel(ah, chan)) { 244 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set channel\n", 245 __func__); 246 FAIL(HAL_EIO); 247 } 248 if (bChannelChange && !IEEE80211_IS_CHAN_DFS(chan)) 249 chan->ic_state &= ~IEEE80211_CHANSTATE_CWINT; 250 251 /* Activate the PHY */ 252 OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ENABLE); 253 254 OS_DELAY(1000); /* Wait a bit (1 msec) */ 255 256 /* calibrate the HW and poll the bit going to 0 for completion */ 257 OS_REG_WRITE(ah, AR_PHY_AGCCTL, 258 OS_REG_READ(ah, AR_PHY_AGCCTL) | AR_PHY_AGC_CAL); 259 (void) ath_hal_wait(ah, AR_PHY_AGCCTL, AR_PHY_AGC_CAL, 0); 260 261 /* Perform noise floor calibration and set status */ 262 if (!ar5210CalNoiseFloor(ah, ichan)) { 263 chan->ic_state |= IEEE80211_CHANSTATE_CWINT; 264 HALDEBUG(ah, HAL_DEBUG_ANY, 265 "%s: noise floor calibration failed\n", __func__); 266 FAIL(HAL_EIO); 267 } 268 269 for (q = 0; q < HAL_NUM_TX_QUEUES; q++) 270 ar5210ResetTxQueue(ah, q); 271 272 if (AH_PRIVATE(ah)->ah_rfkillEnabled) 273 ar5210EnableRfKill(ah); 274 275 /* 276 * Writing to AR_BEACON will start timers. Hence it should be 277 * the last register to be written. Do not reset tsf, do not 278 * enable beacons at this point, but preserve other values 279 * like beaconInterval. 280 */ 281 OS_REG_WRITE(ah, AR_BEACON, 282 (OS_REG_READ(ah, AR_BEACON) & 283 ~(AR_BEACON_EN | AR_BEACON_RESET_TSF))); 284 285 /* Restore user-specified slot time and timeouts */ 286 if (ahp->ah_sifstime != (u_int) -1) 287 ar5210SetSifsTime(ah, ahp->ah_sifstime); 288 if (ahp->ah_slottime != (u_int) -1) 289 ar5210SetSlotTime(ah, ahp->ah_slottime); 290 if (ahp->ah_acktimeout != (u_int) -1) 291 ar5210SetAckTimeout(ah, ahp->ah_acktimeout); 292 if (ahp->ah_ctstimeout != (u_int) -1) 293 ar5210SetCTSTimeout(ah, ahp->ah_ctstimeout); 294 if (AH_PRIVATE(ah)->ah_diagreg != 0) 295 ar5210UpdateDiagReg(ah, AH_PRIVATE(ah)->ah_diagreg); 296 297 AH_PRIVATE(ah)->ah_opmode = opmode; /* record operating mode */ 298 299 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: done\n", __func__); 300 301 return AH_TRUE; 302 bad: 303 if (status != AH_NULL) 304 *status = ecode; 305 return AH_FALSE; 306 #undef FAIL 307 #undef N 308 } 309 310 static void 311 ar5210SetOperatingMode(struct ath_hal *ah, int opmode) 312 { 313 struct ath_hal_5210 *ahp = AH5210(ah); 314 uint32_t val; 315 316 val = OS_REG_READ(ah, AR_STA_ID1) & 0xffff; 317 switch (opmode) { 318 case HAL_M_HOSTAP: 319 OS_REG_WRITE(ah, AR_STA_ID1, val 320 | AR_STA_ID1_AP 321 | AR_STA_ID1_NO_PSPOLL 322 | AR_STA_ID1_DESC_ANTENNA 323 | ahp->ah_staId1Defaults); 324 break; 325 case HAL_M_IBSS: 326 OS_REG_WRITE(ah, AR_STA_ID1, val 327 | AR_STA_ID1_ADHOC 328 | AR_STA_ID1_NO_PSPOLL 329 | AR_STA_ID1_DESC_ANTENNA 330 | ahp->ah_staId1Defaults); 331 break; 332 case HAL_M_STA: 333 OS_REG_WRITE(ah, AR_STA_ID1, val 334 | AR_STA_ID1_NO_PSPOLL 335 | AR_STA_ID1_PWR_SV 336 | ahp->ah_staId1Defaults); 337 break; 338 case HAL_M_MONITOR: 339 OS_REG_WRITE(ah, AR_STA_ID1, val 340 | AR_STA_ID1_NO_PSPOLL 341 | ahp->ah_staId1Defaults); 342 break; 343 } 344 } 345 346 void 347 ar5210SetPCUConfig(struct ath_hal *ah) 348 { 349 ar5210SetOperatingMode(ah, AH_PRIVATE(ah)->ah_opmode); 350 } 351 352 /* 353 * Places the PHY and Radio chips into reset. A full reset 354 * must be called to leave this state. The PCI/MAC/PCU are 355 * not placed into reset as we must receive interrupt to 356 * re-enable the hardware. 357 */ 358 HAL_BOOL 359 ar5210PhyDisable(struct ath_hal *ah) 360 { 361 return ar5210SetResetReg(ah, AR_RC_RPHY, 10); 362 } 363 364 /* 365 * Places all of hardware into reset 366 */ 367 HAL_BOOL 368 ar5210Disable(struct ath_hal *ah) 369 { 370 #define AR_RC_HW (AR_RC_RPCU | AR_RC_RDMA | AR_RC_RPHY | AR_RC_RMAC) 371 if (!ar5210SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 372 return AH_FALSE; 373 374 /* 375 * Reset the HW - PCI must be reset after the rest of the 376 * device has been reset 377 */ 378 if (!ar5210SetResetReg(ah, AR_RC_HW, AR_RC_SETTLE_TIME)) 379 return AH_FALSE; 380 OS_DELAY(1000); 381 (void) ar5210SetResetReg(ah, AR_RC_HW | AR_RC_RPCI, AR_RC_SETTLE_TIME); 382 OS_DELAY(2100); /* 8245 @ 96Mhz hangs with 2000us. */ 383 384 return AH_TRUE; 385 #undef AR_RC_HW 386 } 387 388 /* 389 * Places the hardware into reset and then pulls it out of reset 390 */ 391 HAL_BOOL 392 ar5210ChipReset(struct ath_hal *ah, struct ieee80211_channel *chan) 393 { 394 #define AR_RC_HW (AR_RC_RPCU | AR_RC_RDMA | AR_RC_RPHY | AR_RC_RMAC) 395 396 HALDEBUG(ah, HAL_DEBUG_RESET, "%s turbo %s\n", __func__, 397 chan && IEEE80211_IS_CHAN_TURBO(chan) ? 398 "enabled" : "disabled"); 399 400 if (!ar5210SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 401 return AH_FALSE; 402 403 /* Place chip in turbo before reset to cleanly reset clocks */ 404 OS_REG_WRITE(ah, AR_PHY_FRCTL, 405 chan && IEEE80211_IS_CHAN_TURBO(chan) ? AR_PHY_TURBO_MODE : 0); 406 407 /* 408 * Reset the HW. 409 * PCI must be reset after the rest of the device has been reset. 410 */ 411 if (!ar5210SetResetReg(ah, AR_RC_HW, AR_RC_SETTLE_TIME)) 412 return AH_FALSE; 413 OS_DELAY(1000); 414 if (!ar5210SetResetReg(ah, AR_RC_HW | AR_RC_RPCI, AR_RC_SETTLE_TIME)) 415 return AH_FALSE; 416 OS_DELAY(2100); /* 8245 @ 96Mhz hangs with 2000us. */ 417 418 /* 419 * Bring out of sleep mode (AGAIN) 420 * 421 * WARNING WARNING WARNING 422 * 423 * There is a problem with the chip where it doesn't always indicate 424 * that it's awake, so initializePowerUp() will fail. 425 */ 426 if (!ar5210SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 427 return AH_FALSE; 428 429 /* Clear warm reset reg */ 430 return ar5210SetResetReg(ah, 0, 10); 431 #undef AR_RC_HW 432 } 433 434 enum { 435 FIRPWR_M = 0x03fc0000, 436 FIRPWR_S = 18, 437 KCOARSEHIGH_M = 0x003f8000, 438 KCOARSEHIGH_S = 15, 439 KCOARSELOW_M = 0x00007f80, 440 KCOARSELOW_S = 7, 441 ADCSAT_ICOUNT_M = 0x0001f800, 442 ADCSAT_ICOUNT_S = 11, 443 ADCSAT_THRESH_M = 0x000007e0, 444 ADCSAT_THRESH_S = 5 445 }; 446 447 /* 448 * Recalibrate the lower PHY chips to account for temperature/environment 449 * changes. 450 */ 451 HAL_BOOL 452 ar5210PerCalibrationN(struct ath_hal *ah, 453 struct ieee80211_channel *chan, u_int chainMask, 454 HAL_BOOL longCal, HAL_BOOL *isCalDone) 455 { 456 uint32_t regBeacon; 457 uint32_t reg9858, reg985c, reg9868; 458 HAL_CHANNEL_INTERNAL *ichan; 459 460 ichan = ath_hal_checkchannel(ah, chan); 461 if (ichan == AH_NULL) 462 return AH_FALSE; 463 /* Disable tx and rx */ 464 ar5210UpdateDiagReg(ah, 465 OS_REG_READ(ah, AR_DIAG_SW) | (AR_DIAG_SW_DIS_TX | AR_DIAG_SW_DIS_RX)); 466 467 /* Disable Beacon Enable */ 468 regBeacon = OS_REG_READ(ah, AR_BEACON); 469 OS_REG_WRITE(ah, AR_BEACON, regBeacon & ~AR_BEACON_EN); 470 471 /* Delay 4ms to ensure that all tx and rx activity has ceased */ 472 OS_DELAY(4000); 473 474 /* Disable AGC to radio traffic */ 475 OS_REG_WRITE(ah, 0x9808, OS_REG_READ(ah, 0x9808) | 0x08000000); 476 /* Wait for the AGC traffic to cease. */ 477 OS_DELAY(10); 478 479 /* Change Channel to relock synth */ 480 if (!ar5210SetChannel(ah, chan)) 481 return AH_FALSE; 482 483 /* wait for the synthesizer lock to stabilize */ 484 OS_DELAY(1000); 485 486 /* Re-enable AGC to radio traffic */ 487 OS_REG_WRITE(ah, 0x9808, OS_REG_READ(ah, 0x9808) & (~0x08000000)); 488 489 /* 490 * Configure the AGC so that it is highly unlikely (if not 491 * impossible) for it to send any gain changes to the analog 492 * chip. We store off the current values so that they can 493 * be rewritten below. Setting the following values: 494 * firpwr = -1 495 * Kcoursehigh = -1 496 * Kcourselow = -127 497 * ADCsat_icount = 2 498 * ADCsat_thresh = 12 499 */ 500 reg9858 = OS_REG_READ(ah, 0x9858); 501 reg985c = OS_REG_READ(ah, 0x985c); 502 reg9868 = OS_REG_READ(ah, 0x9868); 503 504 OS_REG_WRITE(ah, 0x9858, (reg9858 & ~FIRPWR_M) | 505 ((-1 << FIRPWR_S) & FIRPWR_M)); 506 OS_REG_WRITE(ah, 0x985c, 507 (reg985c & ~(KCOARSEHIGH_M | KCOARSELOW_M)) | 508 ((-1 << KCOARSEHIGH_S) & KCOARSEHIGH_M) | 509 ((-127 << KCOARSELOW_S) & KCOARSELOW_M)); 510 OS_REG_WRITE(ah, 0x9868, 511 (reg9868 & ~(ADCSAT_ICOUNT_M | ADCSAT_THRESH_M)) | 512 ((2 << ADCSAT_ICOUNT_S) & ADCSAT_ICOUNT_M) | 513 ((12 << ADCSAT_THRESH_S) & ADCSAT_THRESH_M)); 514 515 /* Wait for AGC changes to be enacted */ 516 OS_DELAY(20); 517 518 /* 519 * We disable RF mix/gain stages for the PGA to avoid a 520 * race condition that will occur with receiving a frame 521 * and performing the AGC calibration. This will be 522 * re-enabled at the end of offset cal. We turn off AGC 523 * writes during this write as it will go over the analog bus. 524 */ 525 OS_REG_WRITE(ah, 0x9808, OS_REG_READ(ah, 0x9808) | 0x08000000); 526 OS_DELAY(10); /* wait for the AGC traffic to cease */ 527 OS_REG_WRITE(ah, 0x98D4, 0x21); 528 OS_REG_WRITE(ah, 0x9808, OS_REG_READ(ah, 0x9808) & (~0x08000000)); 529 530 /* wait to make sure that additional AGC traffic has quiesced */ 531 OS_DELAY(1000); 532 533 /* AGC calibration (this was added to make the NF threshold check work) */ 534 OS_REG_WRITE(ah, AR_PHY_AGCCTL, 535 OS_REG_READ(ah, AR_PHY_AGCCTL) | AR_PHY_AGC_CAL); 536 if (!ath_hal_wait(ah, AR_PHY_AGCCTL, AR_PHY_AGC_CAL, 0)) { 537 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: AGC calibration timeout\n", 538 __func__); 539 } 540 541 /* Rewrite our AGC values we stored off earlier (return AGC to normal operation) */ 542 OS_REG_WRITE(ah, 0x9858, reg9858); 543 OS_REG_WRITE(ah, 0x985c, reg985c); 544 OS_REG_WRITE(ah, 0x9868, reg9868); 545 546 /* Perform noise floor and set status */ 547 if (!ar5210CalNoiseFloor(ah, ichan)) { 548 /* 549 * Delay 5ms before retrying the noise floor - 550 * just to make sure. We're in an error 551 * condition here 552 */ 553 HALDEBUG(ah, HAL_DEBUG_NFCAL | HAL_DEBUG_PERCAL, 554 "%s: Performing 2nd Noise Cal\n", __func__); 555 OS_DELAY(5000); 556 if (!ar5210CalNoiseFloor(ah, ichan)) 557 chan->ic_state |= IEEE80211_CHANSTATE_CWINT; 558 } 559 560 /* Clear tx and rx disable bit */ 561 ar5210UpdateDiagReg(ah, 562 OS_REG_READ(ah, AR_DIAG_SW) & ~(AR_DIAG_SW_DIS_TX | AR_DIAG_SW_DIS_RX)); 563 564 /* Re-enable Beacons */ 565 OS_REG_WRITE(ah, AR_BEACON, regBeacon); 566 567 *isCalDone = AH_TRUE; 568 569 return AH_TRUE; 570 } 571 572 HAL_BOOL 573 ar5210PerCalibration(struct ath_hal *ah, struct ieee80211_channel *chan, 574 HAL_BOOL *isIQdone) 575 { 576 return ar5210PerCalibrationN(ah, chan, 0x1, AH_TRUE, isIQdone); 577 } 578 579 HAL_BOOL 580 ar5210ResetCalValid(struct ath_hal *ah, const struct ieee80211_channel *chan) 581 { 582 return AH_TRUE; 583 } 584 585 /* 586 * Writes the given reset bit mask into the reset register 587 */ 588 static HAL_BOOL 589 ar5210SetResetReg(struct ath_hal *ah, uint32_t resetMask, u_int delay) 590 { 591 uint32_t mask = resetMask ? resetMask : ~0; 592 HAL_BOOL rt; 593 594 OS_REG_WRITE(ah, AR_RC, resetMask); 595 /* need to wait at least 128 clocks when reseting PCI before read */ 596 OS_DELAY(delay); 597 598 resetMask &= AR_RC_RPCU | AR_RC_RDMA | AR_RC_RPHY | AR_RC_RMAC; 599 mask &= AR_RC_RPCU | AR_RC_RDMA | AR_RC_RPHY | AR_RC_RMAC; 600 rt = ath_hal_wait(ah, AR_RC, mask, resetMask); 601 if ((resetMask & AR_RC_RMAC) == 0) { 602 if (isBigEndian()) { 603 /* 604 * Set CFG, little-endian for descriptor accesses. 605 */ 606 mask = INIT_CONFIG_STATUS | AR_CFG_SWTD | AR_CFG_SWRD; 607 OS_REG_WRITE(ah, AR_CFG, mask); 608 } else 609 OS_REG_WRITE(ah, AR_CFG, INIT_CONFIG_STATUS); 610 } 611 return rt; 612 } 613 614 615 /* 616 * Returns: the pcdac value 617 */ 618 static uint8_t 619 getPcdac(struct ath_hal *ah, const struct tpcMap *pRD, uint8_t dBm) 620 { 621 int32_t i; 622 int useNextEntry = AH_FALSE; 623 uint32_t interp; 624 625 for (i = AR_TP_SCALING_ENTRIES - 1; i >= 0; i--) { 626 /* Check for exact entry */ 627 if (dBm == AR_I2DBM(i)) { 628 if (pRD->pcdac[i] != 63) 629 return pRD->pcdac[i]; 630 useNextEntry = AH_TRUE; 631 } else if (dBm + 1 == AR_I2DBM(i) && i > 0) { 632 /* Interpolate for between entry with a logish scale */ 633 if (pRD->pcdac[i] != 63 && pRD->pcdac[i-1] != 63) { 634 interp = (350 * (pRD->pcdac[i] - pRD->pcdac[i-1])) + 999; 635 interp = (interp / 1000) + pRD->pcdac[i-1]; 636 return interp; 637 } 638 useNextEntry = AH_TRUE; 639 } else if (useNextEntry == AH_TRUE) { 640 /* Grab the next lowest */ 641 if (pRD->pcdac[i] != 63) 642 return pRD->pcdac[i]; 643 } 644 } 645 646 /* Return the lowest Entry if we haven't returned */ 647 for (i = 0; i < AR_TP_SCALING_ENTRIES; i++) 648 if (pRD->pcdac[i] != 63) 649 return pRD->pcdac[i]; 650 651 /* No value to return from table */ 652 #ifdef AH_DEBUG 653 ath_hal_printf(ah, "%s: empty transmit power table?\n", __func__); 654 #endif 655 return 1; 656 } 657 658 /* 659 * Find or interpolates the gainF value from the table ptr. 660 */ 661 static uint8_t 662 getGainF(struct ath_hal *ah, const struct tpcMap *pRD, 663 uint8_t pcdac, uint8_t *dBm) 664 { 665 uint32_t interp; 666 int low, high, i; 667 668 low = high = -1; 669 670 for (i = 0; i < AR_TP_SCALING_ENTRIES; i++) { 671 if(pRD->pcdac[i] == 63) 672 continue; 673 if (pcdac == pRD->pcdac[i]) { 674 *dBm = AR_I2DBM(i); 675 return pRD->gainF[i]; /* Exact Match */ 676 } 677 if (pcdac > pRD->pcdac[i]) 678 low = i; 679 if (pcdac < pRD->pcdac[i]) { 680 high = i; 681 if (low == -1) { 682 *dBm = AR_I2DBM(i); 683 /* PCDAC is lower than lowest setting */ 684 return pRD->gainF[i]; 685 } 686 break; 687 } 688 } 689 if (i >= AR_TP_SCALING_ENTRIES && low == -1) { 690 /* No settings were found */ 691 #ifdef AH_DEBUG 692 ath_hal_printf(ah, 693 "%s: no valid entries in the pcdac table: %d\n", 694 __func__, pcdac); 695 #endif 696 return 63; 697 } 698 if (i >= AR_TP_SCALING_ENTRIES) { 699 /* PCDAC setting was above the max setting in the table */ 700 *dBm = AR_I2DBM(low); 701 return pRD->gainF[low]; 702 } 703 /* Only exact if table has no missing entries */ 704 *dBm = (low + high) + 3; 705 706 /* 707 * Perform interpolation between low and high values to find gainF 708 * linearly scale the pcdac between low and high 709 */ 710 interp = ((pcdac - pRD->pcdac[low]) * 1000) / 711 (pRD->pcdac[high] - pRD->pcdac[low]); 712 /* 713 * Multiply the scale ratio by the gainF difference 714 * (plus a rnd up factor) 715 */ 716 interp = ((interp * (pRD->gainF[high] - pRD->gainF[low])) + 999) / 1000; 717 718 /* Add ratioed gain_f to low gain_f value */ 719 return interp + pRD->gainF[low]; 720 } 721 722 HAL_BOOL 723 ar5210SetTxPowerLimit(struct ath_hal *ah, uint32_t limit) 724 { 725 AH_PRIVATE(ah)->ah_powerLimit = AH_MIN(limit, AR5210_MAX_RATE_POWER); 726 /* XXX flush to h/w */ 727 return AH_TRUE; 728 } 729 730 /* 731 * Get TXPower values and set them in the radio 732 */ 733 static HAL_BOOL 734 setupPowerSettings(struct ath_hal *ah, const struct ieee80211_channel *chan, 735 uint8_t cp[17]) 736 { 737 uint16_t freq = ath_hal_gethwchannel(ah, chan); 738 const HAL_EEPROM_v1 *ee = AH_PRIVATE(ah)->ah_eeprom; 739 uint8_t gainFRD, gainF36, gainF48, gainF54; 740 uint8_t dBmRD, dBm36, dBm48, dBm54, dontcare; 741 uint32_t rd, group; 742 const struct tpcMap *pRD; 743 744 /* Set OB/DB Values regardless of channel */ 745 cp[15] = (ee->ee_biasCurrents >> 4) & 0x7; 746 cp[16] = ee->ee_biasCurrents & 0x7; 747 748 if (freq < 5170 || freq > 5320) { 749 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel %u\n", 750 __func__, freq); 751 return AH_FALSE; 752 } 753 754 HALASSERT(ee->ee_version >= AR_EEPROM_VER1 && 755 ee->ee_version < AR_EEPROM_VER3); 756 757 /* Match regulatory domain */ 758 for (rd = 0; rd < AR_REG_DOMAINS_MAX; rd++) 759 if (AH_PRIVATE(ah)->ah_currentRD == ee->ee_regDomain[rd]) 760 break; 761 if (rd == AR_REG_DOMAINS_MAX) { 762 #ifdef AH_DEBUG 763 ath_hal_printf(ah, 764 "%s: no calibrated regulatory domain matches the " 765 "current regularly domain (0x%0x)\n", __func__, 766 AH_PRIVATE(ah)->ah_currentRD); 767 #endif 768 return AH_FALSE; 769 } 770 group = ((freq - 5170) / 10); 771 772 if (group > 11) { 773 /* Pull 5.29 into the 5.27 group */ 774 group--; 775 } 776 777 /* Integer divide will set group from 0 to 4 */ 778 group = group / 3; 779 pRD = &ee->ee_tpc[group]; 780 781 /* Set PC DAC Values */ 782 cp[14] = pRD->regdmn[rd]; 783 cp[9] = AH_MIN(pRD->regdmn[rd], pRD->rate36); 784 cp[8] = AH_MIN(pRD->regdmn[rd], pRD->rate48); 785 cp[7] = AH_MIN(pRD->regdmn[rd], pRD->rate54); 786 787 /* Find Corresponding gainF values for RD, 36, 48, 54 */ 788 gainFRD = getGainF(ah, pRD, pRD->regdmn[rd], &dBmRD); 789 gainF36 = getGainF(ah, pRD, cp[9], &dBm36); 790 gainF48 = getGainF(ah, pRD, cp[8], &dBm48); 791 gainF54 = getGainF(ah, pRD, cp[7], &dBm54); 792 793 /* Power Scale if requested */ 794 if (AH_PRIVATE(ah)->ah_tpScale != HAL_TP_SCALE_MAX) { 795 static const uint16_t tpcScaleReductionTable[5] = 796 { 0, 3, 6, 9, AR5210_MAX_RATE_POWER }; 797 uint16_t tpScale; 798 799 tpScale = tpcScaleReductionTable[AH_PRIVATE(ah)->ah_tpScale]; 800 if (dBmRD < tpScale+3) 801 dBmRD = 3; /* min */ 802 else 803 dBmRD -= tpScale; 804 cp[14] = getPcdac(ah, pRD, dBmRD); 805 gainFRD = getGainF(ah, pRD, cp[14], &dontcare); 806 dBm36 = AH_MIN(dBm36, dBmRD); 807 cp[9] = getPcdac(ah, pRD, dBm36); 808 gainF36 = getGainF(ah, pRD, cp[9], &dontcare); 809 dBm48 = AH_MIN(dBm48, dBmRD); 810 cp[8] = getPcdac(ah, pRD, dBm48); 811 gainF48 = getGainF(ah, pRD, cp[8], &dontcare); 812 dBm54 = AH_MIN(dBm54, dBmRD); 813 cp[7] = getPcdac(ah, pRD, dBm54); 814 gainF54 = getGainF(ah, pRD, cp[7], &dontcare); 815 } 816 /* Record current dBm at rate 6 */ 817 AH_PRIVATE(ah)->ah_maxPowerLevel = 2*dBmRD; 818 819 cp[13] = cp[12] = cp[11] = cp[10] = cp[14]; 820 821 /* Set GainF Values */ 822 cp[0] = gainFRD - gainF54; 823 cp[1] = gainFRD - gainF48; 824 cp[2] = gainFRD - gainF36; 825 /* 9, 12, 18, 24 have no gain_delta from 6 */ 826 cp[3] = cp[4] = cp[5] = cp[6] = 0; 827 return AH_TRUE; 828 } 829 830 /* 831 * Places the device in and out of reset and then places sane 832 * values in the registers based on EEPROM config, initialization 833 * vectors (as determined by the mode), and station configuration 834 */ 835 HAL_BOOL 836 ar5210SetTransmitPower(struct ath_hal *ah, const struct ieee80211_channel *chan) 837 { 838 #define N(a) (sizeof (a) / sizeof (a[0])) 839 static const uint32_t pwr_regs_start[17] = { 840 0x00000000, 0x00000000, 0x00000000, 841 0x00000000, 0x00000000, 0xf0000000, 842 0xcc000000, 0x00000000, 0x00000000, 843 0x00000000, 0x0a000000, 0x000000e2, 844 0x0a000020, 0x01000002, 0x01000018, 845 0x40000000, 0x00000418 846 }; 847 uint16_t i; 848 uint8_t cp[sizeof(ar5k0007_pwrSettings)]; 849 uint32_t pwr_regs[17]; 850 851 OS_MEMCPY(pwr_regs, pwr_regs_start, sizeof(pwr_regs)); 852 OS_MEMCPY(cp, ar5k0007_pwrSettings, sizeof(cp)); 853 854 /* Check the EEPROM tx power calibration settings */ 855 if (!setupPowerSettings(ah, chan, cp)) { 856 #ifdef AH_DEBUG 857 ath_hal_printf(ah, "%s: unable to setup power settings\n", 858 __func__); 859 #endif 860 return AH_FALSE; 861 } 862 if (cp[15] < 1 || cp[15] > 5) { 863 #ifdef AH_DEBUG 864 ath_hal_printf(ah, "%s: OB out of range (%u)\n", 865 __func__, cp[15]); 866 #endif 867 return AH_FALSE; 868 } 869 if (cp[16] < 1 || cp[16] > 5) { 870 #ifdef AH_DEBUG 871 ath_hal_printf(ah, "%s: DB out of range (%u)\n", 872 __func__, cp[16]); 873 #endif 874 return AH_FALSE; 875 } 876 877 /* reverse bits of the transmit power array */ 878 for (i = 0; i < 7; i++) 879 cp[i] = ath_hal_reverseBits(cp[i], 5); 880 for (i = 7; i < 15; i++) 881 cp[i] = ath_hal_reverseBits(cp[i], 6); 882 883 /* merge transmit power values into the register - quite gross */ 884 pwr_regs[0] |= ((cp[1] << 5) & 0xE0) | (cp[0] & 0x1F); 885 pwr_regs[1] |= ((cp[3] << 7) & 0x80) | ((cp[2] << 2) & 0x7C) | 886 ((cp[1] >> 3) & 0x03); 887 pwr_regs[2] |= ((cp[4] << 4) & 0xF0) | ((cp[3] >> 1) & 0x0F); 888 pwr_regs[3] |= ((cp[6] << 6) & 0xC0) | ((cp[5] << 1) & 0x3E) | 889 ((cp[4] >> 4) & 0x01); 890 pwr_regs[4] |= ((cp[7] << 3) & 0xF8) | ((cp[6] >> 2) & 0x07); 891 pwr_regs[5] |= ((cp[9] << 7) & 0x80) | ((cp[8] << 1) & 0x7E) | 892 ((cp[7] >> 5) & 0x01); 893 pwr_regs[6] |= ((cp[10] << 5) & 0xE0) | ((cp[9] >> 1) & 0x1F); 894 pwr_regs[7] |= ((cp[11] << 3) & 0xF8) | ((cp[10] >> 3) & 0x07); 895 pwr_regs[8] |= ((cp[12] << 1) & 0x7E) | ((cp[11] >> 5) & 0x01); 896 pwr_regs[9] |= ((cp[13] << 5) & 0xE0); 897 pwr_regs[10] |= ((cp[14] << 3) & 0xF8) | ((cp[13] >> 3) & 0x07); 898 pwr_regs[11] |= ((cp[14] >> 5) & 0x01); 899 900 /* Set OB */ 901 pwr_regs[8] |= (ath_hal_reverseBits(cp[15], 3) << 7) & 0x80; 902 pwr_regs[9] |= (ath_hal_reverseBits(cp[15], 3) >> 1) & 0x03; 903 904 /* Set DB */ 905 pwr_regs[9] |= (ath_hal_reverseBits(cp[16], 3) << 2) & 0x1C; 906 907 /* Write the registers */ 908 for (i = 0; i < N(pwr_regs)-1; i++) 909 OS_REG_WRITE(ah, 0x0000989c, pwr_regs[i]); 910 /* last write is a flush */ 911 OS_REG_WRITE(ah, 0x000098d4, pwr_regs[i]); 912 913 return AH_TRUE; 914 #undef N 915 } 916 917 /* 918 * Takes the MHz channel value and sets the Channel value 919 * 920 * ASSUMES: Writes enabled to analog bus before AGC is active 921 * or by disabling the AGC. 922 */ 923 static HAL_BOOL 924 ar5210SetChannel(struct ath_hal *ah, struct ieee80211_channel *chan) 925 { 926 uint16_t freq = ath_hal_gethwchannel(ah, chan); 927 uint32_t data; 928 929 /* Set the Channel */ 930 data = ath_hal_reverseBits((freq - 5120)/10, 5); 931 data = (data << 1) | 0x41; 932 OS_REG_WRITE(ah, AR_PHY(0x27), data); 933 OS_REG_WRITE(ah, AR_PHY(0x30), 0); 934 AH_PRIVATE(ah)->ah_curchan = chan; 935 return AH_TRUE; 936 } 937 938 int16_t 939 ar5210GetNoiseFloor(struct ath_hal *ah) 940 { 941 int16_t nf; 942 943 nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff; 944 if (nf & 0x100) 945 nf = 0 - ((nf ^ 0x1ff) + 1); 946 return nf; 947 } 948 949 #define NORMAL_NF_THRESH (-72) 950 /* 951 * Peform the noisefloor calibration and check for 952 * any constant channel interference 953 * 954 * Returns: TRUE for a successful noise floor calibration; else FALSE 955 */ 956 HAL_BOOL 957 ar5210CalNoiseFloor(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *ichan) 958 { 959 int32_t nf, nfLoops; 960 961 /* Calibrate the noise floor */ 962 OS_REG_WRITE(ah, AR_PHY_AGCCTL, 963 OS_REG_READ(ah, AR_PHY_AGCCTL) | AR_PHY_AGC_NF); 964 965 /* Do not read noise floor until it has done the first update */ 966 if (!ath_hal_wait(ah, AR_PHY_AGCCTL, AR_PHY_AGC_NF, 0)) { 967 #ifdef ATH_HAL_DEBUG 968 ath_hal_printf(ah, " -PHY NF Reg state: 0x%x\n", 969 OS_REG_READ(ah, AR_PHY_AGCCTL)); 970 ath_hal_printf(ah, " -MAC Reset Reg state: 0x%x\n", 971 OS_REG_READ(ah, AR_RC)); 972 ath_hal_printf(ah, " -PHY Active Reg state: 0x%x\n", 973 OS_REG_READ(ah, AR_PHY_ACTIVE)); 974 #endif /* ATH_HAL_DEBUG */ 975 return AH_FALSE; 976 } 977 978 nf = 0; 979 /* Keep checking until the floor is below the threshold or the nf is done */ 980 for (nfLoops = 0; ((nfLoops < 21) && (nf > NORMAL_NF_THRESH)); nfLoops++) { 981 OS_DELAY(1000); /* Sleep for 1 ms */ 982 nf = ar5210GetNoiseFloor(ah); 983 } 984 985 if (nf > NORMAL_NF_THRESH) { 986 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: Bad noise cal %d\n", 987 __func__, nf); 988 ichan->rawNoiseFloor = 0; 989 return AH_FALSE; 990 } 991 ichan->rawNoiseFloor = nf; 992 return AH_TRUE; 993 } 994 995 /* 996 * Adjust NF based on statistical values for 5GHz frequencies. 997 */ 998 int16_t 999 ar5210GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c) 1000 { 1001 return 0; 1002 } 1003 1004 HAL_RFGAIN 1005 ar5210GetRfgain(struct ath_hal *ah) 1006 { 1007 return HAL_RFGAIN_INACTIVE; 1008 } 1009