xref: /freebsd/sys/dev/ath/ath_hal/ar5210/ar5210_reset.c (revision 9268022b74279434ed6300244e3f977e56a8ceb5)
1 /*
2  * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3  * Copyright (c) 2002-2004 Atheros Communications, Inc.
4  *
5  * Permission to use, copy, modify, and/or distribute this software for any
6  * purpose with or without fee is hereby granted, provided that the above
7  * copyright notice and this permission notice appear in all copies.
8  *
9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16  *
17  * $FreeBSD$
18  */
19 #include "opt_ah.h"
20 
21 #include "ah.h"
22 #include "ah_internal.h"
23 
24 #include "ar5210/ar5210.h"
25 #include "ar5210/ar5210reg.h"
26 #include "ar5210/ar5210phy.h"
27 
28 #include "ah_eeprom_v1.h"
29 
30 typedef struct {
31 	uint32_t	Offset;
32 	uint32_t	Value;
33 } REGISTER_VAL;
34 
35 static const REGISTER_VAL ar5k0007_init[] = {
36 #include "ar5210/ar5k_0007.ini"
37 };
38 
39 /* Default Power Settings for channels outside of EEPROM range */
40 static const uint8_t ar5k0007_pwrSettings[17] = {
41 /*	gain delta			pc dac */
42 /* 54  48  36  24  18  12   9   54  48  36  24  18  12   9   6  ob  db	  */
43     9,  9,  0,  0,  0,  0,  0,   2,  2,  6,  6,  6,  6,  6,  6,  2,  2
44 };
45 
46 /*
47  * The delay, in usecs, between writing AR_RC with a reset
48  * request and waiting for the chip to settle.  If this is
49  * too short then the chip does not come out of sleep state.
50  * Note this value was empirically derived and may be dependent
51  * on the host machine (don't know--the problem was identified
52  * on an IBM 570e laptop; 10us delays worked on other systems).
53  */
54 #define	AR_RC_SETTLE_TIME	20000
55 
56 static HAL_BOOL ar5210SetResetReg(struct ath_hal *,
57 		uint32_t resetMask, u_int delay);
58 static HAL_BOOL ar5210SetChannel(struct ath_hal *, struct ieee80211_channel *);
59 static void ar5210SetOperatingMode(struct ath_hal *, int opmode);
60 
61 /*
62  * Places the device in and out of reset and then places sane
63  * values in the registers based on EEPROM config, initialization
64  * vectors (as determined by the mode), and station configuration
65  *
66  * bChannelChange is used to preserve DMA/PCU registers across
67  * a HW Reset during channel change.
68  */
69 HAL_BOOL
70 ar5210Reset(struct ath_hal *ah, HAL_OPMODE opmode,
71 	struct ieee80211_channel *chan, HAL_BOOL bChannelChange,
72 	HAL_STATUS *status)
73 {
74 #define	N(a)	(sizeof (a) /sizeof (a[0]))
75 #define	FAIL(_code)	do { ecode = _code; goto bad; } while (0)
76 	struct ath_hal_5210 *ahp = AH5210(ah);
77 	const HAL_EEPROM_v1 *ee = AH_PRIVATE(ah)->ah_eeprom;
78 	HAL_CHANNEL_INTERNAL *ichan;
79 	HAL_STATUS ecode;
80 	uint32_t ledstate;
81 	int i, q;
82 
83 	HALDEBUG(ah, HAL_DEBUG_RESET,
84 	    "%s: opmode %u channel %u/0x%x %s channel\n", __func__,
85 	    opmode, chan->ic_freq, chan->ic_flags,
86 	    bChannelChange ? "change" : "same");
87 
88 	if (!IEEE80211_IS_CHAN_5GHZ(chan)) {
89 		/* Only 11a mode */
90 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: channel not 5GHz\n", __func__);
91 		FAIL(HAL_EINVAL);
92 	}
93 	/*
94 	 * Map public channel to private.
95 	 */
96 	ichan = ath_hal_checkchannel(ah, chan);
97 	if (ichan == AH_NULL) {
98 		HALDEBUG(ah, HAL_DEBUG_ANY,
99 		    "%s: invalid channel %u/0x%x; no mapping\n",
100 		    __func__, chan->ic_freq, chan->ic_flags);
101 		FAIL(HAL_EINVAL);
102 	}
103 	switch (opmode) {
104 	case HAL_M_STA:
105 	case HAL_M_IBSS:
106 	case HAL_M_HOSTAP:
107 	case HAL_M_MONITOR:
108 		break;
109 	default:
110 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid operating mode %u\n",
111 		    __func__, opmode);
112 		FAIL(HAL_EINVAL);
113 		break;
114 	}
115 
116 	ledstate = OS_REG_READ(ah, AR_PCICFG) &
117 		(AR_PCICFG_LED_PEND | AR_PCICFG_LED_ACT);
118 
119 	if (!ar5210ChipReset(ah, chan)) {
120 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n",
121 		    __func__);
122 		FAIL(HAL_EIO);
123 	}
124 
125 	OS_REG_WRITE(ah, AR_STA_ID0, LE_READ_4(ahp->ah_macaddr));
126 	OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4));
127 	ar5210SetOperatingMode(ah, opmode);
128 
129 	switch (opmode) {
130 	case HAL_M_HOSTAP:
131 		OS_REG_WRITE(ah, AR_BCR, INIT_BCON_CNTRL_REG);
132 		OS_REG_WRITE(ah, AR_PCICFG,
133 			AR_PCICFG_LED_ACT | AR_PCICFG_LED_BCTL);
134 		break;
135 	case HAL_M_IBSS:
136 		OS_REG_WRITE(ah, AR_BCR, INIT_BCON_CNTRL_REG | AR_BCR_BCMD);
137 		OS_REG_WRITE(ah, AR_PCICFG,
138 			AR_PCICFG_CLKRUNEN | AR_PCICFG_LED_PEND | AR_PCICFG_LED_BCTL);
139 		break;
140 	case HAL_M_STA:
141 		OS_REG_WRITE(ah, AR_BCR, INIT_BCON_CNTRL_REG);
142 		OS_REG_WRITE(ah, AR_PCICFG,
143 			AR_PCICFG_CLKRUNEN | AR_PCICFG_LED_PEND | AR_PCICFG_LED_BCTL);
144 		break;
145 	case HAL_M_MONITOR:
146 		OS_REG_WRITE(ah, AR_BCR, INIT_BCON_CNTRL_REG);
147 		OS_REG_WRITE(ah, AR_PCICFG,
148 			AR_PCICFG_LED_ACT | AR_PCICFG_LED_BCTL);
149 		break;
150 	}
151 
152 	/* Restore previous led state */
153 	OS_REG_WRITE(ah, AR_PCICFG, OS_REG_READ(ah, AR_PCICFG) | ledstate);
154 
155 #if 0
156 	OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));
157 	OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4));
158 #endif
159 	/* BSSID, association id, ps-poll */
160 	ar5210WriteAssocid(ah, ahp->ah_bssid, ahp->ah_associd);
161 
162 	OS_REG_WRITE(ah, AR_TXDP0, 0);
163 	OS_REG_WRITE(ah, AR_TXDP1, 0);
164 	OS_REG_WRITE(ah, AR_RXDP, 0);
165 
166 	/*
167 	 * Initialize interrupt state.
168 	 */
169 	(void) OS_REG_READ(ah, AR_ISR);		/* cleared on read */
170 	OS_REG_WRITE(ah, AR_IMR, 0);
171 	OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
172 	ahp->ah_maskReg = 0;
173 
174 	(void) OS_REG_READ(ah, AR_BSR);		/* cleared on read */
175 	OS_REG_WRITE(ah, AR_TXCFG, AR_DMASIZE_128B);
176 	OS_REG_WRITE(ah, AR_RXCFG, AR_DMASIZE_128B);
177 
178 	OS_REG_WRITE(ah, AR_TOPS, 8);		/* timeout prescale */
179 	OS_REG_WRITE(ah, AR_RXNOFRM, 8);	/* RX no frame timeout */
180 	OS_REG_WRITE(ah, AR_RPGTO, 0);		/* RX frame gap timeout */
181 	OS_REG_WRITE(ah, AR_TXNOFRM, 0);	/* TX no frame timeout */
182 
183 	OS_REG_WRITE(ah, AR_SFR, 0);
184 	OS_REG_WRITE(ah, AR_MIBC, 0);		/* unfreeze ctrs + clr state */
185 	OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr);
186 	OS_REG_WRITE(ah, AR_CFP_DUR, 0);
187 
188 	ar5210SetRxFilter(ah, 0);		/* nothing for now */
189 	OS_REG_WRITE(ah, AR_MCAST_FIL0, 0);	/* multicast filter */
190 	OS_REG_WRITE(ah, AR_MCAST_FIL1, 0);	/* XXX was 2 */
191 
192 	OS_REG_WRITE(ah, AR_TX_MASK0, 0);
193 	OS_REG_WRITE(ah, AR_TX_MASK1, 0);
194 	OS_REG_WRITE(ah, AR_CLR_TMASK, 1);
195 	OS_REG_WRITE(ah, AR_TRIG_LEV, 1);	/* minimum */
196 
197 	ar5210UpdateDiagReg(ah, 0);
198 
199 	OS_REG_WRITE(ah, AR_CFP_PERIOD, 0);
200 	OS_REG_WRITE(ah, AR_TIMER0, 0);		/* next beacon time */
201 	OS_REG_WRITE(ah, AR_TSF_L32, 0);	/* local clock */
202 	OS_REG_WRITE(ah, AR_TIMER1, ~0);	/* next DMA beacon alert */
203 	OS_REG_WRITE(ah, AR_TIMER2, ~0);	/* next SW beacon alert */
204 	OS_REG_WRITE(ah, AR_TIMER3, 1);		/* next ATIM window */
205 
206 	/* Write the INI values for PHYreg initialization */
207 	for (i = 0; i < N(ar5k0007_init); i++) {
208 		uint32_t reg = ar5k0007_init[i].Offset;
209 		/* On channel change, don't reset the PCU registers */
210 		if (!(bChannelChange && (0x8000 <= reg && reg < 0x9000)))
211 			OS_REG_WRITE(ah, reg, ar5k0007_init[i].Value);
212 	}
213 
214 	/* Setup the transmit power values for cards since 0x0[0-2]05 */
215 	if (!ar5210SetTransmitPower(ah, chan)) {
216 		HALDEBUG(ah, HAL_DEBUG_ANY,
217 		    "%s: error init'ing transmit power\n", __func__);
218 		FAIL(HAL_EIO);
219 	}
220 
221 	OS_REG_WRITE(ah, AR_PHY(10),
222 		(OS_REG_READ(ah, AR_PHY(10)) & 0xFFFF00FF) |
223 		(ee->ee_xlnaOn << 8));
224 	OS_REG_WRITE(ah, AR_PHY(13),
225 		(ee->ee_xpaOff << 24) | (ee->ee_xpaOff << 16) |
226 		(ee->ee_xpaOn << 8) | ee->ee_xpaOn);
227 	OS_REG_WRITE(ah, AR_PHY(17),
228 		(OS_REG_READ(ah, AR_PHY(17)) & 0xFFFFC07F) |
229 		((ee->ee_antenna >> 1) & 0x3F80));
230 	OS_REG_WRITE(ah, AR_PHY(18),
231 		(OS_REG_READ(ah, AR_PHY(18)) & 0xFFFC0FFF) |
232 		((ee->ee_antenna << 10) & 0x3F000));
233 	OS_REG_WRITE(ah, AR_PHY(25),
234 		(OS_REG_READ(ah, AR_PHY(25)) & 0xFFF80FFF) |
235 		((ee->ee_thresh62 << 12) & 0x7F000));
236 	OS_REG_WRITE(ah, AR_PHY(68),
237 		(OS_REG_READ(ah, AR_PHY(68)) & 0xFFFFFFFC) |
238 		(ee->ee_antenna & 0x3));
239 
240 	if (!ar5210SetChannel(ah, chan)) {
241 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set channel\n",
242 		    __func__);
243 		FAIL(HAL_EIO);
244 	}
245 	if (bChannelChange && !IEEE80211_IS_CHAN_DFS(chan))
246 		chan->ic_state &= ~IEEE80211_CHANSTATE_CWINT;
247 
248 	/* Activate the PHY */
249 	OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ENABLE);
250 
251 	OS_DELAY(1000);		/* Wait a bit (1 msec) */
252 
253 	/* calibrate the HW and poll the bit going to 0 for completion */
254 	OS_REG_WRITE(ah, AR_PHY_AGCCTL,
255 		OS_REG_READ(ah, AR_PHY_AGCCTL) | AR_PHY_AGC_CAL);
256 	(void) ath_hal_wait(ah, AR_PHY_AGCCTL, AR_PHY_AGC_CAL, 0);
257 
258 	/* Perform noise floor calibration and set status */
259 	if (!ar5210CalNoiseFloor(ah, ichan)) {
260 		chan->ic_state |= IEEE80211_CHANSTATE_CWINT;
261 		HALDEBUG(ah, HAL_DEBUG_ANY,
262 		    "%s: noise floor calibration failed\n", __func__);
263 		FAIL(HAL_EIO);
264 	}
265 
266 	for (q = 0; q < HAL_NUM_TX_QUEUES; q++)
267 		ar5210ResetTxQueue(ah, q);
268 
269 	if (AH_PRIVATE(ah)->ah_rfkillEnabled)
270 		ar5210EnableRfKill(ah);
271 
272 	/*
273 	 * Writing to AR_BEACON will start timers. Hence it should be
274 	 * the last register to be written. Do not reset tsf, do not
275 	 * enable beacons at this point, but preserve other values
276 	 * like beaconInterval.
277 	 */
278 	OS_REG_WRITE(ah, AR_BEACON,
279 		(OS_REG_READ(ah, AR_BEACON) &
280 			~(AR_BEACON_EN | AR_BEACON_RESET_TSF)));
281 
282 	/* Restore user-specified slot time and timeouts */
283 	if (ahp->ah_sifstime != (u_int) -1)
284 		ar5210SetSifsTime(ah, ahp->ah_sifstime);
285 	if (ahp->ah_slottime != (u_int) -1)
286 		ar5210SetSlotTime(ah, ahp->ah_slottime);
287 	if (ahp->ah_acktimeout != (u_int) -1)
288 		ar5210SetAckTimeout(ah, ahp->ah_acktimeout);
289 	if (ahp->ah_ctstimeout != (u_int) -1)
290 		ar5210SetCTSTimeout(ah, ahp->ah_ctstimeout);
291 	if (AH_PRIVATE(ah)->ah_diagreg != 0)
292 		ar5210UpdateDiagReg(ah, AH_PRIVATE(ah)->ah_diagreg);
293 
294 	AH_PRIVATE(ah)->ah_opmode = opmode;	/* record operating mode */
295 
296 	HALDEBUG(ah, HAL_DEBUG_RESET, "%s: done\n", __func__);
297 
298 	return AH_TRUE;
299 bad:
300 	if (status != AH_NULL)
301 		*status = ecode;
302 	return AH_FALSE;
303 #undef FAIL
304 #undef N
305 }
306 
307 static void
308 ar5210SetOperatingMode(struct ath_hal *ah, int opmode)
309 {
310 	struct ath_hal_5210 *ahp = AH5210(ah);
311 	uint32_t val;
312 
313 	val = OS_REG_READ(ah, AR_STA_ID1) & 0xffff;
314 	switch (opmode) {
315 	case HAL_M_HOSTAP:
316 		OS_REG_WRITE(ah, AR_STA_ID1, val
317 			| AR_STA_ID1_AP
318 			| AR_STA_ID1_NO_PSPOLL
319 			| AR_STA_ID1_DESC_ANTENNA
320 			| ahp->ah_staId1Defaults);
321 		break;
322 	case HAL_M_IBSS:
323 		OS_REG_WRITE(ah, AR_STA_ID1, val
324 			| AR_STA_ID1_ADHOC
325 			| AR_STA_ID1_NO_PSPOLL
326 			| AR_STA_ID1_DESC_ANTENNA
327 			| ahp->ah_staId1Defaults);
328 		break;
329 	case HAL_M_STA:
330 		OS_REG_WRITE(ah, AR_STA_ID1, val
331 			| AR_STA_ID1_NO_PSPOLL
332 			| AR_STA_ID1_PWR_SV
333 			| ahp->ah_staId1Defaults);
334 		break;
335 	case HAL_M_MONITOR:
336 		OS_REG_WRITE(ah, AR_STA_ID1, val
337 			| AR_STA_ID1_NO_PSPOLL
338 			| ahp->ah_staId1Defaults);
339 		break;
340 	}
341 }
342 
343 void
344 ar5210SetPCUConfig(struct ath_hal *ah)
345 {
346 	ar5210SetOperatingMode(ah, AH_PRIVATE(ah)->ah_opmode);
347 }
348 
349 /*
350  * Places the PHY and Radio chips into reset.  A full reset
351  * must be called to leave this state.  The PCI/MAC/PCU are
352  * not placed into reset as we must receive interrupt to
353  * re-enable the hardware.
354  */
355 HAL_BOOL
356 ar5210PhyDisable(struct ath_hal *ah)
357 {
358 	return ar5210SetResetReg(ah, AR_RC_RPHY, 10);
359 }
360 
361 /*
362  * Places all of hardware into reset
363  */
364 HAL_BOOL
365 ar5210Disable(struct ath_hal *ah)
366 {
367 #define	AR_RC_HW (AR_RC_RPCU | AR_RC_RDMA | AR_RC_RPHY | AR_RC_RMAC)
368 	if (!ar5210SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))
369 		return AH_FALSE;
370 
371 	/*
372 	 * Reset the HW - PCI must be reset after the rest of the
373 	 * device has been reset
374 	 */
375 	if (!ar5210SetResetReg(ah, AR_RC_HW, AR_RC_SETTLE_TIME))
376 		return AH_FALSE;
377 	OS_DELAY(1000);
378 	(void) ar5210SetResetReg(ah, AR_RC_HW | AR_RC_RPCI, AR_RC_SETTLE_TIME);
379 	OS_DELAY(2100);   /* 8245 @ 96Mhz hangs with 2000us. */
380 
381 	return AH_TRUE;
382 #undef AR_RC_HW
383 }
384 
385 /*
386  * Places the hardware into reset and then pulls it out of reset
387  */
388 HAL_BOOL
389 ar5210ChipReset(struct ath_hal *ah, struct ieee80211_channel *chan)
390 {
391 #define	AR_RC_HW (AR_RC_RPCU | AR_RC_RDMA | AR_RC_RPHY | AR_RC_RMAC)
392 
393 	HALDEBUG(ah, HAL_DEBUG_RESET, "%s turbo %s\n", __func__,
394 		chan && IEEE80211_IS_CHAN_TURBO(chan) ?
395 		"enabled" : "disabled");
396 
397 	if (!ar5210SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))
398 		return AH_FALSE;
399 
400 	/* Place chip in turbo before reset to cleanly reset clocks */
401 	OS_REG_WRITE(ah, AR_PHY_FRCTL,
402 		chan && IEEE80211_IS_CHAN_TURBO(chan) ? AR_PHY_TURBO_MODE : 0);
403 
404 	/*
405 	 * Reset the HW.
406 	 * PCI must be reset after the rest of the device has been reset.
407 	 */
408 	if (!ar5210SetResetReg(ah, AR_RC_HW, AR_RC_SETTLE_TIME))
409 		return AH_FALSE;
410 	OS_DELAY(1000);
411 	if (!ar5210SetResetReg(ah, AR_RC_HW | AR_RC_RPCI, AR_RC_SETTLE_TIME))
412 		return AH_FALSE;
413 	OS_DELAY(2100);   /* 8245 @ 96Mhz hangs with 2000us. */
414 
415 	/*
416 	 * Bring out of sleep mode (AGAIN)
417 	 *
418 	 * WARNING WARNING WARNING
419 	 *
420 	 * There is a problem with the chip where it doesn't always indicate
421 	 * that it's awake, so initializePowerUp() will fail.
422 	 */
423 	if (!ar5210SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))
424 		return AH_FALSE;
425 
426 	/* Clear warm reset reg */
427 	return ar5210SetResetReg(ah, 0, 10);
428 #undef AR_RC_HW
429 }
430 
431 enum {
432 	FIRPWR_M	= 0x03fc0000,
433 	FIRPWR_S	= 18,
434 	KCOARSEHIGH_M   = 0x003f8000,
435 	KCOARSEHIGH_S   = 15,
436 	KCOARSELOW_M	= 0x00007f80,
437 	KCOARSELOW_S	= 7,
438 	ADCSAT_ICOUNT_M	= 0x0001f800,
439 	ADCSAT_ICOUNT_S	= 11,
440 	ADCSAT_THRESH_M	= 0x000007e0,
441 	ADCSAT_THRESH_S	= 5
442 };
443 
444 /*
445  * Recalibrate the lower PHY chips to account for temperature/environment
446  * changes.
447  */
448 HAL_BOOL
449 ar5210PerCalibrationN(struct ath_hal *ah,
450 	struct ieee80211_channel *chan, u_int chainMask,
451 	HAL_BOOL longCal, HAL_BOOL *isCalDone)
452 {
453 	uint32_t regBeacon;
454 	uint32_t reg9858, reg985c, reg9868;
455 	HAL_CHANNEL_INTERNAL *ichan;
456 
457 	ichan = ath_hal_checkchannel(ah, chan);
458 	if (ichan == AH_NULL)
459 		return AH_FALSE;
460 	/* Disable tx and rx */
461 	ar5210UpdateDiagReg(ah,
462 		OS_REG_READ(ah, AR_DIAG_SW) | (AR_DIAG_SW_DIS_TX | AR_DIAG_SW_DIS_RX));
463 
464 	/* Disable Beacon Enable */
465 	regBeacon = OS_REG_READ(ah, AR_BEACON);
466 	OS_REG_WRITE(ah, AR_BEACON, regBeacon & ~AR_BEACON_EN);
467 
468 	/* Delay 4ms to ensure that all tx and rx activity has ceased */
469 	OS_DELAY(4000);
470 
471 	/* Disable AGC to radio traffic */
472 	OS_REG_WRITE(ah, 0x9808, OS_REG_READ(ah, 0x9808) | 0x08000000);
473 	/* Wait for the AGC traffic to cease. */
474 	OS_DELAY(10);
475 
476 	/* Change Channel to relock synth */
477 	if (!ar5210SetChannel(ah, chan))
478 		return AH_FALSE;
479 
480 	/* wait for the synthesizer lock to stabilize */
481 	OS_DELAY(1000);
482 
483 	/* Re-enable AGC to radio traffic */
484 	OS_REG_WRITE(ah, 0x9808, OS_REG_READ(ah, 0x9808) & (~0x08000000));
485 
486 	/*
487 	 * Configure the AGC so that it is highly unlikely (if not
488 	 * impossible) for it to send any gain changes to the analog
489 	 * chip.  We store off the current values so that they can
490 	 * be rewritten below. Setting the following values:
491 	 * firpwr	 = -1
492 	 * Kcoursehigh   = -1
493 	 * Kcourselow	 = -127
494 	 * ADCsat_icount = 2
495 	 * ADCsat_thresh = 12
496 	 */
497 	reg9858 = OS_REG_READ(ah, 0x9858);
498 	reg985c = OS_REG_READ(ah, 0x985c);
499 	reg9868 = OS_REG_READ(ah, 0x9868);
500 
501 	OS_REG_WRITE(ah, 0x9858, (reg9858 & ~FIRPWR_M) |
502 					 ((-1 << FIRPWR_S) & FIRPWR_M));
503 	OS_REG_WRITE(ah, 0x985c,
504 		 (reg985c & ~(KCOARSEHIGH_M | KCOARSELOW_M)) |
505 		 ((-1 << KCOARSEHIGH_S) & KCOARSEHIGH_M) |
506 		 ((-127 << KCOARSELOW_S) & KCOARSELOW_M));
507 	OS_REG_WRITE(ah, 0x9868,
508 		 (reg9868 & ~(ADCSAT_ICOUNT_M | ADCSAT_THRESH_M)) |
509 		 ((2 << ADCSAT_ICOUNT_S) & ADCSAT_ICOUNT_M) |
510 		 ((12 << ADCSAT_THRESH_S) & ADCSAT_THRESH_M));
511 
512 	/* Wait for AGC changes to be enacted */
513 	OS_DELAY(20);
514 
515 	/*
516 	 * We disable RF mix/gain stages for the PGA to avoid a
517 	 * race condition that will occur with receiving a frame
518 	 * and performing the AGC calibration.  This will be
519 	 * re-enabled at the end of offset cal.  We turn off AGC
520 	 * writes during this write as it will go over the analog bus.
521 	 */
522 	OS_REG_WRITE(ah, 0x9808, OS_REG_READ(ah, 0x9808) | 0x08000000);
523 	OS_DELAY(10);		 /* wait for the AGC traffic to cease */
524 	OS_REG_WRITE(ah, 0x98D4, 0x21);
525 	OS_REG_WRITE(ah, 0x9808, OS_REG_READ(ah, 0x9808) & (~0x08000000));
526 
527 	/* wait to make sure that additional AGC traffic has quiesced */
528 	OS_DELAY(1000);
529 
530 	/* AGC calibration (this was added to make the NF threshold check work) */
531 	OS_REG_WRITE(ah, AR_PHY_AGCCTL,
532 		 OS_REG_READ(ah, AR_PHY_AGCCTL) | AR_PHY_AGC_CAL);
533 	if (!ath_hal_wait(ah, AR_PHY_AGCCTL, AR_PHY_AGC_CAL, 0)) {
534 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: AGC calibration timeout\n",
535 		    __func__);
536 	}
537 
538 	/* Rewrite our AGC values we stored off earlier (return AGC to normal operation) */
539 	OS_REG_WRITE(ah, 0x9858, reg9858);
540 	OS_REG_WRITE(ah, 0x985c, reg985c);
541 	OS_REG_WRITE(ah, 0x9868, reg9868);
542 
543 	/* Perform noise floor and set status */
544 	if (!ar5210CalNoiseFloor(ah, ichan)) {
545 		/*
546 		 * Delay 5ms before retrying the noise floor -
547 		 * just to make sure.  We're in an error
548 		 * condition here
549 		 */
550 		HALDEBUG(ah, HAL_DEBUG_NFCAL | HAL_DEBUG_PERCAL,
551 		    "%s: Performing 2nd Noise Cal\n", __func__);
552 		OS_DELAY(5000);
553 		if (!ar5210CalNoiseFloor(ah, ichan))
554 			chan->ic_state |= IEEE80211_CHANSTATE_CWINT;
555 	}
556 
557 	/* Clear tx and rx disable bit */
558 	ar5210UpdateDiagReg(ah,
559 		 OS_REG_READ(ah, AR_DIAG_SW) & ~(AR_DIAG_SW_DIS_TX | AR_DIAG_SW_DIS_RX));
560 
561 	/* Re-enable Beacons */
562 	OS_REG_WRITE(ah, AR_BEACON, regBeacon);
563 
564 	*isCalDone = AH_TRUE;
565 
566 	return AH_TRUE;
567 }
568 
569 HAL_BOOL
570 ar5210PerCalibration(struct ath_hal *ah, struct ieee80211_channel *chan,
571 	HAL_BOOL *isIQdone)
572 {
573 	return ar5210PerCalibrationN(ah,  chan, 0x1, AH_TRUE, isIQdone);
574 }
575 
576 HAL_BOOL
577 ar5210ResetCalValid(struct ath_hal *ah, const struct ieee80211_channel *chan)
578 {
579 	return AH_TRUE;
580 }
581 
582 /*
583  * Writes the given reset bit mask into the reset register
584  */
585 static HAL_BOOL
586 ar5210SetResetReg(struct ath_hal *ah, uint32_t resetMask, u_int delay)
587 {
588 	uint32_t mask = resetMask ? resetMask : ~0;
589 	HAL_BOOL rt;
590 
591 	OS_REG_WRITE(ah, AR_RC, resetMask);
592 	/* need to wait at least 128 clocks when reseting PCI before read */
593 	OS_DELAY(delay);
594 
595 	resetMask &= AR_RC_RPCU | AR_RC_RDMA | AR_RC_RPHY | AR_RC_RMAC;
596 	mask &= AR_RC_RPCU | AR_RC_RDMA | AR_RC_RPHY | AR_RC_RMAC;
597 	rt = ath_hal_wait(ah, AR_RC, mask, resetMask);
598         if ((resetMask & AR_RC_RMAC) == 0) {
599 		if (isBigEndian()) {
600 			/*
601 			 * Set CFG, little-endian for descriptor accesses.
602 			 */
603 			mask = INIT_CONFIG_STATUS | AR_CFG_SWTD | AR_CFG_SWRD;
604 			OS_REG_WRITE(ah, AR_CFG, mask);
605 		} else
606 			OS_REG_WRITE(ah, AR_CFG, INIT_CONFIG_STATUS);
607 	}
608 	return rt;
609 }
610 
611 
612 /*
613  * Returns: the pcdac value
614  */
615 static uint8_t
616 getPcdac(struct ath_hal *ah, const struct tpcMap *pRD, uint8_t dBm)
617 {
618 	int32_t	 i;
619 	int useNextEntry = AH_FALSE;
620 	uint32_t interp;
621 
622 	for (i = AR_TP_SCALING_ENTRIES - 1; i >= 0; i--) {
623 		/* Check for exact entry */
624 		if (dBm == AR_I2DBM(i)) {
625 			if (pRD->pcdac[i] != 63)
626 				return pRD->pcdac[i];
627 			useNextEntry = AH_TRUE;
628 		} else if (dBm + 1 == AR_I2DBM(i) && i > 0) {
629 			/* Interpolate for between entry with a logish scale */
630 			if (pRD->pcdac[i] != 63 && pRD->pcdac[i-1] != 63) {
631 				interp = (350 * (pRD->pcdac[i] - pRD->pcdac[i-1])) + 999;
632 				interp = (interp / 1000) + pRD->pcdac[i-1];
633 				return interp;
634 			}
635 			useNextEntry = AH_TRUE;
636 		} else if (useNextEntry == AH_TRUE) {
637 			/* Grab the next lowest */
638 			if (pRD->pcdac[i] != 63)
639 				return pRD->pcdac[i];
640 		}
641 	}
642 
643 	/* Return the lowest Entry if we haven't returned */
644 	for (i = 0; i < AR_TP_SCALING_ENTRIES; i++)
645 		if (pRD->pcdac[i] != 63)
646 			return pRD->pcdac[i];
647 
648 	/* No value to return from table */
649 #ifdef AH_DEBUG
650 	ath_hal_printf(ah, "%s: empty transmit power table?\n", __func__);
651 #endif
652 	return 1;
653 }
654 
655 /*
656  * Find or interpolates the gainF value from the table ptr.
657  */
658 static uint8_t
659 getGainF(struct ath_hal *ah, const struct tpcMap *pRD,
660 	uint8_t pcdac, uint8_t *dBm)
661 {
662 	uint32_t interp;
663 	int low, high, i;
664 
665 	low = high = -1;
666 
667 	for (i = 0; i < AR_TP_SCALING_ENTRIES; i++) {
668 		if(pRD->pcdac[i] == 63)
669 			continue;
670 		if (pcdac == pRD->pcdac[i]) {
671 			*dBm = AR_I2DBM(i);
672 			return pRD->gainF[i];  /* Exact Match */
673 		}
674 		if (pcdac > pRD->pcdac[i])
675 			low = i;
676 		if (pcdac < pRD->pcdac[i]) {
677 			high = i;
678 			if (low == -1) {
679 				*dBm = AR_I2DBM(i);
680 				/* PCDAC is lower than lowest setting */
681 				return pRD->gainF[i];
682 			}
683 			break;
684 		}
685 	}
686 	if (i >= AR_TP_SCALING_ENTRIES && low == -1) {
687 		/* No settings were found */
688 #ifdef AH_DEBUG
689 		ath_hal_printf(ah,
690 			"%s: no valid entries in the pcdac table: %d\n",
691 			__func__, pcdac);
692 #endif
693 		return 63;
694 	}
695 	if (i >= AR_TP_SCALING_ENTRIES) {
696 		/* PCDAC setting was above the max setting in the table */
697 		*dBm = AR_I2DBM(low);
698 		return pRD->gainF[low];
699 	}
700 	/* Only exact if table has no missing entries */
701 	*dBm = (low + high) + 3;
702 
703 	/*
704 	 * Perform interpolation between low and high values to find gainF
705 	 * linearly scale the pcdac between low and high
706 	 */
707 	interp = ((pcdac - pRD->pcdac[low]) * 1000) /
708 		  (pRD->pcdac[high] - pRD->pcdac[low]);
709 	/*
710 	 * Multiply the scale ratio by the gainF difference
711 	 * (plus a rnd up factor)
712 	 */
713 	interp = ((interp * (pRD->gainF[high] - pRD->gainF[low])) + 999) / 1000;
714 
715 	/* Add ratioed gain_f to low gain_f value */
716 	return interp + pRD->gainF[low];
717 }
718 
719 HAL_BOOL
720 ar5210SetTxPowerLimit(struct ath_hal *ah, uint32_t limit)
721 {
722 	AH_PRIVATE(ah)->ah_powerLimit = AH_MIN(limit, AR5210_MAX_RATE_POWER);
723 	/* XXX flush to h/w */
724 	return AH_TRUE;
725 }
726 
727 /*
728  * Get TXPower values and set them in the radio
729  */
730 static HAL_BOOL
731 setupPowerSettings(struct ath_hal *ah, const struct ieee80211_channel *chan,
732 	uint8_t cp[17])
733 {
734 	uint16_t freq = ath_hal_gethwchannel(ah, chan);
735 	const HAL_EEPROM_v1 *ee = AH_PRIVATE(ah)->ah_eeprom;
736 	uint8_t gainFRD, gainF36, gainF48, gainF54;
737 	uint8_t dBmRD, dBm36, dBm48, dBm54, dontcare;
738 	uint32_t rd, group;
739 	const struct tpcMap  *pRD;
740 
741 	/* Set OB/DB Values regardless of channel */
742 	cp[15] = (ee->ee_biasCurrents >> 4) & 0x7;
743 	cp[16] = ee->ee_biasCurrents & 0x7;
744 
745 	if (freq < 5170 || freq > 5320) {
746 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel %u\n",
747 		    __func__, freq);
748 		return AH_FALSE;
749 	}
750 
751 	HALASSERT(ee->ee_version >= AR_EEPROM_VER1 &&
752 	    ee->ee_version < AR_EEPROM_VER3);
753 
754 	/* Match regulatory domain */
755 	for (rd = 0; rd < AR_REG_DOMAINS_MAX; rd++)
756 		if (AH_PRIVATE(ah)->ah_currentRD == ee->ee_regDomain[rd])
757 			break;
758 	if (rd == AR_REG_DOMAINS_MAX) {
759 #ifdef AH_DEBUG
760 		ath_hal_printf(ah,
761 			"%s: no calibrated regulatory domain matches the "
762 			"current regularly domain (0x%0x)\n", __func__,
763 			AH_PRIVATE(ah)->ah_currentRD);
764 #endif
765 		return AH_FALSE;
766 	}
767 	group = ((freq - 5170) / 10);
768 
769 	if (group > 11) {
770 		/* Pull 5.29 into the 5.27 group */
771 		group--;
772 	}
773 
774 	/* Integer divide will set group from 0 to 4 */
775 	group = group / 3;
776 	pRD   = &ee->ee_tpc[group];
777 
778 	/* Set PC DAC Values */
779 	cp[14] = pRD->regdmn[rd];
780 	cp[9]  = AH_MIN(pRD->regdmn[rd], pRD->rate36);
781 	cp[8]  = AH_MIN(pRD->regdmn[rd], pRD->rate48);
782 	cp[7]  = AH_MIN(pRD->regdmn[rd], pRD->rate54);
783 
784 	/* Find Corresponding gainF values for RD, 36, 48, 54 */
785 	gainFRD = getGainF(ah, pRD, pRD->regdmn[rd], &dBmRD);
786 	gainF36 = getGainF(ah, pRD, cp[9], &dBm36);
787 	gainF48 = getGainF(ah, pRD, cp[8], &dBm48);
788 	gainF54 = getGainF(ah, pRD, cp[7], &dBm54);
789 
790 	/* Power Scale if requested */
791 	if (AH_PRIVATE(ah)->ah_tpScale != HAL_TP_SCALE_MAX) {
792 		static const uint16_t tpcScaleReductionTable[5] =
793 			{ 0, 3, 6, 9, AR5210_MAX_RATE_POWER };
794 		uint16_t tpScale;
795 
796 		tpScale = tpcScaleReductionTable[AH_PRIVATE(ah)->ah_tpScale];
797 		if (dBmRD < tpScale+3)
798 			dBmRD = 3;		/* min */
799 		else
800 			dBmRD -= tpScale;
801 		cp[14]  = getPcdac(ah, pRD, dBmRD);
802 		gainFRD = getGainF(ah, pRD, cp[14], &dontcare);
803 		dBm36   = AH_MIN(dBm36, dBmRD);
804 		cp[9]   = getPcdac(ah, pRD, dBm36);
805 		gainF36 = getGainF(ah, pRD, cp[9], &dontcare);
806 		dBm48   = AH_MIN(dBm48, dBmRD);
807 		cp[8]   = getPcdac(ah, pRD, dBm48);
808 		gainF48 = getGainF(ah, pRD, cp[8], &dontcare);
809 		dBm54   = AH_MIN(dBm54, dBmRD);
810 		cp[7]   = getPcdac(ah, pRD, dBm54);
811 		gainF54 = getGainF(ah, pRD, cp[7], &dontcare);
812 	}
813 	/* Record current dBm at rate 6 */
814 	AH_PRIVATE(ah)->ah_maxPowerLevel = 2*dBmRD;
815 
816 	cp[13] = cp[12] = cp[11] = cp[10] = cp[14];
817 
818 	/* Set GainF Values */
819 	cp[0] = gainFRD - gainF54;
820 	cp[1] = gainFRD - gainF48;
821 	cp[2] = gainFRD - gainF36;
822 	/* 9, 12, 18, 24 have no gain_delta from 6 */
823 	cp[3] = cp[4] = cp[5] = cp[6] = 0;
824 	return AH_TRUE;
825 }
826 
827 /*
828  * Places the device in and out of reset and then places sane
829  * values in the registers based on EEPROM config, initialization
830  * vectors (as determined by the mode), and station configuration
831  */
832 HAL_BOOL
833 ar5210SetTransmitPower(struct ath_hal *ah, const struct ieee80211_channel *chan)
834 {
835 #define	N(a)	(sizeof (a) / sizeof (a[0]))
836 	static const uint32_t pwr_regs_start[17] = {
837 		0x00000000, 0x00000000, 0x00000000,
838 		0x00000000, 0x00000000, 0xf0000000,
839 		0xcc000000, 0x00000000, 0x00000000,
840 		0x00000000, 0x0a000000, 0x000000e2,
841 		0x0a000020, 0x01000002, 0x01000018,
842 		0x40000000, 0x00000418
843 	};
844 	uint16_t i;
845 	uint8_t cp[sizeof(ar5k0007_pwrSettings)];
846 	uint32_t pwr_regs[17];
847 
848 	OS_MEMCPY(pwr_regs, pwr_regs_start, sizeof(pwr_regs));
849 	OS_MEMCPY(cp, ar5k0007_pwrSettings, sizeof(cp));
850 
851 	/* Check the EEPROM tx power calibration settings */
852 	if (!setupPowerSettings(ah, chan, cp)) {
853 #ifdef AH_DEBUG
854 		ath_hal_printf(ah, "%s: unable to setup power settings\n",
855 			__func__);
856 #endif
857 		return AH_FALSE;
858 	}
859 	if (cp[15] < 1 || cp[15] > 5) {
860 #ifdef AH_DEBUG
861 		ath_hal_printf(ah, "%s: OB out of range (%u)\n",
862 			__func__, cp[15]);
863 #endif
864 		return AH_FALSE;
865 	}
866 	if (cp[16] < 1 || cp[16] > 5) {
867 #ifdef AH_DEBUG
868 		ath_hal_printf(ah, "%s: DB out of range (%u)\n",
869 			__func__, cp[16]);
870 #endif
871 		return AH_FALSE;
872 	}
873 
874 	/* reverse bits of the transmit power array */
875 	for (i = 0; i < 7; i++)
876 		cp[i] = ath_hal_reverseBits(cp[i], 5);
877 	for (i = 7; i < 15; i++)
878 		cp[i] = ath_hal_reverseBits(cp[i], 6);
879 
880 	/* merge transmit power values into the register - quite gross */
881 	pwr_regs[0] |= ((cp[1] << 5) & 0xE0) | (cp[0] & 0x1F);
882 	pwr_regs[1] |= ((cp[3] << 7) & 0x80) | ((cp[2] << 2) & 0x7C) |
883 			((cp[1] >> 3) & 0x03);
884 	pwr_regs[2] |= ((cp[4] << 4) & 0xF0) | ((cp[3] >> 1) & 0x0F);
885 	pwr_regs[3] |= ((cp[6] << 6) & 0xC0) | ((cp[5] << 1) & 0x3E) |
886 		       ((cp[4] >> 4) & 0x01);
887 	pwr_regs[4] |= ((cp[7] << 3) & 0xF8) | ((cp[6] >> 2) & 0x07);
888 	pwr_regs[5] |= ((cp[9] << 7) & 0x80) | ((cp[8] << 1) & 0x7E) |
889 			((cp[7] >> 5) & 0x01);
890 	pwr_regs[6] |= ((cp[10] << 5) & 0xE0) | ((cp[9] >> 1) & 0x1F);
891 	pwr_regs[7] |= ((cp[11] << 3) & 0xF8) | ((cp[10] >> 3) & 0x07);
892 	pwr_regs[8] |= ((cp[12] << 1) & 0x7E) | ((cp[11] >> 5) & 0x01);
893 	pwr_regs[9] |= ((cp[13] << 5) & 0xE0);
894 	pwr_regs[10] |= ((cp[14] << 3) & 0xF8) | ((cp[13] >> 3) & 0x07);
895 	pwr_regs[11] |= ((cp[14] >> 5) & 0x01);
896 
897 	/* Set OB */
898 	pwr_regs[8] |=  (ath_hal_reverseBits(cp[15], 3) << 7) & 0x80;
899 	pwr_regs[9] |=  (ath_hal_reverseBits(cp[15], 3) >> 1) & 0x03;
900 
901 	/* Set DB */
902 	pwr_regs[9] |=  (ath_hal_reverseBits(cp[16], 3) << 2) & 0x1C;
903 
904 	/* Write the registers */
905 	for (i = 0; i < N(pwr_regs)-1; i++)
906 		OS_REG_WRITE(ah, 0x0000989c, pwr_regs[i]);
907 	/* last write is a flush */
908 	OS_REG_WRITE(ah, 0x000098d4, pwr_regs[i]);
909 
910 	return AH_TRUE;
911 #undef N
912 }
913 
914 /*
915  * Takes the MHz channel value and sets the Channel value
916  *
917  * ASSUMES: Writes enabled to analog bus before AGC is active
918  *   or by disabling the AGC.
919  */
920 static HAL_BOOL
921 ar5210SetChannel(struct ath_hal *ah, struct ieee80211_channel *chan)
922 {
923 	uint16_t freq = ath_hal_gethwchannel(ah, chan);
924 	uint32_t data;
925 
926 	/* Set the Channel */
927 	data = ath_hal_reverseBits((freq - 5120)/10, 5);
928 	data = (data << 1) | 0x41;
929 	OS_REG_WRITE(ah, AR_PHY(0x27), data);
930 	OS_REG_WRITE(ah, AR_PHY(0x30), 0);
931 	AH_PRIVATE(ah)->ah_curchan = chan;
932 	return AH_TRUE;
933 }
934 
935 int16_t
936 ar5210GetNoiseFloor(struct ath_hal *ah)
937 {
938 	int16_t nf;
939 
940 	nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff;
941 	if (nf & 0x100)
942 		nf = 0 - ((nf ^ 0x1ff) + 1);
943 	return nf;
944 }
945 
946 #define NORMAL_NF_THRESH (-72)
947 /*
948  * Peform the noisefloor calibration and check for
949  * any constant channel interference
950  *
951  * Returns: TRUE for a successful noise floor calibration; else FALSE
952  */
953 HAL_BOOL
954 ar5210CalNoiseFloor(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *ichan)
955 {
956 	int32_t nf, nfLoops;
957 
958 	/* Calibrate the noise floor */
959 	OS_REG_WRITE(ah, AR_PHY_AGCCTL,
960 		OS_REG_READ(ah, AR_PHY_AGCCTL) | AR_PHY_AGC_NF);
961 
962 	/* Do not read noise floor until it has done the first update */
963 	if (!ath_hal_wait(ah, AR_PHY_AGCCTL, AR_PHY_AGC_NF, 0)) {
964 #ifdef ATH_HAL_DEBUG
965 		ath_hal_printf(ah, " -PHY NF Reg state: 0x%x\n",
966 			OS_REG_READ(ah, AR_PHY_AGCCTL));
967 		ath_hal_printf(ah, " -MAC Reset Reg state: 0x%x\n",
968 			OS_REG_READ(ah, AR_RC));
969 		ath_hal_printf(ah, " -PHY Active Reg state: 0x%x\n",
970 			OS_REG_READ(ah, AR_PHY_ACTIVE));
971 #endif /* ATH_HAL_DEBUG */
972 		return AH_FALSE;
973 	}
974 
975 	nf = 0;
976 	/* Keep checking until the floor is below the threshold or the nf is done */
977 	for (nfLoops = 0; ((nfLoops < 21) && (nf > NORMAL_NF_THRESH)); nfLoops++) {
978 		OS_DELAY(1000); /* Sleep for 1 ms */
979 		nf = ar5210GetNoiseFloor(ah);
980 	}
981 
982 	if (nf > NORMAL_NF_THRESH) {
983 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: Bad noise cal %d\n",
984 		    __func__, nf);
985 		ichan->rawNoiseFloor = 0;
986 		return AH_FALSE;
987 	}
988 	ichan->rawNoiseFloor = nf;
989 	return AH_TRUE;
990 }
991 
992 /*
993  * Adjust NF based on statistical values for 5GHz frequencies.
994  */
995 int16_t
996 ar5210GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c)
997 {
998 	return 0;
999 }
1000 
1001 HAL_RFGAIN
1002 ar5210GetRfgain(struct ath_hal *ah)
1003 {
1004 	return HAL_RFGAIN_INACTIVE;
1005 }
1006