1 /* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2004 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19 #include "opt_ah.h" 20 21 #include "ah.h" 22 #include "ah_internal.h" 23 24 #include "ar5210/ar5210.h" 25 #include "ar5210/ar5210reg.h" 26 #include "ar5210/ar5210phy.h" 27 28 #include "ah_eeprom_v1.h" 29 30 typedef struct { 31 uint32_t Offset; 32 uint32_t Value; 33 } REGISTER_VAL; 34 35 static const REGISTER_VAL ar5k0007_init[] = { 36 #include "ar5210/ar5k_0007.ini" 37 }; 38 39 /* Default Power Settings for channels outside of EEPROM range */ 40 static const uint8_t ar5k0007_pwrSettings[17] = { 41 /* gain delta pc dac */ 42 /* 54 48 36 24 18 12 9 54 48 36 24 18 12 9 6 ob db */ 43 9, 9, 0, 0, 0, 0, 0, 2, 2, 6, 6, 6, 6, 6, 6, 2, 2 44 }; 45 46 /* 47 * The delay, in usecs, between writing AR_RC with a reset 48 * request and waiting for the chip to settle. If this is 49 * too short then the chip does not come out of sleep state. 50 * Note this value was empirically derived and may be dependent 51 * on the host machine (don't know--the problem was identified 52 * on an IBM 570e laptop; 10us delays worked on other systems). 53 */ 54 #define AR_RC_SETTLE_TIME 20000 55 56 static HAL_BOOL ar5210SetResetReg(struct ath_hal *, 57 uint32_t resetMask, u_int delay); 58 static HAL_BOOL ar5210SetChannel(struct ath_hal *, struct ieee80211_channel *); 59 static void ar5210SetOperatingMode(struct ath_hal *, int opmode); 60 61 /* 62 * Places the device in and out of reset and then places sane 63 * values in the registers based on EEPROM config, initialization 64 * vectors (as determined by the mode), and station configuration 65 * 66 * bChannelChange is used to preserve DMA/PCU registers across 67 * a HW Reset during channel change. 68 */ 69 HAL_BOOL 70 ar5210Reset(struct ath_hal *ah, HAL_OPMODE opmode, 71 struct ieee80211_channel *chan, HAL_BOOL bChannelChange, 72 HAL_STATUS *status) 73 { 74 #define N(a) (sizeof (a) /sizeof (a[0])) 75 #define FAIL(_code) do { ecode = _code; goto bad; } while (0) 76 struct ath_hal_5210 *ahp = AH5210(ah); 77 const HAL_EEPROM_v1 *ee = AH_PRIVATE(ah)->ah_eeprom; 78 HAL_CHANNEL_INTERNAL *ichan; 79 HAL_STATUS ecode; 80 uint32_t ledstate; 81 int i, q; 82 83 HALDEBUG(ah, HAL_DEBUG_RESET, 84 "%s: opmode %u channel %u/0x%x %s channel\n", __func__, 85 opmode, chan->ic_freq, chan->ic_flags, 86 bChannelChange ? "change" : "same"); 87 88 if (!IEEE80211_IS_CHAN_5GHZ(chan)) { 89 /* Only 11a mode */ 90 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: channel not 5Ghz\n", __func__); 91 FAIL(HAL_EINVAL); 92 } 93 /* 94 * Map public channel to private. 95 */ 96 ichan = ath_hal_checkchannel(ah, chan); 97 if (ichan == AH_NULL) { 98 HALDEBUG(ah, HAL_DEBUG_ANY, 99 "%s: invalid channel %u/0x%x; no mapping\n", 100 __func__, chan->ic_freq, chan->ic_flags); 101 FAIL(HAL_EINVAL); 102 } 103 switch (opmode) { 104 case HAL_M_STA: 105 case HAL_M_IBSS: 106 case HAL_M_HOSTAP: 107 case HAL_M_MONITOR: 108 break; 109 default: 110 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid operating mode %u\n", 111 __func__, opmode); 112 FAIL(HAL_EINVAL); 113 break; 114 } 115 116 ledstate = OS_REG_READ(ah, AR_PCICFG) & 117 (AR_PCICFG_LED_PEND | AR_PCICFG_LED_ACT); 118 119 if (!ar5210ChipReset(ah, chan)) { 120 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", 121 __func__); 122 FAIL(HAL_EIO); 123 } 124 125 OS_REG_WRITE(ah, AR_STA_ID0, LE_READ_4(ahp->ah_macaddr)); 126 OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4)); 127 ar5210SetOperatingMode(ah, opmode); 128 129 switch (opmode) { 130 case HAL_M_HOSTAP: 131 OS_REG_WRITE(ah, AR_BCR, INIT_BCON_CNTRL_REG); 132 OS_REG_WRITE(ah, AR_PCICFG, 133 AR_PCICFG_LED_ACT | AR_PCICFG_LED_BCTL); 134 break; 135 case HAL_M_IBSS: 136 OS_REG_WRITE(ah, AR_BCR, INIT_BCON_CNTRL_REG | AR_BCR_BCMD); 137 OS_REG_WRITE(ah, AR_PCICFG, 138 AR_PCICFG_CLKRUNEN | AR_PCICFG_LED_PEND | AR_PCICFG_LED_BCTL); 139 break; 140 case HAL_M_STA: 141 OS_REG_WRITE(ah, AR_BCR, INIT_BCON_CNTRL_REG); 142 OS_REG_WRITE(ah, AR_PCICFG, 143 AR_PCICFG_CLKRUNEN | AR_PCICFG_LED_PEND | AR_PCICFG_LED_BCTL); 144 break; 145 case HAL_M_MONITOR: 146 OS_REG_WRITE(ah, AR_BCR, INIT_BCON_CNTRL_REG); 147 OS_REG_WRITE(ah, AR_PCICFG, 148 AR_PCICFG_LED_ACT | AR_PCICFG_LED_BCTL); 149 break; 150 } 151 152 /* Restore previous led state */ 153 OS_REG_WRITE(ah, AR_PCICFG, OS_REG_READ(ah, AR_PCICFG) | ledstate); 154 155 OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid)); 156 OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4)); 157 158 OS_REG_WRITE(ah, AR_TXDP0, 0); 159 OS_REG_WRITE(ah, AR_TXDP1, 0); 160 OS_REG_WRITE(ah, AR_RXDP, 0); 161 162 /* 163 * Initialize interrupt state. 164 */ 165 (void) OS_REG_READ(ah, AR_ISR); /* cleared on read */ 166 OS_REG_WRITE(ah, AR_IMR, 0); 167 OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE); 168 ahp->ah_maskReg = 0; 169 170 (void) OS_REG_READ(ah, AR_BSR); /* cleared on read */ 171 OS_REG_WRITE(ah, AR_TXCFG, AR_DMASIZE_128B); 172 OS_REG_WRITE(ah, AR_RXCFG, AR_DMASIZE_128B); 173 174 OS_REG_WRITE(ah, AR_TOPS, 8); /* timeout prescale */ 175 OS_REG_WRITE(ah, AR_RXNOFRM, 8); /* RX no frame timeout */ 176 OS_REG_WRITE(ah, AR_RPGTO, 0); /* RX frame gap timeout */ 177 OS_REG_WRITE(ah, AR_TXNOFRM, 0); /* TX no frame timeout */ 178 179 OS_REG_WRITE(ah, AR_SFR, 0); 180 OS_REG_WRITE(ah, AR_MIBC, 0); /* unfreeze ctrs + clr state */ 181 OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr); 182 OS_REG_WRITE(ah, AR_CFP_DUR, 0); 183 184 ar5210SetRxFilter(ah, 0); /* nothing for now */ 185 OS_REG_WRITE(ah, AR_MCAST_FIL0, 0); /* multicast filter */ 186 OS_REG_WRITE(ah, AR_MCAST_FIL1, 0); /* XXX was 2 */ 187 188 OS_REG_WRITE(ah, AR_TX_MASK0, 0); 189 OS_REG_WRITE(ah, AR_TX_MASK1, 0); 190 OS_REG_WRITE(ah, AR_CLR_TMASK, 1); 191 OS_REG_WRITE(ah, AR_TRIG_LEV, 1); /* minimum */ 192 193 OS_REG_WRITE(ah, AR_DIAG_SW, 0); 194 195 OS_REG_WRITE(ah, AR_CFP_PERIOD, 0); 196 OS_REG_WRITE(ah, AR_TIMER0, 0); /* next beacon time */ 197 OS_REG_WRITE(ah, AR_TSF_L32, 0); /* local clock */ 198 OS_REG_WRITE(ah, AR_TIMER1, ~0); /* next DMA beacon alert */ 199 OS_REG_WRITE(ah, AR_TIMER2, ~0); /* next SW beacon alert */ 200 OS_REG_WRITE(ah, AR_TIMER3, 1); /* next ATIM window */ 201 202 /* Write the INI values for PHYreg initialization */ 203 for (i = 0; i < N(ar5k0007_init); i++) { 204 uint32_t reg = ar5k0007_init[i].Offset; 205 /* On channel change, don't reset the PCU registers */ 206 if (!(bChannelChange && (0x8000 <= reg && reg < 0x9000))) 207 OS_REG_WRITE(ah, reg, ar5k0007_init[i].Value); 208 } 209 210 /* Setup the transmit power values for cards since 0x0[0-2]05 */ 211 if (!ar5210SetTransmitPower(ah, chan)) { 212 HALDEBUG(ah, HAL_DEBUG_ANY, 213 "%s: error init'ing transmit power\n", __func__); 214 FAIL(HAL_EIO); 215 } 216 217 OS_REG_WRITE(ah, AR_PHY(10), 218 (OS_REG_READ(ah, AR_PHY(10)) & 0xFFFF00FF) | 219 (ee->ee_xlnaOn << 8)); 220 OS_REG_WRITE(ah, AR_PHY(13), 221 (ee->ee_xpaOff << 24) | (ee->ee_xpaOff << 16) | 222 (ee->ee_xpaOn << 8) | ee->ee_xpaOn); 223 OS_REG_WRITE(ah, AR_PHY(17), 224 (OS_REG_READ(ah, AR_PHY(17)) & 0xFFFFC07F) | 225 ((ee->ee_antenna >> 1) & 0x3F80)); 226 OS_REG_WRITE(ah, AR_PHY(18), 227 (OS_REG_READ(ah, AR_PHY(18)) & 0xFFFC0FFF) | 228 ((ee->ee_antenna << 10) & 0x3F000)); 229 OS_REG_WRITE(ah, AR_PHY(25), 230 (OS_REG_READ(ah, AR_PHY(25)) & 0xFFF80FFF) | 231 ((ee->ee_thresh62 << 12) & 0x7F000)); 232 OS_REG_WRITE(ah, AR_PHY(68), 233 (OS_REG_READ(ah, AR_PHY(68)) & 0xFFFFFFFC) | 234 (ee->ee_antenna & 0x3)); 235 236 if (!ar5210SetChannel(ah, chan)) { 237 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set channel\n", 238 __func__); 239 FAIL(HAL_EIO); 240 } 241 if (bChannelChange && !IEEE80211_IS_CHAN_DFS(chan)) 242 chan->ic_state &= ~IEEE80211_CHANSTATE_CWINT; 243 244 /* Activate the PHY */ 245 OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ENABLE); 246 247 OS_DELAY(1000); /* Wait a bit (1 msec) */ 248 249 /* calibrate the HW and poll the bit going to 0 for completion */ 250 OS_REG_WRITE(ah, AR_PHY_AGCCTL, 251 OS_REG_READ(ah, AR_PHY_AGCCTL) | AR_PHY_AGC_CAL); 252 (void) ath_hal_wait(ah, AR_PHY_AGCCTL, AR_PHY_AGC_CAL, 0); 253 254 /* Perform noise floor calibration and set status */ 255 if (!ar5210CalNoiseFloor(ah, ichan)) { 256 chan->ic_state |= IEEE80211_CHANSTATE_CWINT; 257 HALDEBUG(ah, HAL_DEBUG_ANY, 258 "%s: noise floor calibration failed\n", __func__); 259 FAIL(HAL_EIO); 260 } 261 262 for (q = 0; q < HAL_NUM_TX_QUEUES; q++) 263 ar5210ResetTxQueue(ah, q); 264 265 if (AH_PRIVATE(ah)->ah_rfkillEnabled) 266 ar5210EnableRfKill(ah); 267 268 /* 269 * Writing to AR_BEACON will start timers. Hence it should be 270 * the last register to be written. Do not reset tsf, do not 271 * enable beacons at this point, but preserve other values 272 * like beaconInterval. 273 */ 274 OS_REG_WRITE(ah, AR_BEACON, 275 (OS_REG_READ(ah, AR_BEACON) & 276 ~(AR_BEACON_EN | AR_BEACON_RESET_TSF))); 277 278 /* Restore user-specified slot time and timeouts */ 279 if (ahp->ah_sifstime != (u_int) -1) 280 ar5210SetSifsTime(ah, ahp->ah_sifstime); 281 if (ahp->ah_slottime != (u_int) -1) 282 ar5210SetSlotTime(ah, ahp->ah_slottime); 283 if (ahp->ah_acktimeout != (u_int) -1) 284 ar5210SetAckTimeout(ah, ahp->ah_acktimeout); 285 if (ahp->ah_ctstimeout != (u_int) -1) 286 ar5210SetCTSTimeout(ah, ahp->ah_ctstimeout); 287 if (AH_PRIVATE(ah)->ah_diagreg != 0) 288 OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg); 289 290 AH_PRIVATE(ah)->ah_opmode = opmode; /* record operating mode */ 291 292 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: done\n", __func__); 293 294 return AH_TRUE; 295 bad: 296 if (status != AH_NULL) 297 *status = ecode; 298 return AH_FALSE; 299 #undef FAIL 300 #undef N 301 } 302 303 static void 304 ar5210SetOperatingMode(struct ath_hal *ah, int opmode) 305 { 306 struct ath_hal_5210 *ahp = AH5210(ah); 307 uint32_t val; 308 309 val = OS_REG_READ(ah, AR_STA_ID1) & 0xffff; 310 switch (opmode) { 311 case HAL_M_HOSTAP: 312 OS_REG_WRITE(ah, AR_STA_ID1, val 313 | AR_STA_ID1_AP 314 | AR_STA_ID1_NO_PSPOLL 315 | AR_STA_ID1_DESC_ANTENNA 316 | ahp->ah_staId1Defaults); 317 break; 318 case HAL_M_IBSS: 319 OS_REG_WRITE(ah, AR_STA_ID1, val 320 | AR_STA_ID1_ADHOC 321 | AR_STA_ID1_NO_PSPOLL 322 | AR_STA_ID1_DESC_ANTENNA 323 | ahp->ah_staId1Defaults); 324 break; 325 case HAL_M_STA: 326 OS_REG_WRITE(ah, AR_STA_ID1, val 327 | AR_STA_ID1_NO_PSPOLL 328 | AR_STA_ID1_PWR_SV 329 | ahp->ah_staId1Defaults); 330 break; 331 case HAL_M_MONITOR: 332 OS_REG_WRITE(ah, AR_STA_ID1, val 333 | AR_STA_ID1_NO_PSPOLL 334 | ahp->ah_staId1Defaults); 335 break; 336 } 337 } 338 339 void 340 ar5210SetPCUConfig(struct ath_hal *ah) 341 { 342 ar5210SetOperatingMode(ah, AH_PRIVATE(ah)->ah_opmode); 343 } 344 345 /* 346 * Places the PHY and Radio chips into reset. A full reset 347 * must be called to leave this state. The PCI/MAC/PCU are 348 * not placed into reset as we must receive interrupt to 349 * re-enable the hardware. 350 */ 351 HAL_BOOL 352 ar5210PhyDisable(struct ath_hal *ah) 353 { 354 return ar5210SetResetReg(ah, AR_RC_RPHY, 10); 355 } 356 357 /* 358 * Places all of hardware into reset 359 */ 360 HAL_BOOL 361 ar5210Disable(struct ath_hal *ah) 362 { 363 #define AR_RC_HW (AR_RC_RPCU | AR_RC_RDMA | AR_RC_RPHY | AR_RC_RMAC) 364 if (!ar5210SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 365 return AH_FALSE; 366 367 /* 368 * Reset the HW - PCI must be reset after the rest of the 369 * device has been reset 370 */ 371 if (!ar5210SetResetReg(ah, AR_RC_HW, AR_RC_SETTLE_TIME)) 372 return AH_FALSE; 373 OS_DELAY(1000); 374 (void) ar5210SetResetReg(ah, AR_RC_HW | AR_RC_RPCI, AR_RC_SETTLE_TIME); 375 OS_DELAY(2100); /* 8245 @ 96Mhz hangs with 2000us. */ 376 377 return AH_TRUE; 378 #undef AR_RC_HW 379 } 380 381 /* 382 * Places the hardware into reset and then pulls it out of reset 383 */ 384 HAL_BOOL 385 ar5210ChipReset(struct ath_hal *ah, struct ieee80211_channel *chan) 386 { 387 #define AR_RC_HW (AR_RC_RPCU | AR_RC_RDMA | AR_RC_RPHY | AR_RC_RMAC) 388 389 HALDEBUG(ah, HAL_DEBUG_RESET, "%s turbo %s\n", __func__, 390 chan && IEEE80211_IS_CHAN_TURBO(chan) ? 391 "enabled" : "disabled"); 392 393 if (!ar5210SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 394 return AH_FALSE; 395 396 /* Place chip in turbo before reset to cleanly reset clocks */ 397 OS_REG_WRITE(ah, AR_PHY_FRCTL, 398 chan && IEEE80211_IS_CHAN_TURBO(chan) ? AR_PHY_TURBO_MODE : 0); 399 400 /* 401 * Reset the HW. 402 * PCI must be reset after the rest of the device has been reset. 403 */ 404 if (!ar5210SetResetReg(ah, AR_RC_HW, AR_RC_SETTLE_TIME)) 405 return AH_FALSE; 406 OS_DELAY(1000); 407 if (!ar5210SetResetReg(ah, AR_RC_HW | AR_RC_RPCI, AR_RC_SETTLE_TIME)) 408 return AH_FALSE; 409 OS_DELAY(2100); /* 8245 @ 96Mhz hangs with 2000us. */ 410 411 /* 412 * Bring out of sleep mode (AGAIN) 413 * 414 * WARNING WARNING WARNING 415 * 416 * There is a problem with the chip where it doesn't always indicate 417 * that it's awake, so initializePowerUp() will fail. 418 */ 419 if (!ar5210SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 420 return AH_FALSE; 421 422 /* Clear warm reset reg */ 423 return ar5210SetResetReg(ah, 0, 10); 424 #undef AR_RC_HW 425 } 426 427 enum { 428 FIRPWR_M = 0x03fc0000, 429 FIRPWR_S = 18, 430 KCOARSEHIGH_M = 0x003f8000, 431 KCOARSEHIGH_S = 15, 432 KCOARSELOW_M = 0x00007f80, 433 KCOARSELOW_S = 7, 434 ADCSAT_ICOUNT_M = 0x0001f800, 435 ADCSAT_ICOUNT_S = 11, 436 ADCSAT_THRESH_M = 0x000007e0, 437 ADCSAT_THRESH_S = 5 438 }; 439 440 /* 441 * Recalibrate the lower PHY chips to account for temperature/environment 442 * changes. 443 */ 444 HAL_BOOL 445 ar5210PerCalibrationN(struct ath_hal *ah, 446 struct ieee80211_channel *chan, u_int chainMask, 447 HAL_BOOL longCal, HAL_BOOL *isCalDone) 448 { 449 uint32_t regBeacon; 450 uint32_t reg9858, reg985c, reg9868; 451 HAL_CHANNEL_INTERNAL *ichan; 452 453 ichan = ath_hal_checkchannel(ah, chan); 454 if (ichan == AH_NULL) 455 return AH_FALSE; 456 /* Disable tx and rx */ 457 OS_REG_WRITE(ah, AR_DIAG_SW, 458 OS_REG_READ(ah, AR_DIAG_SW) | (AR_DIAG_SW_DIS_TX | AR_DIAG_SW_DIS_RX)); 459 460 /* Disable Beacon Enable */ 461 regBeacon = OS_REG_READ(ah, AR_BEACON); 462 OS_REG_WRITE(ah, AR_BEACON, regBeacon & ~AR_BEACON_EN); 463 464 /* Delay 4ms to ensure that all tx and rx activity has ceased */ 465 OS_DELAY(4000); 466 467 /* Disable AGC to radio traffic */ 468 OS_REG_WRITE(ah, 0x9808, OS_REG_READ(ah, 0x9808) | 0x08000000); 469 /* Wait for the AGC traffic to cease. */ 470 OS_DELAY(10); 471 472 /* Change Channel to relock synth */ 473 if (!ar5210SetChannel(ah, chan)) 474 return AH_FALSE; 475 476 /* wait for the synthesizer lock to stabilize */ 477 OS_DELAY(1000); 478 479 /* Re-enable AGC to radio traffic */ 480 OS_REG_WRITE(ah, 0x9808, OS_REG_READ(ah, 0x9808) & (~0x08000000)); 481 482 /* 483 * Configure the AGC so that it is highly unlikely (if not 484 * impossible) for it to send any gain changes to the analog 485 * chip. We store off the current values so that they can 486 * be rewritten below. Setting the following values: 487 * firpwr = -1 488 * Kcoursehigh = -1 489 * Kcourselow = -127 490 * ADCsat_icount = 2 491 * ADCsat_thresh = 12 492 */ 493 reg9858 = OS_REG_READ(ah, 0x9858); 494 reg985c = OS_REG_READ(ah, 0x985c); 495 reg9868 = OS_REG_READ(ah, 0x9868); 496 497 OS_REG_WRITE(ah, 0x9858, (reg9858 & ~FIRPWR_M) | 498 ((-1 << FIRPWR_S) & FIRPWR_M)); 499 OS_REG_WRITE(ah, 0x985c, 500 (reg985c & ~(KCOARSEHIGH_M | KCOARSELOW_M)) | 501 ((-1 << KCOARSEHIGH_S) & KCOARSEHIGH_M) | 502 ((-127 << KCOARSELOW_S) & KCOARSELOW_M)); 503 OS_REG_WRITE(ah, 0x9868, 504 (reg9868 & ~(ADCSAT_ICOUNT_M | ADCSAT_THRESH_M)) | 505 ((2 << ADCSAT_ICOUNT_S) & ADCSAT_ICOUNT_M) | 506 ((12 << ADCSAT_THRESH_S) & ADCSAT_THRESH_M)); 507 508 /* Wait for AGC changes to be enacted */ 509 OS_DELAY(20); 510 511 /* 512 * We disable RF mix/gain stages for the PGA to avoid a 513 * race condition that will occur with receiving a frame 514 * and performing the AGC calibration. This will be 515 * re-enabled at the end of offset cal. We turn off AGC 516 * writes during this write as it will go over the analog bus. 517 */ 518 OS_REG_WRITE(ah, 0x9808, OS_REG_READ(ah, 0x9808) | 0x08000000); 519 OS_DELAY(10); /* wait for the AGC traffic to cease */ 520 OS_REG_WRITE(ah, 0x98D4, 0x21); 521 OS_REG_WRITE(ah, 0x9808, OS_REG_READ(ah, 0x9808) & (~0x08000000)); 522 523 /* wait to make sure that additional AGC traffic has quiesced */ 524 OS_DELAY(1000); 525 526 /* AGC calibration (this was added to make the NF threshold check work) */ 527 OS_REG_WRITE(ah, AR_PHY_AGCCTL, 528 OS_REG_READ(ah, AR_PHY_AGCCTL) | AR_PHY_AGC_CAL); 529 if (!ath_hal_wait(ah, AR_PHY_AGCCTL, AR_PHY_AGC_CAL, 0)) 530 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: AGC calibration timeout\n", 531 __func__); 532 533 /* Rewrite our AGC values we stored off earlier (return AGC to normal operation) */ 534 OS_REG_WRITE(ah, 0x9858, reg9858); 535 OS_REG_WRITE(ah, 0x985c, reg985c); 536 OS_REG_WRITE(ah, 0x9868, reg9868); 537 538 /* Perform noise floor and set status */ 539 if (!ar5210CalNoiseFloor(ah, ichan)) { 540 /* 541 * Delay 5ms before retrying the noise floor - 542 * just to make sure. We're in an error 543 * condition here 544 */ 545 HALDEBUG(ah, HAL_DEBUG_NFCAL | HAL_DEBUG_PERCAL, 546 "%s: Performing 2nd Noise Cal\n", __func__); 547 OS_DELAY(5000); 548 if (!ar5210CalNoiseFloor(ah, ichan)) 549 chan->ic_state |= IEEE80211_CHANSTATE_CWINT; 550 } 551 552 /* Clear tx and rx disable bit */ 553 OS_REG_WRITE(ah, AR_DIAG_SW, 554 OS_REG_READ(ah, AR_DIAG_SW) & ~(AR_DIAG_SW_DIS_TX | AR_DIAG_SW_DIS_RX)); 555 556 /* Re-enable Beacons */ 557 OS_REG_WRITE(ah, AR_BEACON, regBeacon); 558 559 *isCalDone = AH_TRUE; 560 561 return AH_TRUE; 562 } 563 564 HAL_BOOL 565 ar5210PerCalibration(struct ath_hal *ah, struct ieee80211_channel *chan, 566 HAL_BOOL *isIQdone) 567 { 568 return ar5210PerCalibrationN(ah, chan, 0x1, AH_TRUE, isIQdone); 569 } 570 571 HAL_BOOL 572 ar5210ResetCalValid(struct ath_hal *ah, const struct ieee80211_channel *chan) 573 { 574 return AH_TRUE; 575 } 576 577 /* 578 * Writes the given reset bit mask into the reset register 579 */ 580 static HAL_BOOL 581 ar5210SetResetReg(struct ath_hal *ah, uint32_t resetMask, u_int delay) 582 { 583 uint32_t mask = resetMask ? resetMask : ~0; 584 HAL_BOOL rt; 585 586 OS_REG_WRITE(ah, AR_RC, resetMask); 587 /* need to wait at least 128 clocks when reseting PCI before read */ 588 OS_DELAY(delay); 589 590 resetMask &= AR_RC_RPCU | AR_RC_RDMA | AR_RC_RPHY | AR_RC_RMAC; 591 mask &= AR_RC_RPCU | AR_RC_RDMA | AR_RC_RPHY | AR_RC_RMAC; 592 rt = ath_hal_wait(ah, AR_RC, mask, resetMask); 593 if ((resetMask & AR_RC_RMAC) == 0) { 594 if (isBigEndian()) { 595 /* 596 * Set CFG, little-endian for register 597 * and descriptor accesses. 598 */ 599 mask = INIT_CONFIG_STATUS | 600 AR_CFG_SWTD | AR_CFG_SWRD | AR_CFG_SWRG; 601 OS_REG_WRITE(ah, AR_CFG, LE_READ_4(&mask)); 602 } else 603 OS_REG_WRITE(ah, AR_CFG, INIT_CONFIG_STATUS); 604 } 605 return rt; 606 } 607 608 609 /* 610 * Returns: the pcdac value 611 */ 612 static uint8_t 613 getPcdac(struct ath_hal *ah, const struct tpcMap *pRD, uint8_t dBm) 614 { 615 int32_t i; 616 int useNextEntry = AH_FALSE; 617 uint32_t interp; 618 619 for (i = AR_TP_SCALING_ENTRIES - 1; i >= 0; i--) { 620 /* Check for exact entry */ 621 if (dBm == AR_I2DBM(i)) { 622 if (pRD->pcdac[i] != 63) 623 return pRD->pcdac[i]; 624 useNextEntry = AH_TRUE; 625 } else if (dBm + 1 == AR_I2DBM(i) && i > 0) { 626 /* Interpolate for between entry with a logish scale */ 627 if (pRD->pcdac[i] != 63 && pRD->pcdac[i-1] != 63) { 628 interp = (350 * (pRD->pcdac[i] - pRD->pcdac[i-1])) + 999; 629 interp = (interp / 1000) + pRD->pcdac[i-1]; 630 return interp; 631 } 632 useNextEntry = AH_TRUE; 633 } else if (useNextEntry == AH_TRUE) { 634 /* Grab the next lowest */ 635 if (pRD->pcdac[i] != 63) 636 return pRD->pcdac[i]; 637 } 638 } 639 640 /* Return the lowest Entry if we haven't returned */ 641 for (i = 0; i < AR_TP_SCALING_ENTRIES; i++) 642 if (pRD->pcdac[i] != 63) 643 return pRD->pcdac[i]; 644 645 /* No value to return from table */ 646 #ifdef AH_DEBUG 647 ath_hal_printf(ah, "%s: empty transmit power table?\n", __func__); 648 #endif 649 return 1; 650 } 651 652 /* 653 * Find or interpolates the gainF value from the table ptr. 654 */ 655 static uint8_t 656 getGainF(struct ath_hal *ah, const struct tpcMap *pRD, 657 uint8_t pcdac, uint8_t *dBm) 658 { 659 uint32_t interp; 660 int low, high, i; 661 662 low = high = -1; 663 664 for (i = 0; i < AR_TP_SCALING_ENTRIES; i++) { 665 if(pRD->pcdac[i] == 63) 666 continue; 667 if (pcdac == pRD->pcdac[i]) { 668 *dBm = AR_I2DBM(i); 669 return pRD->gainF[i]; /* Exact Match */ 670 } 671 if (pcdac > pRD->pcdac[i]) 672 low = i; 673 if (pcdac < pRD->pcdac[i]) { 674 high = i; 675 if (low == -1) { 676 *dBm = AR_I2DBM(i); 677 /* PCDAC is lower than lowest setting */ 678 return pRD->gainF[i]; 679 } 680 break; 681 } 682 } 683 if (i >= AR_TP_SCALING_ENTRIES && low == -1) { 684 /* No settings were found */ 685 #ifdef AH_DEBUG 686 ath_hal_printf(ah, 687 "%s: no valid entries in the pcdac table: %d\n", 688 __func__, pcdac); 689 #endif 690 return 63; 691 } 692 if (i >= AR_TP_SCALING_ENTRIES) { 693 /* PCDAC setting was above the max setting in the table */ 694 *dBm = AR_I2DBM(low); 695 return pRD->gainF[low]; 696 } 697 /* Only exact if table has no missing entries */ 698 *dBm = (low + high) + 3; 699 700 /* 701 * Perform interpolation between low and high values to find gainF 702 * linearly scale the pcdac between low and high 703 */ 704 interp = ((pcdac - pRD->pcdac[low]) * 1000) / 705 (pRD->pcdac[high] - pRD->pcdac[low]); 706 /* 707 * Multiply the scale ratio by the gainF difference 708 * (plus a rnd up factor) 709 */ 710 interp = ((interp * (pRD->gainF[high] - pRD->gainF[low])) + 999) / 1000; 711 712 /* Add ratioed gain_f to low gain_f value */ 713 return interp + pRD->gainF[low]; 714 } 715 716 HAL_BOOL 717 ar5210SetTxPowerLimit(struct ath_hal *ah, uint32_t limit) 718 { 719 AH_PRIVATE(ah)->ah_powerLimit = AH_MIN(limit, AR5210_MAX_RATE_POWER); 720 /* XXX flush to h/w */ 721 return AH_TRUE; 722 } 723 724 /* 725 * Get TXPower values and set them in the radio 726 */ 727 static HAL_BOOL 728 setupPowerSettings(struct ath_hal *ah, const struct ieee80211_channel *chan, 729 uint8_t cp[17]) 730 { 731 uint16_t freq = ath_hal_gethwchannel(ah, chan); 732 const HAL_EEPROM_v1 *ee = AH_PRIVATE(ah)->ah_eeprom; 733 uint8_t gainFRD, gainF36, gainF48, gainF54; 734 uint8_t dBmRD, dBm36, dBm48, dBm54, dontcare; 735 uint32_t rd, group; 736 const struct tpcMap *pRD; 737 738 /* Set OB/DB Values regardless of channel */ 739 cp[15] = (ee->ee_biasCurrents >> 4) & 0x7; 740 cp[16] = ee->ee_biasCurrents & 0x7; 741 742 if (freq < 5170 || freq > 5320) { 743 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel %u\n", 744 __func__, freq); 745 return AH_FALSE; 746 } 747 748 HALASSERT(ee->ee_version >= AR_EEPROM_VER1 && 749 ee->ee_version < AR_EEPROM_VER3); 750 751 /* Match regulatory domain */ 752 for (rd = 0; rd < AR_REG_DOMAINS_MAX; rd++) 753 if (AH_PRIVATE(ah)->ah_currentRD == ee->ee_regDomain[rd]) 754 break; 755 if (rd == AR_REG_DOMAINS_MAX) { 756 #ifdef AH_DEBUG 757 ath_hal_printf(ah, 758 "%s: no calibrated regulatory domain matches the " 759 "current regularly domain (0x%0x)\n", __func__, 760 AH_PRIVATE(ah)->ah_currentRD); 761 #endif 762 return AH_FALSE; 763 } 764 group = ((freq - 5170) / 10); 765 766 if (group > 11) { 767 /* Pull 5.29 into the 5.27 group */ 768 group--; 769 } 770 771 /* Integer divide will set group from 0 to 4 */ 772 group = group / 3; 773 pRD = &ee->ee_tpc[group]; 774 775 /* Set PC DAC Values */ 776 cp[14] = pRD->regdmn[rd]; 777 cp[9] = AH_MIN(pRD->regdmn[rd], pRD->rate36); 778 cp[8] = AH_MIN(pRD->regdmn[rd], pRD->rate48); 779 cp[7] = AH_MIN(pRD->regdmn[rd], pRD->rate54); 780 781 /* Find Corresponding gainF values for RD, 36, 48, 54 */ 782 gainFRD = getGainF(ah, pRD, pRD->regdmn[rd], &dBmRD); 783 gainF36 = getGainF(ah, pRD, cp[9], &dBm36); 784 gainF48 = getGainF(ah, pRD, cp[8], &dBm48); 785 gainF54 = getGainF(ah, pRD, cp[7], &dBm54); 786 787 /* Power Scale if requested */ 788 if (AH_PRIVATE(ah)->ah_tpScale != HAL_TP_SCALE_MAX) { 789 static const uint16_t tpcScaleReductionTable[5] = 790 { 0, 3, 6, 9, AR5210_MAX_RATE_POWER }; 791 uint16_t tpScale; 792 793 tpScale = tpcScaleReductionTable[AH_PRIVATE(ah)->ah_tpScale]; 794 if (dBmRD < tpScale+3) 795 dBmRD = 3; /* min */ 796 else 797 dBmRD -= tpScale; 798 cp[14] = getPcdac(ah, pRD, dBmRD); 799 gainFRD = getGainF(ah, pRD, cp[14], &dontcare); 800 dBm36 = AH_MIN(dBm36, dBmRD); 801 cp[9] = getPcdac(ah, pRD, dBm36); 802 gainF36 = getGainF(ah, pRD, cp[9], &dontcare); 803 dBm48 = AH_MIN(dBm48, dBmRD); 804 cp[8] = getPcdac(ah, pRD, dBm48); 805 gainF48 = getGainF(ah, pRD, cp[8], &dontcare); 806 dBm54 = AH_MIN(dBm54, dBmRD); 807 cp[7] = getPcdac(ah, pRD, dBm54); 808 gainF54 = getGainF(ah, pRD, cp[7], &dontcare); 809 } 810 /* Record current dBm at rate 6 */ 811 AH_PRIVATE(ah)->ah_maxPowerLevel = 2*dBmRD; 812 813 cp[13] = cp[12] = cp[11] = cp[10] = cp[14]; 814 815 /* Set GainF Values */ 816 cp[0] = gainFRD - gainF54; 817 cp[1] = gainFRD - gainF48; 818 cp[2] = gainFRD - gainF36; 819 /* 9, 12, 18, 24 have no gain_delta from 6 */ 820 cp[3] = cp[4] = cp[5] = cp[6] = 0; 821 return AH_TRUE; 822 } 823 824 /* 825 * Places the device in and out of reset and then places sane 826 * values in the registers based on EEPROM config, initialization 827 * vectors (as determined by the mode), and station configuration 828 */ 829 HAL_BOOL 830 ar5210SetTransmitPower(struct ath_hal *ah, const struct ieee80211_channel *chan) 831 { 832 #define N(a) (sizeof (a) / sizeof (a[0])) 833 static const uint32_t pwr_regs_start[17] = { 834 0x00000000, 0x00000000, 0x00000000, 835 0x00000000, 0x00000000, 0xf0000000, 836 0xcc000000, 0x00000000, 0x00000000, 837 0x00000000, 0x0a000000, 0x000000e2, 838 0x0a000020, 0x01000002, 0x01000018, 839 0x40000000, 0x00000418 840 }; 841 uint16_t i; 842 uint8_t cp[sizeof(ar5k0007_pwrSettings)]; 843 uint32_t pwr_regs[17]; 844 845 OS_MEMCPY(pwr_regs, pwr_regs_start, sizeof(pwr_regs)); 846 OS_MEMCPY(cp, ar5k0007_pwrSettings, sizeof(cp)); 847 848 /* Check the EEPROM tx power calibration settings */ 849 if (!setupPowerSettings(ah, chan, cp)) { 850 #ifdef AH_DEBUG 851 ath_hal_printf(ah, "%s: unable to setup power settings\n", 852 __func__); 853 #endif 854 return AH_FALSE; 855 } 856 if (cp[15] < 1 || cp[15] > 5) { 857 #ifdef AH_DEBUG 858 ath_hal_printf(ah, "%s: OB out of range (%u)\n", 859 __func__, cp[15]); 860 #endif 861 return AH_FALSE; 862 } 863 if (cp[16] < 1 || cp[16] > 5) { 864 #ifdef AH_DEBUG 865 ath_hal_printf(ah, "%s: DB out of range (%u)\n", 866 __func__, cp[16]); 867 #endif 868 return AH_FALSE; 869 } 870 871 /* reverse bits of the transmit power array */ 872 for (i = 0; i < 7; i++) 873 cp[i] = ath_hal_reverseBits(cp[i], 5); 874 for (i = 7; i < 15; i++) 875 cp[i] = ath_hal_reverseBits(cp[i], 6); 876 877 /* merge transmit power values into the register - quite gross */ 878 pwr_regs[0] |= ((cp[1] << 5) & 0xE0) | (cp[0] & 0x1F); 879 pwr_regs[1] |= ((cp[3] << 7) & 0x80) | ((cp[2] << 2) & 0x7C) | 880 ((cp[1] >> 3) & 0x03); 881 pwr_regs[2] |= ((cp[4] << 4) & 0xF0) | ((cp[3] >> 1) & 0x0F); 882 pwr_regs[3] |= ((cp[6] << 6) & 0xC0) | ((cp[5] << 1) & 0x3E) | 883 ((cp[4] >> 4) & 0x01); 884 pwr_regs[4] |= ((cp[7] << 3) & 0xF8) | ((cp[6] >> 2) & 0x07); 885 pwr_regs[5] |= ((cp[9] << 7) & 0x80) | ((cp[8] << 1) & 0x7E) | 886 ((cp[7] >> 5) & 0x01); 887 pwr_regs[6] |= ((cp[10] << 5) & 0xE0) | ((cp[9] >> 1) & 0x1F); 888 pwr_regs[7] |= ((cp[11] << 3) & 0xF8) | ((cp[10] >> 3) & 0x07); 889 pwr_regs[8] |= ((cp[12] << 1) & 0x7E) | ((cp[11] >> 5) & 0x01); 890 pwr_regs[9] |= ((cp[13] << 5) & 0xE0); 891 pwr_regs[10] |= ((cp[14] << 3) & 0xF8) | ((cp[13] >> 3) & 0x07); 892 pwr_regs[11] |= ((cp[14] >> 5) & 0x01); 893 894 /* Set OB */ 895 pwr_regs[8] |= (ath_hal_reverseBits(cp[15], 3) << 7) & 0x80; 896 pwr_regs[9] |= (ath_hal_reverseBits(cp[15], 3) >> 1) & 0x03; 897 898 /* Set DB */ 899 pwr_regs[9] |= (ath_hal_reverseBits(cp[16], 3) << 2) & 0x1C; 900 901 /* Write the registers */ 902 for (i = 0; i < N(pwr_regs)-1; i++) 903 OS_REG_WRITE(ah, 0x0000989c, pwr_regs[i]); 904 /* last write is a flush */ 905 OS_REG_WRITE(ah, 0x000098d4, pwr_regs[i]); 906 907 return AH_TRUE; 908 #undef N 909 } 910 911 /* 912 * Takes the MHz channel value and sets the Channel value 913 * 914 * ASSUMES: Writes enabled to analog bus before AGC is active 915 * or by disabling the AGC. 916 */ 917 static HAL_BOOL 918 ar5210SetChannel(struct ath_hal *ah, struct ieee80211_channel *chan) 919 { 920 uint16_t freq = ath_hal_gethwchannel(ah, chan); 921 uint32_t data; 922 923 /* Set the Channel */ 924 data = ath_hal_reverseBits((freq - 5120)/10, 5); 925 data = (data << 1) | 0x41; 926 OS_REG_WRITE(ah, AR_PHY(0x27), data); 927 OS_REG_WRITE(ah, AR_PHY(0x30), 0); 928 AH_PRIVATE(ah)->ah_curchan = chan; 929 return AH_TRUE; 930 } 931 932 int16_t 933 ar5210GetNoiseFloor(struct ath_hal *ah) 934 { 935 int16_t nf; 936 937 nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff; 938 if (nf & 0x100) 939 nf = 0 - ((nf ^ 0x1ff) + 1); 940 return nf; 941 } 942 943 #define NORMAL_NF_THRESH (-72) 944 /* 945 * Peform the noisefloor calibration and check for 946 * any constant channel interference 947 * 948 * Returns: TRUE for a successful noise floor calibration; else FALSE 949 */ 950 HAL_BOOL 951 ar5210CalNoiseFloor(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *ichan) 952 { 953 int32_t nf, nfLoops; 954 955 /* Calibrate the noise floor */ 956 OS_REG_WRITE(ah, AR_PHY_AGCCTL, 957 OS_REG_READ(ah, AR_PHY_AGCCTL) | AR_PHY_AGC_NF); 958 959 /* Do not read noise floor until it has done the first update */ 960 if (!ath_hal_wait(ah, AR_PHY_AGCCTL, AR_PHY_AGC_NF, 0)) { 961 #ifdef ATH_HAL_DEBUG 962 ath_hal_printf(ah, " -PHY NF Reg state: 0x%x\n", 963 OS_REG_READ(ah, AR_PHY_AGCCTL)); 964 ath_hal_printf(ah, " -MAC Reset Reg state: 0x%x\n", 965 OS_REG_READ(ah, AR_RC)); 966 ath_hal_printf(ah, " -PHY Active Reg state: 0x%x\n", 967 OS_REG_READ(ah, AR_PHY_ACTIVE)); 968 #endif /* ATH_HAL_DEBUG */ 969 return AH_FALSE; 970 } 971 972 nf = 0; 973 /* Keep checking until the floor is below the threshold or the nf is done */ 974 for (nfLoops = 0; ((nfLoops < 21) && (nf > NORMAL_NF_THRESH)); nfLoops++) { 975 OS_DELAY(1000); /* Sleep for 1 ms */ 976 nf = ar5210GetNoiseFloor(ah); 977 } 978 979 if (nf > NORMAL_NF_THRESH) { 980 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: Bad noise cal %d\n", 981 __func__, nf); 982 ichan->rawNoiseFloor = 0; 983 return AH_FALSE; 984 } 985 ichan->rawNoiseFloor = nf; 986 return AH_TRUE; 987 } 988 989 /* 990 * Adjust NF based on statistical values for 5GHz frequencies. 991 */ 992 int16_t 993 ar5210GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c) 994 { 995 return 0; 996 } 997 998 HAL_RFGAIN 999 ar5210GetRfgain(struct ath_hal *ah) 1000 { 1001 return HAL_RFGAIN_INACTIVE; 1002 } 1003