1 /*- 2 * SPDX-License-Identifier: ISC 3 * 4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 5 * Copyright (c) 2002-2004 Atheros Communications, Inc. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 * 19 * $FreeBSD$ 20 */ 21 #include "opt_ah.h" 22 23 #include "ah.h" 24 #include "ah_internal.h" 25 #include "ah_desc.h" 26 27 #include "ar5210/ar5210.h" 28 #include "ar5210/ar5210reg.h" 29 #include "ar5210/ar5210desc.h" 30 31 /* 32 * Get the RXDP. 33 */ 34 uint32_t 35 ar5210GetRxDP(struct ath_hal *ah, HAL_RX_QUEUE qtype) 36 { 37 38 HALASSERT(qtype == HAL_RX_QUEUE_HP); 39 return OS_REG_READ(ah, AR_RXDP); 40 } 41 42 /* 43 * Set the RxDP. 44 */ 45 void 46 ar5210SetRxDP(struct ath_hal *ah, uint32_t rxdp, HAL_RX_QUEUE qtype) 47 { 48 49 HALASSERT(qtype == HAL_RX_QUEUE_HP); 50 OS_REG_WRITE(ah, AR_RXDP, rxdp); 51 } 52 53 /* 54 * Set Receive Enable bits. 55 */ 56 void 57 ar5210EnableReceive(struct ath_hal *ah) 58 { 59 OS_REG_WRITE(ah, AR_CR, AR_CR_RXE); 60 } 61 62 /* 63 * Stop Receive at the DMA engine 64 */ 65 HAL_BOOL 66 ar5210StopDmaReceive(struct ath_hal *ah) 67 { 68 int i; 69 70 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */ 71 for (i = 0; i < 1000; i++) { 72 if ((OS_REG_READ(ah, AR_CR) & AR_CR_RXE) == 0) 73 return AH_TRUE; 74 OS_DELAY(10); 75 } 76 #ifdef AH_DEBUG 77 ath_hal_printf(ah, "ar5210: dma receive failed to stop in 10ms\n"); 78 ath_hal_printf(ah, "AR_CR=0x%x\n", OS_REG_READ(ah, AR_CR)); 79 ath_hal_printf(ah, "AR_DIAG_SW=0x%x\n", OS_REG_READ(ah, AR_DIAG_SW)); 80 #endif 81 return AH_FALSE; 82 } 83 84 /* 85 * Start Transmit at the PCU engine (unpause receive) 86 */ 87 void 88 ar5210StartPcuReceive(struct ath_hal *ah, HAL_BOOL is_scanning) 89 { 90 ar5210UpdateDiagReg(ah, 91 OS_REG_READ(ah, AR_DIAG_SW) & ~(AR_DIAG_SW_DIS_RX)); 92 } 93 94 /* 95 * Stop Transmit at the PCU engine (pause receive) 96 */ 97 void 98 ar5210StopPcuReceive(struct ath_hal *ah) 99 { 100 ar5210UpdateDiagReg(ah, 101 OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_SW_DIS_RX); 102 } 103 104 /* 105 * Set multicast filter 0 (lower 32-bits) 106 * filter 1 (upper 32-bits) 107 */ 108 void 109 ar5210SetMulticastFilter(struct ath_hal *ah, uint32_t filter0, uint32_t filter1) 110 { 111 OS_REG_WRITE(ah, AR_MCAST_FIL0, filter0); 112 OS_REG_WRITE(ah, AR_MCAST_FIL1, filter1); 113 } 114 115 /* 116 * Clear multicast filter by index 117 */ 118 HAL_BOOL 119 ar5210ClrMulticastFilterIndex(struct ath_hal *ah, uint32_t ix) 120 { 121 uint32_t val; 122 123 if (ix >= 64) 124 return AH_FALSE; 125 if (ix >= 32) { 126 val = OS_REG_READ(ah, AR_MCAST_FIL1); 127 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val &~ (1<<(ix-32)))); 128 } else { 129 val = OS_REG_READ(ah, AR_MCAST_FIL0); 130 OS_REG_WRITE(ah, AR_MCAST_FIL0, (val &~ (1<<ix))); 131 } 132 return AH_TRUE; 133 } 134 135 /* 136 * Set multicast filter by index 137 */ 138 HAL_BOOL 139 ar5210SetMulticastFilterIndex(struct ath_hal *ah, uint32_t ix) 140 { 141 uint32_t val; 142 143 if (ix >= 64) 144 return AH_FALSE; 145 if (ix >= 32) { 146 val = OS_REG_READ(ah, AR_MCAST_FIL1); 147 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val | (1<<(ix-32)))); 148 } else { 149 val = OS_REG_READ(ah, AR_MCAST_FIL0); 150 OS_REG_WRITE(ah, AR_MCAST_FIL0, (val | (1<<ix))); 151 } 152 return AH_TRUE; 153 } 154 155 /* 156 * Return the receive packet filter. 157 */ 158 uint32_t 159 ar5210GetRxFilter(struct ath_hal *ah) 160 { 161 /* XXX can't be sure if promiscuous mode is set because of PHYRADAR */ 162 return OS_REG_READ(ah, AR_RX_FILTER); 163 } 164 165 /* 166 * Turn off/on bits in the receive packet filter. 167 */ 168 void 169 ar5210SetRxFilter(struct ath_hal *ah, uint32_t bits) 170 { 171 if (bits & HAL_RX_FILTER_PHYRADAR) { 172 /* must enable promiscuous mode to get radar */ 173 bits = (bits &~ HAL_RX_FILTER_PHYRADAR) | AR_RX_FILTER_PROMISCUOUS; 174 } 175 OS_REG_WRITE(ah, AR_RX_FILTER, bits); 176 } 177 178 /* 179 * Initialize RX descriptor, by clearing the status and clearing 180 * the size. This is not strictly HW dependent, but we want the 181 * control and status words to be opaque above the hal. 182 */ 183 HAL_BOOL 184 ar5210SetupRxDesc(struct ath_hal *ah, struct ath_desc *ds, 185 uint32_t size, u_int flags) 186 { 187 struct ar5210_desc *ads = AR5210DESC(ds); 188 189 (void) flags; 190 191 ads->ds_ctl0 = 0; 192 ads->ds_ctl1 = size & AR_BufLen; 193 if (ads->ds_ctl1 != size) { 194 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: buffer size %u too large\n", 195 __func__, size); 196 return AH_FALSE; 197 } 198 if (flags & HAL_RXDESC_INTREQ) 199 ads->ds_ctl1 |= AR_RxInterReq; 200 ads->ds_status0 = ads->ds_status1 = 0; 201 202 return AH_TRUE; 203 } 204 205 /* 206 * Process an RX descriptor, and return the status to the caller. 207 * Copy some hardware specific items into the software portion 208 * of the descriptor. 209 * 210 * NB: the caller is responsible for validating the memory contents 211 * of the descriptor (e.g. flushing any cached copy). 212 */ 213 HAL_STATUS 214 ar5210ProcRxDesc(struct ath_hal *ah, struct ath_desc *ds, 215 uint32_t pa, struct ath_desc *nds, uint64_t tsf, 216 struct ath_rx_status *rs) 217 { 218 struct ar5210_desc *ads = AR5210DESC(ds); 219 struct ar5210_desc *ands = AR5210DESC(nds); 220 uint32_t now, rstamp; 221 222 if ((ads->ds_status1 & AR_Done) == 0) 223 return HAL_EINPROGRESS; 224 /* 225 * Given the use of a self-linked tail be very sure that the hw is 226 * done with this descriptor; the hw may have done this descriptor 227 * once and picked it up again...make sure the hw has moved on. 228 */ 229 if ((ands->ds_status1 & AR_Done) == 0 && OS_REG_READ(ah, AR_RXDP) == pa) 230 return HAL_EINPROGRESS; 231 232 rs->rs_datalen = ads->ds_status0 & AR_DataLen; 233 rstamp = MS(ads->ds_status1, AR_RcvTimestamp); 234 /* 235 * Convert timestamp. The value in the 236 * descriptor is bits [10..22] of the TSF. 237 */ 238 now = (OS_REG_READ(ah, AR_TSF_L32) >> 10) & 0xffff; 239 if ((now & 0x1fff) < rstamp) 240 rstamp |= (now - 0x2000) & 0xffff; 241 else 242 rstamp |= now; 243 /* NB: keep only 15 bits for consistency w/ other chips */ 244 rs->rs_tstamp = rstamp & 0x7fff; 245 rs->rs_status = 0; 246 if ((ads->ds_status1 & AR_FrmRcvOK) == 0) { 247 if (ads->ds_status1 & AR_CRCErr) 248 rs->rs_status |= HAL_RXERR_CRC; 249 else if (ads->ds_status1 & AR_DecryptCRCErr) 250 rs->rs_status |= HAL_RXERR_DECRYPT; 251 else if (ads->ds_status1 & AR_FIFOOverrun) 252 rs->rs_status |= HAL_RXERR_FIFO; 253 else { 254 rs->rs_status |= HAL_RXERR_PHY; 255 rs->rs_phyerr = 256 (ads->ds_status1 & AR_PHYErr) >> AR_PHYErr_S; 257 } 258 } 259 /* XXX what about KeyCacheMiss? */ 260 rs->rs_rssi = MS(ads->ds_status0, AR_RcvSigStrength); 261 if (ads->ds_status1 & AR_KeyIdxValid) 262 rs->rs_keyix = MS(ads->ds_status1, AR_KeyIdx); 263 else 264 rs->rs_keyix = HAL_RXKEYIX_INVALID; 265 /* NB: caller expected to do rate table mapping */ 266 rs->rs_rate = MS(ads->ds_status0, AR_RcvRate); 267 rs->rs_antenna = (ads->ds_status0 & AR_RcvAntenna) ? 1 : 0; 268 rs->rs_more = (ads->ds_status0 & AR_More) ? 1 : 0; 269 270 return HAL_OK; 271 } 272