1 /*- 2 * SPDX-License-Identifier: ISC 3 * 4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 5 * Copyright (c) 2002-2004 Atheros Communications, Inc. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 * 19 * $FreeBSD$ 20 */ 21 #include "opt_ah.h" 22 23 #include "ah.h" 24 #include "ah_internal.h" 25 #include "ah_desc.h" 26 27 #include "ar5210/ar5210.h" 28 #include "ar5210/ar5210reg.h" 29 #include "ar5210/ar5210desc.h" 30 31 /* 32 * Get the RXDP. 33 */ 34 uint32_t 35 ar5210GetRxDP(struct ath_hal *ah, HAL_RX_QUEUE qtype) 36 { 37 38 HALASSERT(qtype == HAL_RX_QUEUE_HP); 39 return OS_REG_READ(ah, AR_RXDP); 40 } 41 42 /* 43 * Set the RxDP. 44 */ 45 void 46 ar5210SetRxDP(struct ath_hal *ah, uint32_t rxdp, HAL_RX_QUEUE qtype) 47 { 48 49 HALASSERT(qtype == HAL_RX_QUEUE_HP); 50 OS_REG_WRITE(ah, AR_RXDP, rxdp); 51 } 52 53 54 /* 55 * Set Receive Enable bits. 56 */ 57 void 58 ar5210EnableReceive(struct ath_hal *ah) 59 { 60 OS_REG_WRITE(ah, AR_CR, AR_CR_RXE); 61 } 62 63 /* 64 * Stop Receive at the DMA engine 65 */ 66 HAL_BOOL 67 ar5210StopDmaReceive(struct ath_hal *ah) 68 { 69 int i; 70 71 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */ 72 for (i = 0; i < 1000; i++) { 73 if ((OS_REG_READ(ah, AR_CR) & AR_CR_RXE) == 0) 74 return AH_TRUE; 75 OS_DELAY(10); 76 } 77 #ifdef AH_DEBUG 78 ath_hal_printf(ah, "ar5210: dma receive failed to stop in 10ms\n"); 79 ath_hal_printf(ah, "AR_CR=0x%x\n", OS_REG_READ(ah, AR_CR)); 80 ath_hal_printf(ah, "AR_DIAG_SW=0x%x\n", OS_REG_READ(ah, AR_DIAG_SW)); 81 #endif 82 return AH_FALSE; 83 } 84 85 /* 86 * Start Transmit at the PCU engine (unpause receive) 87 */ 88 void 89 ar5210StartPcuReceive(struct ath_hal *ah, HAL_BOOL is_scanning) 90 { 91 ar5210UpdateDiagReg(ah, 92 OS_REG_READ(ah, AR_DIAG_SW) & ~(AR_DIAG_SW_DIS_RX)); 93 } 94 95 /* 96 * Stop Transmit at the PCU engine (pause receive) 97 */ 98 void 99 ar5210StopPcuReceive(struct ath_hal *ah) 100 { 101 ar5210UpdateDiagReg(ah, 102 OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_SW_DIS_RX); 103 } 104 105 /* 106 * Set multicast filter 0 (lower 32-bits) 107 * filter 1 (upper 32-bits) 108 */ 109 void 110 ar5210SetMulticastFilter(struct ath_hal *ah, uint32_t filter0, uint32_t filter1) 111 { 112 OS_REG_WRITE(ah, AR_MCAST_FIL0, filter0); 113 OS_REG_WRITE(ah, AR_MCAST_FIL1, filter1); 114 } 115 116 /* 117 * Clear multicast filter by index 118 */ 119 HAL_BOOL 120 ar5210ClrMulticastFilterIndex(struct ath_hal *ah, uint32_t ix) 121 { 122 uint32_t val; 123 124 if (ix >= 64) 125 return AH_FALSE; 126 if (ix >= 32) { 127 val = OS_REG_READ(ah, AR_MCAST_FIL1); 128 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val &~ (1<<(ix-32)))); 129 } else { 130 val = OS_REG_READ(ah, AR_MCAST_FIL0); 131 OS_REG_WRITE(ah, AR_MCAST_FIL0, (val &~ (1<<ix))); 132 } 133 return AH_TRUE; 134 } 135 136 /* 137 * Set multicast filter by index 138 */ 139 HAL_BOOL 140 ar5210SetMulticastFilterIndex(struct ath_hal *ah, uint32_t ix) 141 { 142 uint32_t val; 143 144 if (ix >= 64) 145 return AH_FALSE; 146 if (ix >= 32) { 147 val = OS_REG_READ(ah, AR_MCAST_FIL1); 148 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val | (1<<(ix-32)))); 149 } else { 150 val = OS_REG_READ(ah, AR_MCAST_FIL0); 151 OS_REG_WRITE(ah, AR_MCAST_FIL0, (val | (1<<ix))); 152 } 153 return AH_TRUE; 154 } 155 156 /* 157 * Return the receive packet filter. 158 */ 159 uint32_t 160 ar5210GetRxFilter(struct ath_hal *ah) 161 { 162 /* XXX can't be sure if promiscuous mode is set because of PHYRADAR */ 163 return OS_REG_READ(ah, AR_RX_FILTER); 164 } 165 166 /* 167 * Turn off/on bits in the receive packet filter. 168 */ 169 void 170 ar5210SetRxFilter(struct ath_hal *ah, uint32_t bits) 171 { 172 if (bits & HAL_RX_FILTER_PHYRADAR) { 173 /* must enable promiscuous mode to get radar */ 174 bits = (bits &~ HAL_RX_FILTER_PHYRADAR) | AR_RX_FILTER_PROMISCUOUS; 175 } 176 OS_REG_WRITE(ah, AR_RX_FILTER, bits); 177 } 178 179 /* 180 * Initialize RX descriptor, by clearing the status and clearing 181 * the size. This is not strictly HW dependent, but we want the 182 * control and status words to be opaque above the hal. 183 */ 184 HAL_BOOL 185 ar5210SetupRxDesc(struct ath_hal *ah, struct ath_desc *ds, 186 uint32_t size, u_int flags) 187 { 188 struct ar5210_desc *ads = AR5210DESC(ds); 189 190 (void) flags; 191 192 ads->ds_ctl0 = 0; 193 ads->ds_ctl1 = size & AR_BufLen; 194 if (ads->ds_ctl1 != size) { 195 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: buffer size %u too large\n", 196 __func__, size); 197 return AH_FALSE; 198 } 199 if (flags & HAL_RXDESC_INTREQ) 200 ads->ds_ctl1 |= AR_RxInterReq; 201 ads->ds_status0 = ads->ds_status1 = 0; 202 203 return AH_TRUE; 204 } 205 206 /* 207 * Process an RX descriptor, and return the status to the caller. 208 * Copy some hardware specific items into the software portion 209 * of the descriptor. 210 * 211 * NB: the caller is responsible for validating the memory contents 212 * of the descriptor (e.g. flushing any cached copy). 213 */ 214 HAL_STATUS 215 ar5210ProcRxDesc(struct ath_hal *ah, struct ath_desc *ds, 216 uint32_t pa, struct ath_desc *nds, uint64_t tsf, 217 struct ath_rx_status *rs) 218 { 219 struct ar5210_desc *ads = AR5210DESC(ds); 220 struct ar5210_desc *ands = AR5210DESC(nds); 221 uint32_t now, rstamp; 222 223 if ((ads->ds_status1 & AR_Done) == 0) 224 return HAL_EINPROGRESS; 225 /* 226 * Given the use of a self-linked tail be very sure that the hw is 227 * done with this descriptor; the hw may have done this descriptor 228 * once and picked it up again...make sure the hw has moved on. 229 */ 230 if ((ands->ds_status1 & AR_Done) == 0 && OS_REG_READ(ah, AR_RXDP) == pa) 231 return HAL_EINPROGRESS; 232 233 rs->rs_datalen = ads->ds_status0 & AR_DataLen; 234 rstamp = MS(ads->ds_status1, AR_RcvTimestamp); 235 /* 236 * Convert timestamp. The value in the 237 * descriptor is bits [10..22] of the TSF. 238 */ 239 now = (OS_REG_READ(ah, AR_TSF_L32) >> 10) & 0xffff; 240 if ((now & 0x1fff) < rstamp) 241 rstamp |= (now - 0x2000) & 0xffff; 242 else 243 rstamp |= now; 244 /* NB: keep only 15 bits for consistency w/ other chips */ 245 rs->rs_tstamp = rstamp & 0x7fff; 246 rs->rs_status = 0; 247 if ((ads->ds_status1 & AR_FrmRcvOK) == 0) { 248 if (ads->ds_status1 & AR_CRCErr) 249 rs->rs_status |= HAL_RXERR_CRC; 250 else if (ads->ds_status1 & AR_DecryptCRCErr) 251 rs->rs_status |= HAL_RXERR_DECRYPT; 252 else if (ads->ds_status1 & AR_FIFOOverrun) 253 rs->rs_status |= HAL_RXERR_FIFO; 254 else { 255 rs->rs_status |= HAL_RXERR_PHY; 256 rs->rs_phyerr = 257 (ads->ds_status1 & AR_PHYErr) >> AR_PHYErr_S; 258 } 259 } 260 /* XXX what about KeyCacheMiss? */ 261 rs->rs_rssi = MS(ads->ds_status0, AR_RcvSigStrength); 262 if (ads->ds_status1 & AR_KeyIdxValid) 263 rs->rs_keyix = MS(ads->ds_status1, AR_KeyIdx); 264 else 265 rs->rs_keyix = HAL_RXKEYIX_INVALID; 266 /* NB: caller expected to do rate table mapping */ 267 rs->rs_rate = MS(ads->ds_status0, AR_RcvRate); 268 rs->rs_antenna = (ads->ds_status0 & AR_RcvAntenna) ? 1 : 0; 269 rs->rs_more = (ads->ds_status0 & AR_More) ? 1 : 0; 270 271 return HAL_OK; 272 } 273