xref: /freebsd/sys/dev/ath/ath_hal/ar5210/ar5210.h (revision 74fe6c29fb7eef3418d7919dcd41dc1a04a982a1)
1 /*-
2  * SPDX-License-Identifier: ISC
3  *
4  * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
5  * Copyright (c) 2002-2004 Atheros Communications, Inc.
6  *
7  * Permission to use, copy, modify, and/or distribute this software for any
8  * purpose with or without fee is hereby granted, provided that the above
9  * copyright notice and this permission notice appear in all copies.
10  *
11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18  *
19  * $FreeBSD$
20  */
21 #ifndef _ATH_AR5210_H_
22 #define _ATH_AR5210_H_
23 
24 #define	AR5210_MAGIC	0x19980124
25 
26 #if 0
27 /*
28  * RTS_ENABLE includes LONG_PKT because they essentially
29  * imply the same thing, and are set or not set together
30  * for this chip
31  */
32 #define AR5210_TXD_CTRL_A_HDR_LEN(_val)         (((_val)      ) & 0x0003f)
33 #define AR5210_TXD_CTRL_A_TX_RATE(_val)         (((_val) <<  6) & 0x003c0)
34 #define AR5210_TXD_CTRL_A_RTS_ENABLE            (                 0x00c00)
35 #define AR5210_TXD_CTRL_A_CLEAR_DEST_MASK(_val) (((_val) << 12) & 0x01000)
36 #define AR5210_TXD_CTRL_A_ANT_MODE(_val)        (((_val) << 13) & 0x02000)
37 #define AR5210_TXD_CTRL_A_PKT_TYPE(_val)        (((_val) << 14) & 0x1c000)
38 #define AR5210_TXD_CTRL_A_INT_REQ               (                 0x20000)
39 #define AR5210_TXD_CTRL_A_KEY_VALID             (                 0x40000)
40 #define AR5210_TXD_CTRL_B_KEY_ID(_val)          (((_val)      ) & 0x0003f)
41 #define AR5210_TXD_CTRL_B_RTS_DURATION(_val)    (((_val) <<  6) & 0x7ffc0)
42 #endif
43 
44 #define INIT_CONFIG_STATUS              0x00000000
45 #define INIT_ACKTOPS                    0x00000008
46 #define INIT_BCON_CNTRL_REG             0x00000000
47 #define INIT_SLOT_TIME                  0x00000168
48 #define INIT_SLOT_TIME_TURBO            0x000001e0 /* More aggressive turbo slot timing = 6 us */
49 #define INIT_ACK_CTS_TIMEOUT            0x04000400
50 #define INIT_ACK_CTS_TIMEOUT_TURBO      0x08000800
51 
52 #define INIT_USEC                       0x27
53 #define INIT_USEC_TURBO                 0x4f
54 #define INIT_USEC_32                    0x1f
55 #define INIT_TX_LATENCY                 0x36
56 #define INIT_RX_LATENCY                 0x1D
57 #define INIT_TRANSMIT_LATENCY \
58 	((INIT_RX_LATENCY << AR_USEC_RX_LATENCY_S) | \
59 	 (INIT_TX_LATENCY << AR_USEC_TX_LATENCY_S) | \
60 	 (INIT_USEC_32 << 7) | INIT_USEC )
61 #define INIT_TRANSMIT_LATENCY_TURBO  \
62 	((INIT_RX_LATENCY << AR_USEC_RX_LATENCY_S) | \
63 	 (INIT_TX_LATENCY << AR_USEC_TX_LATENCY_S) | \
64 	 (INIT_USEC_32 << 7) | INIT_USEC_TURBO)
65 
66 #define INIT_SIFS                       0x230 /* = 16 us - 2 us */
67 #define INIT_SIFS_TURBO                 0x1E0 /* More aggressive turbo SIFS timing - 8 us - 2 us */
68 
69 /*
70  * Various fifo fill before Tx start, in 64-byte units
71  * i.e. put the frame in the air while still DMAing
72  */
73 #define MIN_TX_FIFO_THRESHOLD           0x1
74 #define MAX_TX_FIFO_THRESHOLD           ((IEEE80211_MAX_LEN / 64) + 1)
75 
76 #define INIT_NEXT_CFP_START             0xffffffff
77 
78 #define INIT_BEACON_PERIOD              0xffff
79 #define INIT_BEACON_EN                  0 /* this should be set by AP only when it's ready */
80 #define INIT_BEACON_CONTROL \
81 	((INIT_RESET_TSF << 24) | (INIT_BEACON_EN << 23) | \
82 	 (INIT_TIM_OFFSET<<16)  | INIT_BEACON_PERIOD)
83 
84 #define INIT_RSSI_THR                   0x00000700 /* Missed beacon counter initialized to max value of 7 */
85 #define INIT_ProgIFS                    0x398      /* PIFS - 2us */
86 #define INIT_ProgIFS_TURBO              0x3C0
87 #define INIT_EIFS                       0xd70
88 #define INIT_EIFS_TURBO                 0x1ae0
89 #define INIT_CARR_SENSE_EN              1
90 #define INIT_PROTO_TIME_CNTRL           ( (INIT_CARR_SENSE_EN << 26) | (INIT_EIFS << 12) | \
91                                           (INIT_ProgIFS) )
92 #define INIT_PROTO_TIME_CNTRL_TURBO     ( (INIT_CARR_SENSE_EN << 26) | (INIT_EIFS_TURBO << 12) | \
93                                           (INIT_ProgIFS_TURBO) )
94 
95 #define	AR5210_MAX_RATE_POWER	60
96 
97 #undef HAL_NUM_TX_QUEUES	/* from ah.h */
98 #define	HAL_NUM_TX_QUEUES	3
99 
100 struct ath_hal_5210 {
101 	struct ath_hal_private ah_priv;	/* base definitions */
102 
103 	uint8_t		ah_macaddr[IEEE80211_ADDR_LEN];
104 	/*
105 	 * Runtime state.
106 	 */
107 	uint32_t	ah_maskReg;		/* shadow of IMR+IER regs */
108 	uint32_t	ah_txOkInterruptMask;
109 	uint32_t	ah_txErrInterruptMask;
110 	uint32_t	ah_txDescInterruptMask;
111 	uint32_t	ah_txEolInterruptMask;
112 	uint32_t	ah_txUrnInterruptMask;
113 	uint8_t		ah_bssid[IEEE80211_ADDR_LEN];
114 	HAL_TX_QUEUE_INFO ah_txq[HAL_NUM_TX_QUEUES]; /* beacon+cab+data */
115 	/*
116 	 * Station mode support.
117 	 */
118 	uint32_t	ah_staId1Defaults;	/* STA_ID1 default settings */
119 	uint32_t	ah_rssiThr;		/* RSSI_THR settings */
120 
121 	u_int		ah_sifstime;		/* user-specified sifs time */
122 	u_int		ah_slottime;		/* user-specified slot time */
123 	u_int		ah_acktimeout;		/* user-specified ack timeout */
124 	u_int		ah_ctstimeout;		/* user-specified cts timeout */
125 
126 	uint16_t	ah_associd;		/* association id */
127 };
128 #define	AH5210(ah)	((struct ath_hal_5210 *)(ah))
129 
130 struct ath_hal;
131 
132 extern	void ar5210Detach(struct ath_hal *ah);
133 extern	HAL_BOOL ar5210Reset(struct ath_hal *, HAL_OPMODE,
134 		struct ieee80211_channel *, HAL_BOOL bChannelChange,
135 		HAL_RESET_TYPE, HAL_STATUS *);
136 extern	void ar5210SetPCUConfig(struct ath_hal *);
137 extern	HAL_BOOL ar5210PhyDisable(struct ath_hal *);
138 extern	HAL_BOOL ar5210Disable(struct ath_hal *);
139 extern	HAL_BOOL ar5210ChipReset(struct ath_hal *, struct ieee80211_channel *);
140 extern	HAL_BOOL ar5210PerCalibration(struct ath_hal *, struct ieee80211_channel *, HAL_BOOL *);
141 extern	HAL_BOOL ar5210PerCalibrationN(struct ath_hal *ah, struct ieee80211_channel *chan,
142 		u_int chainMask, HAL_BOOL longCal, HAL_BOOL *isCalDone);
143 extern	HAL_BOOL ar5210ResetCalValid(struct ath_hal *ah, const struct ieee80211_channel *);
144 extern	int16_t ar5210GetNoiseFloor(struct ath_hal *);
145 extern	int16_t ar5210GetNfAdjust(struct ath_hal *,
146 		const HAL_CHANNEL_INTERNAL *);
147 extern	HAL_BOOL ar5210SetTxPowerLimit(struct ath_hal *, uint32_t limit);
148 extern	HAL_BOOL ar5210SetTransmitPower(struct ath_hal *,
149 		const struct ieee80211_channel *);
150 extern	HAL_BOOL ar5210CalNoiseFloor(struct ath_hal *, HAL_CHANNEL_INTERNAL *);
151 extern	HAL_BOOL ar5210ResetDma(struct ath_hal *, HAL_OPMODE);
152 
153 extern  HAL_BOOL ar5210SetTxQueueProps(struct ath_hal *ah, int q,
154 		const HAL_TXQ_INFO *qInfo);
155 extern	HAL_BOOL ar5210GetTxQueueProps(struct ath_hal *ah, int q,
156 		HAL_TXQ_INFO *qInfo);
157 extern	int ar5210SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type,
158 		const HAL_TXQ_INFO *qInfo);
159 extern	HAL_BOOL ar5210ReleaseTxQueue(struct ath_hal *ah, u_int q);
160 extern	HAL_BOOL ar5210ResetTxQueue(struct ath_hal *ah, u_int q);
161 extern	uint32_t ar5210GetTxDP(struct ath_hal *, u_int);
162 extern	HAL_BOOL ar5210SetTxDP(struct ath_hal *, u_int, uint32_t txdp);
163 extern	HAL_BOOL ar5210UpdateTxTrigLevel(struct ath_hal *, HAL_BOOL);
164 extern	uint32_t ar5210NumTxPending(struct ath_hal *, u_int);
165 extern	HAL_BOOL ar5210StartTxDma(struct ath_hal *, u_int);
166 extern	HAL_BOOL ar5210StopTxDma(struct ath_hal *, u_int);
167 extern	HAL_BOOL ar5210SetupTxDesc(struct ath_hal *, struct ath_desc *,
168 		u_int pktLen, u_int hdrLen, HAL_PKT_TYPE type, u_int txPower,
169 		u_int txRate0, u_int txRetries0,
170 		u_int keyIx, u_int antMode, u_int flags,
171 		u_int rtsctsRate, u_int rtsctsDuration,
172                 u_int compicvLen, u_int compivLen, u_int comp);
173 extern	HAL_BOOL ar5210SetupXTxDesc(struct ath_hal *, struct ath_desc *,
174 		u_int txRate1, u_int txRetries1,
175 		u_int txRate2, u_int txRetries2,
176 		u_int txRate3, u_int txRetries3);
177 extern	HAL_BOOL ar5210FillTxDesc(struct ath_hal *, struct ath_desc *,
178 		HAL_DMA_ADDR *bufAddrList, uint32_t *segLenList,
179 		u_int descId, u_int qcuId, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
180 		const struct ath_desc *ds0);
181 extern	HAL_STATUS ar5210ProcTxDesc(struct ath_hal *,
182 		struct ath_desc *, struct ath_tx_status *);
183 extern  void ar5210GetTxIntrQueue(struct ath_hal *ah, uint32_t *);
184 extern  void ar5210IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *);
185 extern	HAL_BOOL ar5210GetTxCompletionRates(struct ath_hal *ah,
186 		const struct ath_desc *, int *rates, int *tries);
187 extern	void ar5210SetTxDescLink(struct ath_hal *ah, void *ds,
188 		uint32_t link);
189 extern	void ar5210GetTxDescLink(struct ath_hal *ah, void *ds,
190 		uint32_t *link);
191 extern	void ar5210GetTxDescLinkPtr(struct ath_hal *ah, void *ds,
192 		uint32_t **linkptr);
193 
194 extern	uint32_t ar5210GetRxDP(struct ath_hal *, HAL_RX_QUEUE);
195 extern	void ar5210SetRxDP(struct ath_hal *, uint32_t rxdp, HAL_RX_QUEUE);
196 extern	void ar5210EnableReceive(struct ath_hal *);
197 extern	HAL_BOOL ar5210StopDmaReceive(struct ath_hal *);
198 extern	void ar5210StartPcuReceive(struct ath_hal *);
199 extern	void ar5210StopPcuReceive(struct ath_hal *);
200 extern	void ar5210SetMulticastFilter(struct ath_hal *,
201 		uint32_t filter0, uint32_t filter1);
202 extern	HAL_BOOL ar5210ClrMulticastFilterIndex(struct ath_hal *, uint32_t);
203 extern	HAL_BOOL ar5210SetMulticastFilterIndex(struct ath_hal *, uint32_t);
204 extern	uint32_t ar5210GetRxFilter(struct ath_hal *);
205 extern	void ar5210SetRxFilter(struct ath_hal *, uint32_t);
206 extern	HAL_BOOL ar5210SetupRxDesc(struct ath_hal *, struct ath_desc *,
207 		uint32_t, u_int flags);
208 extern	HAL_STATUS ar5210ProcRxDesc(struct ath_hal *, struct ath_desc *,
209 		uint32_t, struct ath_desc *, uint64_t,
210 		struct ath_rx_status *);
211 
212 extern	void ar5210GetMacAddress(struct ath_hal *, uint8_t *);
213 extern	HAL_BOOL ar5210SetMacAddress(struct ath_hal *ah, const uint8_t *);
214 extern	void ar5210GetBssIdMask(struct ath_hal *, uint8_t *);
215 extern	HAL_BOOL ar5210SetBssIdMask(struct ath_hal *, const uint8_t *);
216 extern	HAL_BOOL ar5210EepromRead(struct ath_hal *, u_int off, uint16_t *data);
217 extern	HAL_BOOL ar5210EepromWrite(struct ath_hal *, u_int off, uint16_t data);
218 extern	HAL_BOOL ar5210SetRegulatoryDomain(struct ath_hal *,
219 		uint16_t, HAL_STATUS *);
220 extern	u_int ar5210GetWirelessModes(struct ath_hal *ah);
221 extern	void ar5210EnableRfKill(struct ath_hal *);
222 extern	HAL_BOOL ar5210GpioCfgInput(struct ath_hal *, uint32_t gpio);
223 extern	HAL_BOOL ar5210GpioCfgOutput(struct ath_hal *, uint32_t gpio,
224 		HAL_GPIO_MUX_TYPE);
225 extern	uint32_t ar5210GpioGet(struct ath_hal *, uint32_t gpio);
226 extern	HAL_BOOL ar5210GpioSet(struct ath_hal *, uint32_t gpio, uint32_t);
227 extern	void ar5210Gpio0SetIntr(struct ath_hal *, u_int, uint32_t ilevel);
228 extern	void ar5210SetLedState(struct ath_hal *, HAL_LED_STATE);
229 extern	u_int ar5210GetDefAntenna(struct ath_hal *);
230 extern	void ar5210SetDefAntenna(struct ath_hal *, u_int);
231 extern	HAL_ANT_SETTING ar5210GetAntennaSwitch(struct ath_hal *);
232 extern	HAL_BOOL ar5210SetAntennaSwitch(struct ath_hal *, HAL_ANT_SETTING);
233 extern	void ar5210WriteAssocid(struct ath_hal *,
234 		const uint8_t *bssid, uint16_t assocId);
235 extern	uint32_t ar5210GetTsf32(struct ath_hal *);
236 extern	uint64_t ar5210GetTsf64(struct ath_hal *);
237 extern	void ar5210ResetTsf(struct ath_hal *);
238 extern	uint32_t ar5210GetRandomSeed(struct ath_hal *);
239 extern	HAL_BOOL ar5210DetectCardPresent(struct ath_hal *);
240 extern	void ar5210UpdateMibCounters(struct ath_hal *, HAL_MIB_STATS *);
241 extern	void ar5210EnableHwEncryption(struct ath_hal *);
242 extern	void ar5210DisableHwEncryption(struct ath_hal *);
243 extern	HAL_RFGAIN ar5210GetRfgain(struct ath_hal *);
244 extern	HAL_BOOL ar5210SetSifsTime(struct ath_hal *, u_int);
245 extern	u_int ar5210GetSifsTime(struct ath_hal *);
246 extern	HAL_BOOL ar5210SetSlotTime(struct ath_hal *, u_int);
247 extern	u_int ar5210GetSlotTime(struct ath_hal *);
248 extern	HAL_BOOL ar5210SetAckTimeout(struct ath_hal *, u_int);
249 extern	u_int ar5210GetAckTimeout(struct ath_hal *);
250 extern	HAL_BOOL ar5210SetAckCTSRate(struct ath_hal *, u_int);
251 extern	u_int ar5210GetAckCTSRate(struct ath_hal *);
252 extern	HAL_BOOL ar5210SetCTSTimeout(struct ath_hal *, u_int);
253 extern	u_int ar5210GetCTSTimeout(struct ath_hal *);
254 extern  HAL_BOOL ar5210SetDecompMask(struct ath_hal *, uint16_t, int);
255 void 	ar5210SetCoverageClass(struct ath_hal *, uint8_t, int);
256 extern	HAL_STATUS ar5210SetQuiet(struct ath_hal *, uint32_t, uint32_t,
257 		uint32_t, HAL_QUIET_FLAG);
258 extern	HAL_STATUS ar5210GetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE,
259 		uint32_t, uint32_t *);
260 extern	HAL_BOOL ar5210SetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE,
261 		uint32_t, uint32_t, HAL_STATUS *);
262 extern	HAL_BOOL ar5210GetDiagState(struct ath_hal *ah, int request,
263 		const void *args, uint32_t argsize,
264 		void **result, uint32_t *resultsize);
265 extern	uint32_t ar5210Get11nExtBusy(struct ath_hal *);
266 extern	HAL_BOOL ar5210GetMibCycleCounts(struct ath_hal *,
267 		HAL_SURVEY_SAMPLE *);
268 extern	void ar5210SetChainMasks(struct ath_hal *, uint32_t, uint32_t);
269 extern	void ar5210EnableDfs(struct ath_hal *, HAL_PHYERR_PARAM *);
270 extern	void ar5210GetDfsThresh(struct ath_hal *, HAL_PHYERR_PARAM *);
271 extern	void ar5210UpdateDiagReg(struct ath_hal *ah, uint32_t val);
272 
273 extern	u_int ar5210GetKeyCacheSize(struct ath_hal *);
274 extern	HAL_BOOL ar5210IsKeyCacheEntryValid(struct ath_hal *, uint16_t);
275 extern	HAL_BOOL ar5210ResetKeyCacheEntry(struct ath_hal *, uint16_t entry);
276 extern	HAL_BOOL ar5210SetKeyCacheEntry(struct ath_hal *, uint16_t entry,
277                        const HAL_KEYVAL *, const uint8_t *mac, int xorKey);
278 extern	HAL_BOOL ar5210SetKeyCacheEntryMac(struct ath_hal *,
279 			uint16_t, const uint8_t *);
280 
281 extern	HAL_BOOL ar5210SetPowerMode(struct ath_hal *, uint32_t powerRequest,
282 		int setChip);
283 extern	HAL_POWER_MODE ar5210GetPowerMode(struct ath_hal *);
284 
285 extern	void ar5210SetBeaconTimers(struct ath_hal *,
286 		const HAL_BEACON_TIMERS *);
287 extern	void ar5210BeaconInit(struct ath_hal *, uint32_t, uint32_t);
288 extern	void ar5210SetStaBeaconTimers(struct ath_hal *,
289 		const HAL_BEACON_STATE *);
290 extern	void ar5210ResetStaBeaconTimers(struct ath_hal *);
291 extern	uint64_t ar5210GetNextTBTT(struct ath_hal *);
292 
293 extern	HAL_BOOL ar5210IsInterruptPending(struct ath_hal *);
294 extern	HAL_BOOL ar5210GetPendingInterrupts(struct ath_hal *, HAL_INT *);
295 extern	HAL_INT ar5210GetInterrupts(struct ath_hal *);
296 extern	HAL_INT ar5210SetInterrupts(struct ath_hal *, HAL_INT ints);
297 
298 extern	const HAL_RATE_TABLE *ar5210GetRateTable(struct ath_hal *, u_int mode);
299 
300 extern	HAL_BOOL ar5210AniControl(struct ath_hal *, HAL_ANI_CMD, int );
301 extern	void ar5210AniPoll(struct ath_hal *, const struct ieee80211_channel *);
302 extern	void ar5210RxMonitor(struct ath_hal *, const HAL_NODE_STATS *,
303 		const struct ieee80211_channel *);
304 extern	void ar5210MibEvent(struct ath_hal *, const HAL_NODE_STATS *);
305 #endif /* _ATH_AR5210_H_ */
306