1 /*- 2 * SPDX-License-Identifier: ISC 3 * 4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 5 * Copyright (c) 2005-2006 Atheros Communications, Inc. 6 * All rights reserved. 7 * 8 * Permission to use, copy, modify, and/or distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 #ifndef __AH_REGDOMAIN_H__ 21 #define __AH_REGDOMAIN_H__ 22 23 /* 24 * BMLEN defines the size of the bitmask used to hold frequency 25 * band specifications. Note this must agree with the BM macro 26 * definition that's used to setup initializers. See also further 27 * comments below. 28 */ 29 #define BMLEN 2 /* 2 x 64 bits in each channel bitmask */ 30 typedef uint64_t chanbmask_t[BMLEN]; 31 32 /* 33 * The following describe the bit masks for different passive scan 34 * capability/requirements per regdomain. 35 */ 36 #define NO_PSCAN 0x0ULL /* NB: must be zero */ 37 #define PSCAN_FCC 0x0000000000000001ULL 38 #define PSCAN_FCC_T 0x0000000000000002ULL 39 #define PSCAN_ETSI 0x0000000000000004ULL 40 #define PSCAN_MKK1 0x0000000000000008ULL 41 #define PSCAN_MKK2 0x0000000000000010ULL 42 #define PSCAN_MKKA 0x0000000000000020ULL 43 #define PSCAN_MKKA_G 0x0000000000000040ULL 44 #define PSCAN_ETSIA 0x0000000000000080ULL 45 #define PSCAN_ETSIB 0x0000000000000100ULL 46 #define PSCAN_ETSIC 0x0000000000000200ULL 47 #define PSCAN_WWR 0x0000000000000400ULL 48 #define PSCAN_MKKA1 0x0000000000000800ULL 49 #define PSCAN_MKKA1_G 0x0000000000001000ULL 50 #define PSCAN_MKKA2 0x0000000000002000ULL 51 #define PSCAN_MKKA2_G 0x0000000000004000ULL 52 #define PSCAN_MKK3 0x0000000000008000ULL 53 #define PSCAN_DEFER 0x7FFFFFFFFFFFFFFFULL 54 #define IS_ECM_CHAN 0x8000000000000000ULL 55 56 /* 57 * The following are flags for different requirements per reg domain. 58 * These requirements are either inhereted from the reg domain pair or 59 * from the unitary reg domain if the reg domain pair flags value is 0 60 */ 61 enum { 62 NO_REQ = 0x00000000, /* NB: must be zero */ 63 DISALLOW_ADHOC_11A = 0x00000001, /* adhoc not allowed in 5GHz */ 64 DISALLOW_ADHOC_11A_TURB = 0x00000002, /* not allowed w/ 5GHz turbo */ 65 NEED_NFC = 0x00000004, /* need noise floor check */ 66 ADHOC_PER_11D = 0x00000008, /* must receive 11d beacon */ 67 LIMIT_FRAME_4MS = 0x00000020, /* 4msec tx burst limit */ 68 NO_HOSTAP = 0x00000040, /* No HOSTAP mode opereation */ 69 }; 70 71 /* Bit masks for DFS per regdomain */ 72 enum { 73 NO_DFS = 0x0000000000000000ULL, /* NB: must be zero */ 74 DFS_FCC3 = 0x0000000000000001ULL, 75 DFS_ETSI = 0x0000000000000002ULL, 76 DFS_MKK4 = 0x0000000000000004ULL, 77 }; 78 79 enum { /* conformance test limits */ 80 FCC = 0x10, 81 MKK = 0x40, 82 ETSI = 0x30, 83 }; 84 85 /* 86 * THE following table is the mapping of regdomain pairs specified by 87 * an 8 bit regdomain value to the individual unitary reg domains 88 */ 89 typedef struct regDomainPair { 90 HAL_REG_DOMAIN regDmnEnum; /* 16 bit reg domain pair */ 91 HAL_REG_DOMAIN regDmn5GHz; /* 5GHz reg domain */ 92 HAL_REG_DOMAIN regDmn2GHz; /* 2GHz reg domain */ 93 uint32_t flags5GHz; /* Requirements flags (AdHoc 94 disallow, noise floor cal needed, 95 etc) */ 96 uint32_t flags2GHz; /* Requirements flags (AdHoc 97 disallow, noise floor cal needed, 98 etc) */ 99 uint64_t pscanMask; /* Passive Scan flags which 100 can override unitary domain 101 passive scan flags. This 102 value is used as a mask on 103 the unitary flags*/ 104 uint16_t singleCC; /* Country code of single country if 105 a one-on-one mapping exists */ 106 } REG_DMN_PAIR_MAPPING; 107 108 typedef struct { 109 HAL_CTRY_CODE countryCode; 110 HAL_REG_DOMAIN regDmnEnum; 111 } COUNTRY_CODE_TO_ENUM_RD; 112 113 /* 114 * Frequency band collections are defined using bitmasks. Each bit 115 * in a mask is the index of an entry in one of the following tables. 116 * Bitmasks are BMLEN*64 bits so if a table grows beyond that the bit 117 * vectors must be enlarged or the tables split somehow (e.g. split 118 * 1/2 and 1/4 rate channels into a separate table). 119 * 120 * Beware of ordering; the indices are defined relative to the preceding 121 * entry so if things get off there will be confusion. A good way to 122 * check the indices is to collect them in a switch statement in a stub 123 * function so the compiler checks for duplicates. 124 */ 125 typedef struct { 126 uint16_t lowChannel; /* Low channel center in MHz */ 127 uint16_t highChannel; /* High Channel center in MHz */ 128 uint8_t powerDfs; /* Max power (dBm) for channel 129 range when using DFS */ 130 uint8_t antennaMax; /* Max allowed antenna gain */ 131 uint8_t channelBW; /* Bandwidth of the channel */ 132 uint8_t channelSep; /* Channel separation within 133 the band */ 134 uint64_t useDfs; /* Use DFS in the RegDomain 135 if corresponding bit is set */ 136 uint64_t usePassScan; /* Use Passive Scan in the RegDomain 137 if corresponding bit is set */ 138 } REG_DMN_FREQ_BAND; 139 140 typedef struct regDomain { 141 uint16_t regDmnEnum; /* value from EnumRd table */ 142 uint8_t conformanceTestLimit; 143 uint32_t flags; /* Requirement flags (AdHoc disallow, 144 noise floor cal needed, etc) */ 145 uint64_t dfsMask; /* DFS bitmask for 5Ghz tables */ 146 uint64_t pscan; /* Bitmask for passive scan */ 147 chanbmask_t chan11a; /* 11a channels */ 148 chanbmask_t chan11a_turbo; /* 11a static turbo channels */ 149 chanbmask_t chan11a_dyn_turbo; /* 11a dynamic turbo channels */ 150 chanbmask_t chan11a_half; /* 11a 1/2 width channels */ 151 chanbmask_t chan11a_quarter; /* 11a 1/4 width channels */ 152 chanbmask_t chan11b; /* 11b channels */ 153 chanbmask_t chan11g; /* 11g channels */ 154 chanbmask_t chan11g_turbo; /* 11g dynamic turbo channels */ 155 chanbmask_t chan11g_half; /* 11g 1/2 width channels */ 156 chanbmask_t chan11g_quarter; /* 11g 1/4 width channels */ 157 } REG_DOMAIN; 158 159 struct cmode { 160 u_int mode; 161 u_int flags; 162 REG_DMN_FREQ_BAND *freqs; 163 }; 164 #endif 165