1 /*- 2 * SPDX-License-Identifier: ISC 3 * 4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 5 * Copyright (c) 2005-2006 Atheros Communications, Inc. 6 * All rights reserved. 7 * 8 * Permission to use, copy, modify, and/or distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 * 20 * $FreeBSD$ 21 */ 22 #ifndef __AH_REGDOMAIN_H__ 23 #define __AH_REGDOMAIN_H__ 24 25 /* 26 * BMLEN defines the size of the bitmask used to hold frequency 27 * band specifications. Note this must agree with the BM macro 28 * definition that's used to setup initializers. See also further 29 * comments below. 30 */ 31 #define BMLEN 2 /* 2 x 64 bits in each channel bitmask */ 32 typedef uint64_t chanbmask_t[BMLEN]; 33 34 /* 35 * The following describe the bit masks for different passive scan 36 * capability/requirements per regdomain. 37 */ 38 #define NO_PSCAN 0x0ULL /* NB: must be zero */ 39 #define PSCAN_FCC 0x0000000000000001ULL 40 #define PSCAN_FCC_T 0x0000000000000002ULL 41 #define PSCAN_ETSI 0x0000000000000004ULL 42 #define PSCAN_MKK1 0x0000000000000008ULL 43 #define PSCAN_MKK2 0x0000000000000010ULL 44 #define PSCAN_MKKA 0x0000000000000020ULL 45 #define PSCAN_MKKA_G 0x0000000000000040ULL 46 #define PSCAN_ETSIA 0x0000000000000080ULL 47 #define PSCAN_ETSIB 0x0000000000000100ULL 48 #define PSCAN_ETSIC 0x0000000000000200ULL 49 #define PSCAN_WWR 0x0000000000000400ULL 50 #define PSCAN_MKKA1 0x0000000000000800ULL 51 #define PSCAN_MKKA1_G 0x0000000000001000ULL 52 #define PSCAN_MKKA2 0x0000000000002000ULL 53 #define PSCAN_MKKA2_G 0x0000000000004000ULL 54 #define PSCAN_MKK3 0x0000000000008000ULL 55 #define PSCAN_DEFER 0x7FFFFFFFFFFFFFFFULL 56 #define IS_ECM_CHAN 0x8000000000000000ULL 57 58 /* 59 * The following are flags for different requirements per reg domain. 60 * These requirements are either inhereted from the reg domain pair or 61 * from the unitary reg domain if the reg domain pair flags value is 0 62 */ 63 enum { 64 NO_REQ = 0x00000000, /* NB: must be zero */ 65 DISALLOW_ADHOC_11A = 0x00000001, /* adhoc not allowed in 5GHz */ 66 DISALLOW_ADHOC_11A_TURB = 0x00000002, /* not allowed w/ 5GHz turbo */ 67 NEED_NFC = 0x00000004, /* need noise floor check */ 68 ADHOC_PER_11D = 0x00000008, /* must receive 11d beacon */ 69 LIMIT_FRAME_4MS = 0x00000020, /* 4msec tx burst limit */ 70 NO_HOSTAP = 0x00000040, /* No HOSTAP mode opereation */ 71 }; 72 73 /* Bit masks for DFS per regdomain */ 74 enum { 75 NO_DFS = 0x0000000000000000ULL, /* NB: must be zero */ 76 DFS_FCC3 = 0x0000000000000001ULL, 77 DFS_ETSI = 0x0000000000000002ULL, 78 DFS_MKK4 = 0x0000000000000004ULL, 79 }; 80 81 enum { /* conformance test limits */ 82 FCC = 0x10, 83 MKK = 0x40, 84 ETSI = 0x30, 85 }; 86 87 /* 88 * THE following table is the mapping of regdomain pairs specified by 89 * an 8 bit regdomain value to the individual unitary reg domains 90 */ 91 typedef struct regDomainPair { 92 HAL_REG_DOMAIN regDmnEnum; /* 16 bit reg domain pair */ 93 HAL_REG_DOMAIN regDmn5GHz; /* 5GHz reg domain */ 94 HAL_REG_DOMAIN regDmn2GHz; /* 2GHz reg domain */ 95 uint32_t flags5GHz; /* Requirements flags (AdHoc 96 disallow, noise floor cal needed, 97 etc) */ 98 uint32_t flags2GHz; /* Requirements flags (AdHoc 99 disallow, noise floor cal needed, 100 etc) */ 101 uint64_t pscanMask; /* Passive Scan flags which 102 can override unitary domain 103 passive scan flags. This 104 value is used as a mask on 105 the unitary flags*/ 106 uint16_t singleCC; /* Country code of single country if 107 a one-on-one mapping exists */ 108 } REG_DMN_PAIR_MAPPING; 109 110 typedef struct { 111 HAL_CTRY_CODE countryCode; 112 HAL_REG_DOMAIN regDmnEnum; 113 } COUNTRY_CODE_TO_ENUM_RD; 114 115 /* 116 * Frequency band collections are defined using bitmasks. Each bit 117 * in a mask is the index of an entry in one of the following tables. 118 * Bitmasks are BMLEN*64 bits so if a table grows beyond that the bit 119 * vectors must be enlarged or the tables split somehow (e.g. split 120 * 1/2 and 1/4 rate channels into a separate table). 121 * 122 * Beware of ordering; the indices are defined relative to the preceding 123 * entry so if things get off there will be confusion. A good way to 124 * check the indices is to collect them in a switch statement in a stub 125 * function so the compiler checks for duplicates. 126 */ 127 typedef struct { 128 uint16_t lowChannel; /* Low channel center in MHz */ 129 uint16_t highChannel; /* High Channel center in MHz */ 130 uint8_t powerDfs; /* Max power (dBm) for channel 131 range when using DFS */ 132 uint8_t antennaMax; /* Max allowed antenna gain */ 133 uint8_t channelBW; /* Bandwidth of the channel */ 134 uint8_t channelSep; /* Channel separation within 135 the band */ 136 uint64_t useDfs; /* Use DFS in the RegDomain 137 if corresponding bit is set */ 138 uint64_t usePassScan; /* Use Passive Scan in the RegDomain 139 if corresponding bit is set */ 140 } REG_DMN_FREQ_BAND; 141 142 typedef struct regDomain { 143 uint16_t regDmnEnum; /* value from EnumRd table */ 144 uint8_t conformanceTestLimit; 145 uint32_t flags; /* Requirement flags (AdHoc disallow, 146 noise floor cal needed, etc) */ 147 uint64_t dfsMask; /* DFS bitmask for 5Ghz tables */ 148 uint64_t pscan; /* Bitmask for passive scan */ 149 chanbmask_t chan11a; /* 11a channels */ 150 chanbmask_t chan11a_turbo; /* 11a static turbo channels */ 151 chanbmask_t chan11a_dyn_turbo; /* 11a dynamic turbo channels */ 152 chanbmask_t chan11a_half; /* 11a 1/2 width channels */ 153 chanbmask_t chan11a_quarter; /* 11a 1/4 width channels */ 154 chanbmask_t chan11b; /* 11b channels */ 155 chanbmask_t chan11g; /* 11g channels */ 156 chanbmask_t chan11g_turbo; /* 11g dynamic turbo channels */ 157 chanbmask_t chan11g_half; /* 11g 1/2 width channels */ 158 chanbmask_t chan11g_quarter; /* 11g 1/4 width channels */ 159 } REG_DOMAIN; 160 161 struct cmode { 162 u_int mode; 163 u_int flags; 164 REG_DMN_FREQ_BAND *freqs; 165 }; 166 #endif 167