xref: /freebsd/sys/dev/ath/ath_hal/ah_regdomain.c (revision 1477970585cad11dfbf3ef65e1149f7004b9a005)
114779705SSam Leffler /*
214779705SSam Leffler  * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
314779705SSam Leffler  * Copyright (c) 2005-2006 Atheros Communications, Inc.
414779705SSam Leffler  * All rights reserved.
514779705SSam Leffler  *
614779705SSam Leffler  * Permission to use, copy, modify, and/or distribute this software for any
714779705SSam Leffler  * purpose with or without fee is hereby granted, provided that the above
814779705SSam Leffler  * copyright notice and this permission notice appear in all copies.
914779705SSam Leffler  *
1014779705SSam Leffler  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
1114779705SSam Leffler  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
1214779705SSam Leffler  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
1314779705SSam Leffler  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
1414779705SSam Leffler  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
1514779705SSam Leffler  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
1614779705SSam Leffler  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
1714779705SSam Leffler  *
1814779705SSam Leffler  * $Id: ah_regdomain.c,v 1.24 2008/11/27 22:29:27 sam Exp $
1914779705SSam Leffler  */
2014779705SSam Leffler #include "opt_ah.h"
2114779705SSam Leffler 
2214779705SSam Leffler #include "ah.h"
2314779705SSam Leffler #include "ah_internal.h"
2414779705SSam Leffler #include "ah_eeprom.h"
2514779705SSam Leffler #include "ah_devid.h"
2614779705SSam Leffler 
2714779705SSam Leffler /*
2814779705SSam Leffler  * XXX this code needs a audit+review
2914779705SSam Leffler  */
3014779705SSam Leffler 
3114779705SSam Leffler /* used throughout this file... */
3214779705SSam Leffler #define	N(a)	(sizeof (a) / sizeof (a[0]))
3314779705SSam Leffler 
3414779705SSam Leffler #define HAL_MODE_11A_TURBO	HAL_MODE_108A
3514779705SSam Leffler #define HAL_MODE_11G_TURBO	HAL_MODE_108G
3614779705SSam Leffler 
3714779705SSam Leffler /* 10MHz is half the 11A bandwidth used to determine upper edge freq
3814779705SSam Leffler    of the outdoor channel */
3914779705SSam Leffler #define HALF_MAXCHANBW		10
4014779705SSam Leffler 
4114779705SSam Leffler /*
4214779705SSam Leffler  * BMLEN defines the size of the bitmask used to hold frequency
4314779705SSam Leffler  * band specifications.  Note this must agree with the BM macro
4414779705SSam Leffler  * definition that's used to setup initializers.  See also further
4514779705SSam Leffler  * comments below.
4614779705SSam Leffler  */
4714779705SSam Leffler #define BMLEN 2		/* 2 x 64 bits in each channel bitmask */
4814779705SSam Leffler typedef uint64_t chanbmask_t[BMLEN];
4914779705SSam Leffler 
5014779705SSam Leffler #define	W0(_a) \
5114779705SSam Leffler 	(((_a) >= 0 && (_a) < 64 ? (((uint64_t) 1)<<(_a)) : (uint64_t) 0))
5214779705SSam Leffler #define	W1(_a) \
5314779705SSam Leffler 	(((_a) > 63 && (_a) < 128 ? (((uint64_t) 1)<<((_a)-64)) : (uint64_t) 0))
5414779705SSam Leffler #define BM1(_fa)	{ W0(_fa), W1(_fa) }
5514779705SSam Leffler #define BM2(_fa, _fb)	{ W0(_fa) | W0(_fb), W1(_fa) | W1(_fb) }
5614779705SSam Leffler #define BM3(_fa, _fb, _fc) \
5714779705SSam Leffler 	{ W0(_fa) | W0(_fb) | W0(_fc), W1(_fa) | W1(_fb) | W1(_fc) }
5814779705SSam Leffler #define BM4(_fa, _fb, _fc, _fd)						\
5914779705SSam Leffler 	{ W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd),			\
6014779705SSam Leffler 	  W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) }
6114779705SSam Leffler #define BM5(_fa, _fb, _fc, _fd, _fe)					\
6214779705SSam Leffler 	{ W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe),		\
6314779705SSam Leffler 	  W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) }
6414779705SSam Leffler #define BM6(_fa, _fb, _fc, _fd, _fe, _ff)				\
6514779705SSam Leffler 	{ W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe) | W0(_ff),	\
6614779705SSam Leffler 	  W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) | W1(_ff) }
6714779705SSam Leffler #define BM7(_fa, _fb, _fc, _fd, _fe, _ff, _fg)	\
6814779705SSam Leffler 	{ W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe) | W0(_ff) |	\
6914779705SSam Leffler 	  W0(_fg),\
7014779705SSam Leffler 	  W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) | W1(_ff) |	\
7114779705SSam Leffler 	  W1(_fg) }
7214779705SSam Leffler #define BM8(_fa, _fb, _fc, _fd, _fe, _ff, _fg, _fh)	\
7314779705SSam Leffler 	{ W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe) | W0(_ff) |	\
7414779705SSam Leffler 	  W0(_fg) | W0(_fh) ,	\
7514779705SSam Leffler 	  W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) | W1(_ff) |	\
7614779705SSam Leffler 	  W1(_fg) | W1(_fh) }
7714779705SSam Leffler 
7814779705SSam Leffler /*
7914779705SSam Leffler  * Country/Region Codes
8014779705SSam Leffler  * Numbering from ISO 3166
8114779705SSam Leffler  */
8214779705SSam Leffler enum {
8314779705SSam Leffler     CTRY_ALBANIA              = 8,       /* Albania */
8414779705SSam Leffler     CTRY_ALGERIA              = 12,      /* Algeria */
8514779705SSam Leffler     CTRY_ARGENTINA            = 32,      /* Argentina */
8614779705SSam Leffler     CTRY_ARMENIA              = 51,      /* Armenia */
8714779705SSam Leffler     CTRY_AUSTRALIA            = 36,      /* Australia */
8814779705SSam Leffler     CTRY_AUSTRIA              = 40,      /* Austria */
8914779705SSam Leffler     CTRY_AZERBAIJAN           = 31,      /* Azerbaijan */
9014779705SSam Leffler     CTRY_BAHRAIN              = 48,      /* Bahrain */
9114779705SSam Leffler     CTRY_BELARUS              = 112,     /* Belarus */
9214779705SSam Leffler     CTRY_BELGIUM              = 56,      /* Belgium */
9314779705SSam Leffler     CTRY_BELIZE               = 84,      /* Belize */
9414779705SSam Leffler     CTRY_BOLIVIA              = 68,      /* Bolivia */
9514779705SSam Leffler     CTRY_BRAZIL               = 76,      /* Brazil */
9614779705SSam Leffler     CTRY_BRUNEI_DARUSSALAM    = 96,      /* Brunei Darussalam */
9714779705SSam Leffler     CTRY_BULGARIA             = 100,     /* Bulgaria */
9814779705SSam Leffler     CTRY_CANADA               = 124,     /* Canada */
9914779705SSam Leffler     CTRY_CHILE                = 152,     /* Chile */
10014779705SSam Leffler     CTRY_CHINA                = 156,     /* People's Republic of China */
10114779705SSam Leffler     CTRY_COLOMBIA             = 170,     /* Colombia */
10214779705SSam Leffler     CTRY_COSTA_RICA           = 188,     /* Costa Rica */
10314779705SSam Leffler     CTRY_CROATIA              = 191,     /* Croatia */
10414779705SSam Leffler     CTRY_CYPRUS               = 196,
10514779705SSam Leffler     CTRY_CZECH                = 203,     /* Czech Republic */
10614779705SSam Leffler     CTRY_DENMARK              = 208,     /* Denmark */
10714779705SSam Leffler     CTRY_DOMINICAN_REPUBLIC   = 214,     /* Dominican Republic */
10814779705SSam Leffler     CTRY_ECUADOR              = 218,     /* Ecuador */
10914779705SSam Leffler     CTRY_EGYPT                = 818,     /* Egypt */
11014779705SSam Leffler     CTRY_EL_SALVADOR          = 222,     /* El Salvador */
11114779705SSam Leffler     CTRY_ESTONIA              = 233,     /* Estonia */
11214779705SSam Leffler     CTRY_FAEROE_ISLANDS       = 234,     /* Faeroe Islands */
11314779705SSam Leffler     CTRY_FINLAND              = 246,     /* Finland */
11414779705SSam Leffler     CTRY_FRANCE               = 250,     /* France */
11514779705SSam Leffler     CTRY_FRANCE2              = 255,     /* France2 */
11614779705SSam Leffler     CTRY_GEORGIA              = 268,     /* Georgia */
11714779705SSam Leffler     CTRY_GERMANY              = 276,     /* Germany */
11814779705SSam Leffler     CTRY_GREECE               = 300,     /* Greece */
11914779705SSam Leffler     CTRY_GUATEMALA            = 320,     /* Guatemala */
12014779705SSam Leffler     CTRY_HONDURAS             = 340,     /* Honduras */
12114779705SSam Leffler     CTRY_HONG_KONG            = 344,     /* Hong Kong S.A.R., P.R.C. */
12214779705SSam Leffler     CTRY_HUNGARY              = 348,     /* Hungary */
12314779705SSam Leffler     CTRY_ICELAND              = 352,     /* Iceland */
12414779705SSam Leffler     CTRY_INDIA                = 356,     /* India */
12514779705SSam Leffler     CTRY_INDONESIA            = 360,     /* Indonesia */
12614779705SSam Leffler     CTRY_IRAN                 = 364,     /* Iran */
12714779705SSam Leffler     CTRY_IRAQ                 = 368,     /* Iraq */
12814779705SSam Leffler     CTRY_IRELAND              = 372,     /* Ireland */
12914779705SSam Leffler     CTRY_ISRAEL               = 376,     /* Israel */
13014779705SSam Leffler     CTRY_ITALY                = 380,     /* Italy */
13114779705SSam Leffler     CTRY_JAMAICA              = 388,     /* Jamaica */
13214779705SSam Leffler     CTRY_JAPAN                = 392,     /* Japan */
13314779705SSam Leffler     CTRY_JAPAN1               = 393,     /* Japan (JP1) */
13414779705SSam Leffler     CTRY_JAPAN2               = 394,     /* Japan (JP0) */
13514779705SSam Leffler     CTRY_JAPAN3               = 395,     /* Japan (JP1-1) */
13614779705SSam Leffler     CTRY_JAPAN4               = 396,     /* Japan (JE1) */
13714779705SSam Leffler     CTRY_JAPAN5               = 397,     /* Japan (JE2) */
13814779705SSam Leffler     CTRY_JAPAN6               = 399,     /* Japan (JP6) */
13914779705SSam Leffler 
14014779705SSam Leffler     CTRY_JAPAN7		      = 4007,	 /* Japan (J7) */
14114779705SSam Leffler     CTRY_JAPAN8		      = 4008,	 /* Japan (J8) */
14214779705SSam Leffler     CTRY_JAPAN9		      = 4009,	 /* Japan (J9) */
14314779705SSam Leffler 
14414779705SSam Leffler     CTRY_JAPAN10	      = 4010,	 /* Japan (J10) */
14514779705SSam Leffler     CTRY_JAPAN11	      = 4011,	 /* Japan (J11) */
14614779705SSam Leffler     CTRY_JAPAN12	      = 4012,	 /* Japan (J12) */
14714779705SSam Leffler 
14814779705SSam Leffler     CTRY_JAPAN13	      = 4013,	 /* Japan (J13) */
14914779705SSam Leffler     CTRY_JAPAN14	      = 4014,	 /* Japan (J14) */
15014779705SSam Leffler     CTRY_JAPAN15	      = 4015,	 /* Japan (J15) */
15114779705SSam Leffler 
15214779705SSam Leffler     CTRY_JAPAN16	      = 4016,	 /* Japan (J16) */
15314779705SSam Leffler     CTRY_JAPAN17	      = 4017,	 /* Japan (J17) */
15414779705SSam Leffler     CTRY_JAPAN18	      = 4018,	 /* Japan (J18) */
15514779705SSam Leffler 
15614779705SSam Leffler     CTRY_JAPAN19	      = 4019,	 /* Japan (J19) */
15714779705SSam Leffler     CTRY_JAPAN20	      = 4020,	 /* Japan (J20) */
15814779705SSam Leffler     CTRY_JAPAN21	      = 4021,	 /* Japan (J21) */
15914779705SSam Leffler 
16014779705SSam Leffler     CTRY_JAPAN22	      = 4022,	 /* Japan (J22) */
16114779705SSam Leffler     CTRY_JAPAN23	      = 4023,	 /* Japan (J23) */
16214779705SSam Leffler     CTRY_JAPAN24	      = 4024,	 /* Japan (J24) */
16314779705SSam Leffler 
16414779705SSam Leffler     CTRY_JORDAN               = 400,     /* Jordan */
16514779705SSam Leffler     CTRY_KAZAKHSTAN           = 398,     /* Kazakhstan */
16614779705SSam Leffler     CTRY_KENYA                = 404,     /* Kenya */
16714779705SSam Leffler     CTRY_KOREA_NORTH          = 408,     /* North Korea */
16814779705SSam Leffler     CTRY_KOREA_ROC            = 410,     /* South Korea */
16914779705SSam Leffler     CTRY_KOREA_ROC2           = 411,     /* South Korea */
17014779705SSam Leffler     CTRY_KOREA_ROC3           = 412,     /* South Korea */
17114779705SSam Leffler     CTRY_KUWAIT               = 414,     /* Kuwait */
17214779705SSam Leffler     CTRY_LATVIA               = 428,     /* Latvia */
17314779705SSam Leffler     CTRY_LEBANON              = 422,     /* Lebanon */
17414779705SSam Leffler     CTRY_LIBYA                = 434,     /* Libya */
17514779705SSam Leffler     CTRY_LIECHTENSTEIN        = 438,     /* Liechtenstein */
17614779705SSam Leffler     CTRY_LITHUANIA            = 440,     /* Lithuania */
17714779705SSam Leffler     CTRY_LUXEMBOURG           = 442,     /* Luxembourg */
17814779705SSam Leffler     CTRY_MACAU                = 446,     /* Macau */
17914779705SSam Leffler     CTRY_MACEDONIA            = 807,     /* the Former Yugoslav Republic of Macedonia */
18014779705SSam Leffler     CTRY_MALAYSIA             = 458,     /* Malaysia */
18114779705SSam Leffler     CTRY_MALTA		      = 470,	 /* Malta */
18214779705SSam Leffler     CTRY_MEXICO               = 484,     /* Mexico */
18314779705SSam Leffler     CTRY_MONACO               = 492,     /* Principality of Monaco */
18414779705SSam Leffler     CTRY_MOROCCO              = 504,     /* Morocco */
18514779705SSam Leffler     CTRY_NETHERLANDS          = 528,     /* Netherlands */
18614779705SSam Leffler     CTRY_NEW_ZEALAND          = 554,     /* New Zealand */
18714779705SSam Leffler     CTRY_NICARAGUA            = 558,     /* Nicaragua */
18814779705SSam Leffler     CTRY_NORWAY               = 578,     /* Norway */
18914779705SSam Leffler     CTRY_OMAN                 = 512,     /* Oman */
19014779705SSam Leffler     CTRY_PAKISTAN             = 586,     /* Islamic Republic of Pakistan */
19114779705SSam Leffler     CTRY_PANAMA               = 591,     /* Panama */
19214779705SSam Leffler     CTRY_PARAGUAY             = 600,     /* Paraguay */
19314779705SSam Leffler     CTRY_PERU                 = 604,     /* Peru */
19414779705SSam Leffler     CTRY_PHILIPPINES          = 608,     /* Republic of the Philippines */
19514779705SSam Leffler     CTRY_POLAND               = 616,     /* Poland */
19614779705SSam Leffler     CTRY_PORTUGAL             = 620,     /* Portugal */
19714779705SSam Leffler     CTRY_PUERTO_RICO          = 630,     /* Puerto Rico */
19814779705SSam Leffler     CTRY_QATAR                = 634,     /* Qatar */
19914779705SSam Leffler     CTRY_ROMANIA              = 642,     /* Romania */
20014779705SSam Leffler     CTRY_RUSSIA               = 643,     /* Russia */
20114779705SSam Leffler     CTRY_SAUDI_ARABIA         = 682,     /* Saudi Arabia */
20214779705SSam Leffler     CTRY_SINGAPORE            = 702,     /* Singapore */
20314779705SSam Leffler     CTRY_SLOVAKIA             = 703,     /* Slovak Republic */
20414779705SSam Leffler     CTRY_SLOVENIA             = 705,     /* Slovenia */
20514779705SSam Leffler     CTRY_SOUTH_AFRICA         = 710,     /* South Africa */
20614779705SSam Leffler     CTRY_SPAIN                = 724,     /* Spain */
20714779705SSam Leffler     CTRY_SR9                  = 5000,    /* Ubiquiti SR9 (900MHz/GSM) */
20814779705SSam Leffler     CTRY_SWEDEN               = 752,     /* Sweden */
20914779705SSam Leffler     CTRY_SWITZERLAND          = 756,     /* Switzerland */
21014779705SSam Leffler     CTRY_SYRIA                = 760,     /* Syria */
21114779705SSam Leffler     CTRY_TAIWAN               = 158,     /* Taiwan */
21214779705SSam Leffler     CTRY_THAILAND             = 764,     /* Thailand */
21314779705SSam Leffler     CTRY_TRINIDAD_Y_TOBAGO    = 780,     /* Trinidad y Tobago */
21414779705SSam Leffler     CTRY_TUNISIA              = 788,     /* Tunisia */
21514779705SSam Leffler     CTRY_TURKEY               = 792,     /* Turkey */
21614779705SSam Leffler     CTRY_UAE                  = 784,     /* U.A.E. */
21714779705SSam Leffler     CTRY_UKRAINE              = 804,     /* Ukraine */
21814779705SSam Leffler     CTRY_UNITED_KINGDOM       = 826,     /* United Kingdom */
21914779705SSam Leffler     CTRY_UNITED_STATES        = 840,     /* United States */
22014779705SSam Leffler     CTRY_UNITED_STATES_FCC49  = 842,     /* United States (Public Safety)*/
22114779705SSam Leffler     CTRY_URUGUAY              = 858,     /* Uruguay */
22214779705SSam Leffler     CTRY_UZBEKISTAN           = 860,     /* Uzbekistan */
22314779705SSam Leffler     CTRY_VENEZUELA            = 862,     /* Venezuela */
22414779705SSam Leffler     CTRY_VIET_NAM             = 704,     /* Viet Nam */
22514779705SSam Leffler     CTRY_XR9                  = 5001,    /* Ubiquiti XR9 (900MHz/GSM) */
22614779705SSam Leffler     CTRY_GZ901                = 5002,    /* Zcomax GZ-901 (900MHz/GSM) */
22714779705SSam Leffler     CTRY_YEMEN                = 887,     /* Yemen */
22814779705SSam Leffler     CTRY_ZIMBABWE             = 716      /* Zimbabwe */
22914779705SSam Leffler };
23014779705SSam Leffler 
23114779705SSam Leffler 
23214779705SSam Leffler /*
23314779705SSam Leffler  * Mask to check whether a domain is a multidomain or a single domain
23414779705SSam Leffler  */
23514779705SSam Leffler #define MULTI_DOMAIN_MASK 0xFF00
23614779705SSam Leffler 
23714779705SSam Leffler /*
23814779705SSam Leffler  * Enumerated Regulatory Domain Information 8 bit values indicate that
23914779705SSam Leffler  * the regdomain is really a pair of unitary regdomains.  12 bit values
24014779705SSam Leffler  * are the real unitary regdomains and are the only ones which have the
24114779705SSam Leffler  * frequency bitmasks and flags set.
24214779705SSam Leffler  */
24314779705SSam Leffler enum {
24414779705SSam Leffler 	/*
24514779705SSam Leffler 	 * The following regulatory domain definitions are
24614779705SSam Leffler 	 * found in the EEPROM. Each regulatory domain
24714779705SSam Leffler 	 * can operate in either a 5GHz or 2.4GHz wireless mode or
24814779705SSam Leffler 	 * both 5GHz and 2.4GHz wireless modes.
24914779705SSam Leffler 	 * In general, the value holds no special
25014779705SSam Leffler 	 * meaning and is used to decode into either specific
25114779705SSam Leffler 	 * 2.4GHz or 5GHz wireless mode for that particular
25214779705SSam Leffler 	 * regulatory domain.
25314779705SSam Leffler 	 */
25414779705SSam Leffler 	NO_ENUMRD	= 0x00,
25514779705SSam Leffler 	NULL1_WORLD	= 0x03,		/* For 11b-only countries (no 11a allowed) */
25614779705SSam Leffler 	NULL1_ETSIB	= 0x07,		/* Israel */
25714779705SSam Leffler 	NULL1_ETSIC	= 0x08,
25814779705SSam Leffler 	FCC1_FCCA	= 0x10,		/* USA */
25914779705SSam Leffler 	FCC1_WORLD	= 0x11,		/* Hong Kong */
26014779705SSam Leffler 	FCC4_FCCA	= 0x12,		/* USA - Public Safety */
26114779705SSam Leffler 	FCC5_FCCB	= 0x13,		/* USA w/ 1/2 and 1/4 width channels */
26214779705SSam Leffler 
26314779705SSam Leffler 	FCC2_FCCA	= 0x20,		/* Canada */
26414779705SSam Leffler 	FCC2_WORLD	= 0x21,		/* Australia & HK */
26514779705SSam Leffler 	FCC2_ETSIC	= 0x22,
26614779705SSam Leffler 	FRANCE_RES	= 0x31,		/* Legacy France for OEM */
26714779705SSam Leffler 	FCC3_FCCA	= 0x3A,		/* USA & Canada w/5470 band, 11h, DFS enabled */
26814779705SSam Leffler 	FCC3_WORLD	= 0x3B,		/* USA & Canada w/5470 band, 11h, DFS enabled */
26914779705SSam Leffler 
27014779705SSam Leffler 	ETSI1_WORLD	= 0x37,
27114779705SSam Leffler 	ETSI3_ETSIA	= 0x32,		/* France (optional) */
27214779705SSam Leffler 	ETSI2_WORLD	= 0x35,		/* Hungary & others */
27314779705SSam Leffler 	ETSI3_WORLD	= 0x36,		/* France & others */
27414779705SSam Leffler 	ETSI4_WORLD	= 0x30,
27514779705SSam Leffler 	ETSI4_ETSIC	= 0x38,
27614779705SSam Leffler 	ETSI5_WORLD	= 0x39,
27714779705SSam Leffler 	ETSI6_WORLD	= 0x34,		/* Bulgaria */
27814779705SSam Leffler 	ETSI_RESERVED	= 0x33,		/* Reserved (Do not used) */
27914779705SSam Leffler 
28014779705SSam Leffler 	MKK1_MKKA	= 0x40,		/* Japan (JP1) */
28114779705SSam Leffler 	MKK1_MKKB	= 0x41,		/* Japan (JP0) */
28214779705SSam Leffler 	APL4_WORLD	= 0x42,		/* Singapore */
28314779705SSam Leffler 	MKK2_MKKA	= 0x43,		/* Japan with 4.9G channels */
28414779705SSam Leffler 	APL_RESERVED	= 0x44,		/* Reserved (Do not used)  */
28514779705SSam Leffler 	APL2_WORLD	= 0x45,		/* Korea */
28614779705SSam Leffler 	APL2_APLC	= 0x46,
28714779705SSam Leffler 	APL3_WORLD	= 0x47,
28814779705SSam Leffler 	MKK1_FCCA	= 0x48,		/* Japan (JP1-1) */
28914779705SSam Leffler 	APL2_APLD	= 0x49,		/* Korea with 2.3G channels */
29014779705SSam Leffler 	MKK1_MKKA1	= 0x4A,		/* Japan (JE1) */
29114779705SSam Leffler 	MKK1_MKKA2	= 0x4B,		/* Japan (JE2) */
29214779705SSam Leffler 	MKK1_MKKC	= 0x4C,		/* Japan (MKK1_MKKA,except Ch14) */
29314779705SSam Leffler 
29414779705SSam Leffler 	APL3_FCCA       = 0x50,
29514779705SSam Leffler 	APL1_WORLD	= 0x52,		/* Latin America */
29614779705SSam Leffler 	APL1_FCCA	= 0x53,
29714779705SSam Leffler 	APL1_APLA	= 0x54,
29814779705SSam Leffler 	APL1_ETSIC	= 0x55,
29914779705SSam Leffler 	APL2_ETSIC	= 0x56,		/* Venezuela */
30014779705SSam Leffler 	APL5_WORLD	= 0x58,		/* Chile */
30114779705SSam Leffler 	APL6_WORLD	= 0x5B,		/* Singapore */
30214779705SSam Leffler 	APL7_FCCA   = 0x5C,     /* Taiwan 5.47 Band */
30314779705SSam Leffler 	APL8_WORLD  = 0x5D,     /* Malaysia 5GHz */
30414779705SSam Leffler 	APL9_WORLD  = 0x5E,     /* Korea 5GHz */
30514779705SSam Leffler 
30614779705SSam Leffler 	/*
30714779705SSam Leffler 	 * World mode SKUs
30814779705SSam Leffler 	 */
30914779705SSam Leffler 	WOR0_WORLD	= 0x60,		/* World0 (WO0 SKU) */
31014779705SSam Leffler 	WOR1_WORLD	= 0x61,		/* World1 (WO1 SKU) */
31114779705SSam Leffler 	WOR2_WORLD	= 0x62,		/* World2 (WO2 SKU) */
31214779705SSam Leffler 	WOR3_WORLD	= 0x63,		/* World3 (WO3 SKU) */
31314779705SSam Leffler 	WOR4_WORLD	= 0x64,		/* World4 (WO4 SKU) */
31414779705SSam Leffler 	WOR5_ETSIC	= 0x65,		/* World5 (WO5 SKU) */
31514779705SSam Leffler 
31614779705SSam Leffler 	WOR01_WORLD	= 0x66,		/* World0-1 (WW0-1 SKU) */
31714779705SSam Leffler 	WOR02_WORLD	= 0x67,		/* World0-2 (WW0-2 SKU) */
31814779705SSam Leffler 	EU1_WORLD	= 0x68,		/* Same as World0-2 (WW0-2 SKU), except active scan ch1-13. No ch14 */
31914779705SSam Leffler 
32014779705SSam Leffler 	WOR9_WORLD	= 0x69,		/* World9 (WO9 SKU) */
32114779705SSam Leffler 	WORA_WORLD	= 0x6A,		/* WorldA (WOA SKU) */
32214779705SSam Leffler 
32314779705SSam Leffler 	MKK3_MKKB	= 0x80,		/* Japan UNI-1 even + MKKB */
32414779705SSam Leffler 	MKK3_MKKA2	= 0x81,		/* Japan UNI-1 even + MKKA2 */
32514779705SSam Leffler 	MKK3_MKKC	= 0x82,		/* Japan UNI-1 even + MKKC */
32614779705SSam Leffler 
32714779705SSam Leffler 	MKK4_MKKB	= 0x83,		/* Japan UNI-1 even + UNI-2 + MKKB */
32814779705SSam Leffler 	MKK4_MKKA2	= 0x84,		/* Japan UNI-1 even + UNI-2 + MKKA2 */
32914779705SSam Leffler 	MKK4_MKKC	= 0x85,		/* Japan UNI-1 even + UNI-2 + MKKC */
33014779705SSam Leffler 
33114779705SSam Leffler 	MKK5_MKKB	= 0x86,		/* Japan UNI-1 even + UNI-2 + mid-band + MKKB */
33214779705SSam Leffler 	MKK5_MKKA2	= 0x87,		/* Japan UNI-1 even + UNI-2 + mid-band + MKKA2 */
33314779705SSam Leffler 	MKK5_MKKC	= 0x88,		/* Japan UNI-1 even + UNI-2 + mid-band + MKKC */
33414779705SSam Leffler 
33514779705SSam Leffler 	MKK6_MKKB	= 0x89,		/* Japan UNI-1 even + UNI-1 odd MKKB */
33614779705SSam Leffler 	MKK6_MKKA2	= 0x8A,		/* Japan UNI-1 even + UNI-1 odd + MKKA2 */
33714779705SSam Leffler 	MKK6_MKKC	= 0x8B,		/* Japan UNI-1 even + UNI-1 odd + MKKC */
33814779705SSam Leffler 
33914779705SSam Leffler 	MKK7_MKKB	= 0x8C,		/* Japan UNI-1 even + UNI-1 odd + UNI-2 + MKKB */
34014779705SSam Leffler 	MKK7_MKKA2	= 0x8D,		/* Japan UNI-1 even + UNI-1 odd + UNI-2 + MKKA2 */
34114779705SSam Leffler 	MKK7_MKKC	= 0x8E,		/* Japan UNI-1 even + UNI-1 odd + UNI-2 + MKKC */
34214779705SSam Leffler 
34314779705SSam Leffler 	MKK8_MKKB	= 0x8F,		/* Japan UNI-1 even + UNI-1 odd + UNI-2 + mid-band + MKKB */
34414779705SSam Leffler 	MKK8_MKKA2	= 0x90,		/* Japan UNI-1 even + UNI-1 odd + UNI-2 + mid-band + MKKA2 */
34514779705SSam Leffler 	MKK8_MKKC	= 0x91,		/* Japan UNI-1 even + UNI-1 odd + UNI-2 + mid-band + MKKC */
34614779705SSam Leffler 
34714779705SSam Leffler 	/* Following definitions are used only by s/w to map old
34814779705SSam Leffler  	 * Japan SKUs.
34914779705SSam Leffler 	 */
35014779705SSam Leffler 	MKK3_MKKA       = 0xF0,         /* Japan UNI-1 even + MKKA */
35114779705SSam Leffler 	MKK3_MKKA1      = 0xF1,         /* Japan UNI-1 even + MKKA1 */
35214779705SSam Leffler 	MKK3_FCCA       = 0xF2,         /* Japan UNI-1 even + FCCA */
35314779705SSam Leffler 	MKK4_MKKA       = 0xF3,         /* Japan UNI-1 even + UNI-2 + MKKA */
35414779705SSam Leffler 	MKK4_MKKA1      = 0xF4,         /* Japan UNI-1 even + UNI-2 + MKKA1 */
35514779705SSam Leffler 	MKK4_FCCA       = 0xF5,         /* Japan UNI-1 even + UNI-2 + FCCA */
35614779705SSam Leffler 	MKK9_MKKA       = 0xF6,         /* Japan UNI-1 even + 4.9GHz */
35714779705SSam Leffler 	MKK10_MKKA      = 0xF7,         /* Japan UNI-1 even + UNI-2 + 4.9GHz */
35814779705SSam Leffler 
35914779705SSam Leffler 	/*
36014779705SSam Leffler 	 * Regulator domains ending in a number (e.g. APL1,
36114779705SSam Leffler 	 * MK1, ETSI4, etc) apply to 5GHz channel and power
36214779705SSam Leffler 	 * information.  Regulator domains ending in a letter
36314779705SSam Leffler 	 * (e.g. APLA, FCCA, etc) apply to 2.4GHz channel and
36414779705SSam Leffler 	 * power information.
36514779705SSam Leffler 	 */
36614779705SSam Leffler 	APL1		= 0x0150,	/* LAT & Asia */
36714779705SSam Leffler 	APL2		= 0x0250,	/* LAT & Asia */
36814779705SSam Leffler 	APL3		= 0x0350,	/* Taiwan */
36914779705SSam Leffler 	APL4		= 0x0450,	/* Jordan */
37014779705SSam Leffler 	APL5		= 0x0550,	/* Chile */
37114779705SSam Leffler 	APL6		= 0x0650,	/* Singapore */
37214779705SSam Leffler 	APL8		= 0x0850,	/* Malaysia */
37314779705SSam Leffler 	APL9		= 0x0950,	/* Korea (South) ROC 3 */
37414779705SSam Leffler 
37514779705SSam Leffler 	ETSI1		= 0x0130,	/* Europe & others */
37614779705SSam Leffler 	ETSI2		= 0x0230,	/* Europe & others */
37714779705SSam Leffler 	ETSI3		= 0x0330,	/* Europe & others */
37814779705SSam Leffler 	ETSI4		= 0x0430,	/* Europe & others */
37914779705SSam Leffler 	ETSI5		= 0x0530,	/* Europe & others */
38014779705SSam Leffler 	ETSI6		= 0x0630,	/* Europe & others */
38114779705SSam Leffler 	ETSIA		= 0x0A30,	/* France */
38214779705SSam Leffler 	ETSIB		= 0x0B30,	/* Israel */
38314779705SSam Leffler 	ETSIC		= 0x0C30,	/* Latin America */
38414779705SSam Leffler 
38514779705SSam Leffler 	FCC1		= 0x0110,	/* US & others */
38614779705SSam Leffler 	FCC2		= 0x0120,	/* Canada, Australia & New Zealand */
38714779705SSam Leffler 	FCC3		= 0x0160,	/* US w/new middle band & DFS */
38814779705SSam Leffler 	FCC4          	= 0x0165,     	/* US Public Safety */
38914779705SSam Leffler 	FCC5          	= 0x0166,     	/* US w/ 1/2 and 1/4 width channels */
39014779705SSam Leffler 	FCCA		= 0x0A10,
39114779705SSam Leffler 	FCCB		= 0x0A11,	/* US w/ 1/2 and 1/4 width channels */
39214779705SSam Leffler 
39314779705SSam Leffler 	APLD		= 0x0D50,	/* South Korea */
39414779705SSam Leffler 
39514779705SSam Leffler 	MKK1		= 0x0140,	/* Japan (UNI-1 odd)*/
39614779705SSam Leffler 	MKK2		= 0x0240,	/* Japan (4.9 GHz + UNI-1 odd) */
39714779705SSam Leffler 	MKK3		= 0x0340,	/* Japan (UNI-1 even) */
39814779705SSam Leffler 	MKK4		= 0x0440,	/* Japan (UNI-1 even + UNI-2) */
39914779705SSam Leffler 	MKK5		= 0x0540,	/* Japan (UNI-1 even + UNI-2 + mid-band) */
40014779705SSam Leffler 	MKK6		= 0x0640,	/* Japan (UNI-1 odd + UNI-1 even) */
40114779705SSam Leffler 	MKK7		= 0x0740,	/* Japan (UNI-1 odd + UNI-1 even + UNI-2 */
40214779705SSam Leffler 	MKK8		= 0x0840,	/* Japan (UNI-1 odd + UNI-1 even + UNI-2 + mid-band) */
40314779705SSam Leffler 	MKK9            = 0x0940,       /* Japan (UNI-1 even + 4.9 GHZ) */
40414779705SSam Leffler 	MKK10           = 0x0B40,       /* Japan (UNI-1 even + UNI-2 + 4.9 GHZ) */
40514779705SSam Leffler 	MKKA		= 0x0A40,	/* Japan */
40614779705SSam Leffler 	MKKC		= 0x0A50,
40714779705SSam Leffler 
40814779705SSam Leffler 	NULL1		= 0x0198,
40914779705SSam Leffler 	WORLD		= 0x0199,
41014779705SSam Leffler 	SR9_WORLD	= 0x0298,
41114779705SSam Leffler 	XR9_WORLD	= 0x0299,
41214779705SSam Leffler 	GZ901_WORLD	= 0x029a,
41314779705SSam Leffler 	DEBUG_REG_DMN	= 0x01ff,
41414779705SSam Leffler };
41514779705SSam Leffler 
41614779705SSam Leffler #define	WORLD_SKU_MASK		0x00F0
41714779705SSam Leffler #define	WORLD_SKU_PREFIX	0x0060
41814779705SSam Leffler 
41914779705SSam Leffler enum {					/* conformance test limits */
42014779705SSam Leffler 	FCC	= 0x10,
42114779705SSam Leffler 	MKK	= 0x40,
42214779705SSam Leffler 	ETSI	= 0x30,
42314779705SSam Leffler };
42414779705SSam Leffler 
42514779705SSam Leffler /*
42614779705SSam Leffler  * The following are flags for different requirements per reg domain.
42714779705SSam Leffler  * These requirements are either inhereted from the reg domain pair or
42814779705SSam Leffler  * from the unitary reg domain if the reg domain pair flags value is 0
42914779705SSam Leffler  */
43014779705SSam Leffler enum {
43114779705SSam Leffler 	NO_REQ			= 0x00000000,	/* NB: must be zero */
43214779705SSam Leffler 	DISALLOW_ADHOC_11A	= 0x00000001,
43314779705SSam Leffler 	DISALLOW_ADHOC_11A_TURB	= 0x00000002,
43414779705SSam Leffler 	NEED_NFC		= 0x00000004,
43514779705SSam Leffler 	ADHOC_PER_11D		= 0x00000008,  /* Start Ad-Hoc mode */
43614779705SSam Leffler 	ADHOC_NO_11A		= 0x00000010,
43714779705SSam Leffler 	LIMIT_FRAME_4MS 	= 0x00000020, 	/* 4msec limit on frame length*/
43814779705SSam Leffler 	NO_HOSTAP		= 0x00000040,	/* No HOSTAP mode opereation */
43914779705SSam Leffler };
44014779705SSam Leffler 
44114779705SSam Leffler /*
44214779705SSam Leffler  * The following describe the bit masks for different passive scan
44314779705SSam Leffler  * capability/requirements per regdomain.
44414779705SSam Leffler  */
44514779705SSam Leffler #define	NO_PSCAN	0x0ULL			/* NB: must be zero */
44614779705SSam Leffler #define	PSCAN_FCC	0x0000000000000001ULL
44714779705SSam Leffler #define	PSCAN_FCC_T	0x0000000000000002ULL
44814779705SSam Leffler #define	PSCAN_ETSI	0x0000000000000004ULL
44914779705SSam Leffler #define	PSCAN_MKK1	0x0000000000000008ULL
45014779705SSam Leffler #define	PSCAN_MKK2	0x0000000000000010ULL
45114779705SSam Leffler #define	PSCAN_MKKA	0x0000000000000020ULL
45214779705SSam Leffler #define	PSCAN_MKKA_G	0x0000000000000040ULL
45314779705SSam Leffler #define	PSCAN_ETSIA	0x0000000000000080ULL
45414779705SSam Leffler #define	PSCAN_ETSIB	0x0000000000000100ULL
45514779705SSam Leffler #define	PSCAN_ETSIC	0x0000000000000200ULL
45614779705SSam Leffler #define	PSCAN_WWR	0x0000000000000400ULL
45714779705SSam Leffler #define	PSCAN_MKKA1	0x0000000000000800ULL
45814779705SSam Leffler #define	PSCAN_MKKA1_G	0x0000000000001000ULL
45914779705SSam Leffler #define	PSCAN_MKKA2	0x0000000000002000ULL
46014779705SSam Leffler #define	PSCAN_MKKA2_G	0x0000000000004000ULL
46114779705SSam Leffler #define	PSCAN_MKK3	0x0000000000008000ULL
46214779705SSam Leffler #define	PSCAN_DEFER	0x7FFFFFFFFFFFFFFFULL
46314779705SSam Leffler #define	IS_ECM_CHAN	0x8000000000000000ULL
46414779705SSam Leffler 
46514779705SSam Leffler /*
46614779705SSam Leffler  * THE following table is the mapping of regdomain pairs specified by
46714779705SSam Leffler  * an 8 bit regdomain value to the individual unitary reg domains
46814779705SSam Leffler  */
46914779705SSam Leffler typedef struct {
47014779705SSam Leffler 	HAL_REG_DOMAIN regDmnEnum;	/* 16 bit reg domain pair */
47114779705SSam Leffler 	HAL_REG_DOMAIN regDmn5GHz;	/* 5GHz reg domain */
47214779705SSam Leffler 	HAL_REG_DOMAIN regDmn2GHz;	/* 2GHz reg domain */
47314779705SSam Leffler 	uint32_t flags5GHz;		/* Requirements flags (AdHoc
47414779705SSam Leffler 					   disallow, noise floor cal needed,
47514779705SSam Leffler 					   etc) */
47614779705SSam Leffler 	uint32_t flags2GHz;		/* Requirements flags (AdHoc
47714779705SSam Leffler 					   disallow, noise floor cal needed,
47814779705SSam Leffler 					   etc) */
47914779705SSam Leffler 	uint64_t pscanMask;		/* Passive Scan flags which
48014779705SSam Leffler 					   can override unitary domain
48114779705SSam Leffler 					   passive scan flags.  This
48214779705SSam Leffler 					   value is used as a mask on
48314779705SSam Leffler 					   the unitary flags*/
48414779705SSam Leffler 	uint16_t singleCC;		/* Country code of single country if
48514779705SSam Leffler 					   a one-on-one mapping exists */
48614779705SSam Leffler }  REG_DMN_PAIR_MAPPING;
48714779705SSam Leffler 
48814779705SSam Leffler static REG_DMN_PAIR_MAPPING regDomainPairs[] = {
48914779705SSam Leffler 	{NO_ENUMRD,	DEBUG_REG_DMN,	DEBUG_REG_DMN, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
49014779705SSam Leffler 	{NULL1_WORLD,	NULL1,		WORLD,		NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
49114779705SSam Leffler 	{NULL1_ETSIB,	NULL1,		ETSIB,		NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
49214779705SSam Leffler 	{NULL1_ETSIC,	NULL1,		ETSIC,		NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
49314779705SSam Leffler 
49414779705SSam Leffler 	{FCC2_FCCA,	FCC2,		FCCA,		NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
49514779705SSam Leffler 	{FCC2_WORLD,	FCC2,		WORLD,		NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
49614779705SSam Leffler 	{FCC2_ETSIC,	FCC2,		ETSIC,		NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
49714779705SSam Leffler 	{FCC3_FCCA,	FCC3,		FCCA,		NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
49814779705SSam Leffler 	{FCC3_WORLD,	FCC3,		WORLD,		NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
49914779705SSam Leffler 	{FCC4_FCCA,	FCC4,		FCCA,		DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
50014779705SSam Leffler 	{FCC5_FCCB,	FCC5,		FCCB,		NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
50114779705SSam Leffler 
50214779705SSam Leffler 	{ETSI1_WORLD,	ETSI1,		WORLD,		DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
50314779705SSam Leffler 	{ETSI2_WORLD,	ETSI2,		WORLD,		DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
50414779705SSam Leffler 	{ETSI3_WORLD,	ETSI3,		WORLD,		DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
50514779705SSam Leffler 	{ETSI4_WORLD,	ETSI4,		WORLD,		DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
50614779705SSam Leffler 	{ETSI5_WORLD,	ETSI5,		WORLD,		DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
50714779705SSam Leffler 	{ETSI6_WORLD,	ETSI6,		WORLD,		DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
50814779705SSam Leffler 
50914779705SSam Leffler 	{ETSI3_ETSIA,	ETSI3,		WORLD,		DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
51014779705SSam Leffler 	{FRANCE_RES,	ETSI3,		WORLD,		NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
51114779705SSam Leffler 
51214779705SSam Leffler 	{FCC1_WORLD,	FCC1,		WORLD,		NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
51314779705SSam Leffler 	{FCC1_FCCA,	FCC1,		FCCA,		NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
51414779705SSam Leffler 	{APL1_WORLD,	APL1,		WORLD,		NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
51514779705SSam Leffler 	{APL2_WORLD,	APL2,		WORLD,		NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
51614779705SSam Leffler 	{APL3_WORLD,	APL3,		WORLD,		NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
51714779705SSam Leffler 	{APL4_WORLD,	APL4,		WORLD,		NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
51814779705SSam Leffler 	{APL5_WORLD,	APL5,		WORLD,		NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
51914779705SSam Leffler 	{APL6_WORLD,	APL6,		WORLD,		NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
52014779705SSam Leffler 	{APL8_WORLD,	APL8,		WORLD,		NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
52114779705SSam Leffler 	{APL9_WORLD,	APL9,		WORLD,		NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
52214779705SSam Leffler 
52314779705SSam Leffler 	{APL3_FCCA,	APL3,		FCCA,		NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
52414779705SSam Leffler 	{APL1_ETSIC,	APL1,		ETSIC,		NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
52514779705SSam Leffler 	{APL2_ETSIC,	APL2,		ETSIC,		NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
52614779705SSam Leffler 	{APL2_APLD,	APL2,		APLD,		NO_REQ, NO_REQ, PSCAN_DEFER,  },
52714779705SSam Leffler 
52814779705SSam Leffler 	{MKK1_MKKA,	MKK1,		MKKA,		DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA, CTRY_JAPAN },
52914779705SSam Leffler 	{MKK1_MKKB,	MKK1,		MKKA,		DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC| LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN1 },
53014779705SSam Leffler 	{MKK1_FCCA,	MKK1,		FCCA,		DISALLOW_ADHOC_11A_TURB | NEED_NFC| LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1, CTRY_JAPAN2 },
53114779705SSam Leffler 	{MKK1_MKKA1,	MKK1,		MKKA,		DISALLOW_ADHOC_11A_TURB | NEED_NFC| LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN4 },
53214779705SSam Leffler 	{MKK1_MKKA2,	MKK1,		MKKA,		DISALLOW_ADHOC_11A_TURB | NEED_NFC| LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN5 },
53314779705SSam Leffler 	{MKK1_MKKC,	MKK1,		MKKC,		DISALLOW_ADHOC_11A_TURB | NEED_NFC| LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1, CTRY_JAPAN6 },
53414779705SSam Leffler 
53514779705SSam Leffler 	/* MKK2 */
53614779705SSam Leffler 	{MKK2_MKKA,	MKK2,		MKKA,		DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC| LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK2 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN3 },
53714779705SSam Leffler 
53814779705SSam Leffler 	/* MKK3 */
53914779705SSam Leffler 	{MKK3_MKKA,	MKK3,	MKKA,	DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC , PSCAN_MKKA, 0 },
54014779705SSam Leffler 	{MKK3_MKKB,	MKK3,		MKKA,		DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN7 },
54114779705SSam Leffler 	{MKK3_MKKA1,	MKK3,	MKKA,	DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKKA1 | PSCAN_MKKA1_G, 0 },
54214779705SSam Leffler 	{MKK3_MKKA2,MKK3,		MKKA,		DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN8 },
54314779705SSam Leffler 	{MKK3_MKKC,	MKK3,		MKKC,		DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, NO_PSCAN, CTRY_JAPAN9 },
54414779705SSam Leffler 	{MKK3_FCCA,	MKK3,	FCCA,	DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, NO_PSCAN, 0 },
54514779705SSam Leffler 
54614779705SSam Leffler 	/* MKK4 */
54714779705SSam Leffler 	{MKK4_MKKB,	MKK4,		MKKA,		DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN10 },
54814779705SSam Leffler 	{MKK4_MKKA1,	MKK4,	MKKA,	DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA1 | PSCAN_MKKA1_G, 0 },
54914779705SSam Leffler 	{MKK4_MKKA2,	MKK4,		MKKA,		DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3 |PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN11 },
55014779705SSam Leffler 	{MKK4_MKKC,	MKK4,		MKKC,		DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3, CTRY_JAPAN12 },
55114779705SSam Leffler 	{MKK4_FCCA,	MKK4,	FCCA,	DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3, 0 },
55214779705SSam Leffler 
55314779705SSam Leffler 	/* MKK5 */
55414779705SSam Leffler 	{MKK5_MKKB,	MKK5,		MKKA,		DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN13 },
55514779705SSam Leffler 	{MKK5_MKKA2,MKK5,		MKKA,		DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN14 },
55614779705SSam Leffler 	{MKK5_MKKC,	MKK5,		MKKC,		DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3, CTRY_JAPAN15 },
55714779705SSam Leffler 
55814779705SSam Leffler 	/* MKK6 */
55914779705SSam Leffler 	{MKK6_MKKB,	MKK6,		MKKA,		DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN16 },
56014779705SSam Leffler 	{MKK6_MKKA2,	MKK6,		MKKA,		DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN17 },
56114779705SSam Leffler 	{MKK6_MKKC,	MKK6,		MKKC,		DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1, CTRY_JAPAN18 },
56214779705SSam Leffler 
56314779705SSam Leffler 	/* MKK7 */
56414779705SSam Leffler 	{MKK7_MKKB,	MKK7,		MKKA,		DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN19 },
56514779705SSam Leffler 	{MKK7_MKKA2, MKK7,		MKKA,		DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN20 },
56614779705SSam Leffler 	{MKK7_MKKC,	MKK7,		MKKC,		DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3, CTRY_JAPAN21 },
56714779705SSam Leffler 
56814779705SSam Leffler 	/* MKK8 */
56914779705SSam Leffler 	{MKK8_MKKB,	MKK8,		MKKA,		DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN22 },
57014779705SSam Leffler 	{MKK8_MKKA2,MKK8,		MKKA,		DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN23 },
57114779705SSam Leffler 	{MKK8_MKKC,	MKK8,		MKKC,		DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 , CTRY_JAPAN24 },
57214779705SSam Leffler 
57314779705SSam Leffler 	{MKK9_MKKA,	MKK9,	MKKA,	DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, 0 },
57414779705SSam Leffler 	{MKK10_MKKA,	MKK10,	MKKA,	DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, 0 },
57514779705SSam Leffler 
57614779705SSam Leffler 		/* These are super domains */
57714779705SSam Leffler 	{WOR0_WORLD,	WOR0_WORLD,	WOR0_WORLD,	NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
57814779705SSam Leffler 	{WOR1_WORLD,	WOR1_WORLD,	WOR1_WORLD,	DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
57914779705SSam Leffler 	{WOR2_WORLD,	WOR2_WORLD,	WOR2_WORLD,	DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
58014779705SSam Leffler 	{WOR3_WORLD,	WOR3_WORLD,	WOR3_WORLD,	NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
58114779705SSam Leffler 	{WOR4_WORLD,	WOR4_WORLD,	WOR4_WORLD,	DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
58214779705SSam Leffler 	{WOR5_ETSIC,	WOR5_ETSIC,	WOR5_ETSIC,	DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
58314779705SSam Leffler 	{WOR01_WORLD,	WOR01_WORLD,	WOR01_WORLD,	NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
58414779705SSam Leffler 	{WOR02_WORLD,	WOR02_WORLD,	WOR02_WORLD,	NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
58514779705SSam Leffler 	{EU1_WORLD,	EU1_WORLD,	EU1_WORLD,	NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
58614779705SSam Leffler 	{WOR9_WORLD,	WOR9_WORLD,	WOR9_WORLD,	DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
58714779705SSam Leffler 	{WORA_WORLD,	WORA_WORLD,	WORA_WORLD,	DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
58814779705SSam Leffler 	{SR9_WORLD,	NULL1,		SR9_WORLD,	NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_SR9 },
58914779705SSam Leffler 	{XR9_WORLD,	NULL1,		XR9_WORLD,	NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_XR9 },
59014779705SSam Leffler 	{GZ901_WORLD,	NULL1,		GZ901_WORLD,	NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_GZ901 },
59114779705SSam Leffler };
59214779705SSam Leffler 
59314779705SSam Leffler /*
59414779705SSam Leffler  * The following tables are the master list for all different freqeuncy
59514779705SSam Leffler  * bands with the complete matrix of all possible flags and settings
59614779705SSam Leffler  * for each band if it is used in ANY reg domain.
59714779705SSam Leffler  */
59814779705SSam Leffler 
59914779705SSam Leffler #define DEF_REGDMN		FCC1_FCCA
60014779705SSam Leffler #define	DEF_DMN_5		FCC1
60114779705SSam Leffler #define	DEF_DMN_2		FCCA
60214779705SSam Leffler #define	COUNTRY_ERD_FLAG        0x8000
60314779705SSam Leffler #define WORLDWIDE_ROAMING_FLAG  0x4000
60414779705SSam Leffler #define	SUPER_DOMAIN_MASK	0x0fff
60514779705SSam Leffler #define	COUNTRY_CODE_MASK	0x3fff
60614779705SSam Leffler 
60714779705SSam Leffler #define	YES	AH_TRUE
60814779705SSam Leffler #define	NO	AH_FALSE
60914779705SSam Leffler 
61014779705SSam Leffler typedef struct {
61114779705SSam Leffler 	HAL_CTRY_CODE		countryCode;
61214779705SSam Leffler 	HAL_REG_DOMAIN		regDmnEnum;
61314779705SSam Leffler 	HAL_BOOL		allow11g;
61414779705SSam Leffler 	HAL_BOOL		allow11aTurbo;
61514779705SSam Leffler 	HAL_BOOL		allow11gTurbo;
61614779705SSam Leffler 	HAL_BOOL		allow11ng20;
61714779705SSam Leffler 	HAL_BOOL		allow11ng40;
61814779705SSam Leffler 	HAL_BOOL		allow11na20;
61914779705SSam Leffler 	HAL_BOOL		allow11na40;
62014779705SSam Leffler 	uint16_t		outdoorChanStart;
62114779705SSam Leffler } COUNTRY_CODE_TO_ENUM_RD;
62214779705SSam Leffler 
62314779705SSam Leffler static COUNTRY_CODE_TO_ENUM_RD allCountries[] = {
62414779705SSam Leffler     {CTRY_DEBUG,       NO_ENUMRD,	YES, YES, YES, YES,YES, YES,YES, 7000 },
62514779705SSam Leffler     {CTRY_DEFAULT,     DEF_REGDMN,	YES, YES, YES, YES,YES, YES,YES, 7000 },
62614779705SSam Leffler     {CTRY_ALBANIA,     NULL1_WORLD,	YES,  NO, YES, YES, NO,  NO, NO, 7000 },
62714779705SSam Leffler     {CTRY_ALGERIA,     NULL1_WORLD,	YES,  NO, YES, YES, NO,  NO, NO, 7000 },
62814779705SSam Leffler     {CTRY_ARGENTINA,   APL3_WORLD,	 NO,  NO,  NO,  NO, NO,  NO, NO, 7000 },
62914779705SSam Leffler     {CTRY_ARMENIA,     ETSI4_WORLD,	YES,  NO, YES, YES,YES,  NO, NO, 7000 },
63014779705SSam Leffler     {CTRY_AUSTRALIA,   FCC2_WORLD,      YES, YES, YES, YES,YES, YES,YES, 7000 },
63114779705SSam Leffler     {CTRY_AUSTRIA,     ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
63214779705SSam Leffler     {CTRY_AZERBAIJAN,  ETSI4_WORLD,     YES, YES, YES, YES,YES, YES,YES, 7000 },
63314779705SSam Leffler     {CTRY_BAHRAIN,     APL6_WORLD,	YES,  NO, YES, YES,YES, YES, NO, 7000 },
63414779705SSam Leffler     {CTRY_BELARUS,     NULL1_WORLD,	YES,  NO, YES, YES,YES, YES, NO, 7000 },
63514779705SSam Leffler     {CTRY_BELGIUM,     ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
63614779705SSam Leffler     {CTRY_BELIZE,      APL1_ETSIC,	YES, YES, YES, YES,YES, YES,YES, 7000 },
63714779705SSam Leffler     {CTRY_BOLIVIA,     APL1_ETSIC,	YES, YES, YES, YES,YES, YES,YES, 7000 },
63814779705SSam Leffler     {CTRY_BRAZIL,      FCC3_WORLD,	YES,  NO,  NO, YES, NO, YES, NO, 7000 },
63914779705SSam Leffler     {CTRY_BRUNEI_DARUSSALAM,APL1_WORLD, YES, YES, YES, YES,YES, YES,YES, 7000 },
64014779705SSam Leffler     {CTRY_BULGARIA,    ETSI6_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
64114779705SSam Leffler     {CTRY_CANADA,      FCC2_FCCA,	YES, YES, YES, YES,YES, YES,YES, 7000 },
64214779705SSam Leffler     {CTRY_CHILE,       APL6_WORLD,	YES, YES, YES, YES,YES, YES,YES, 7000 },
64314779705SSam Leffler     {CTRY_CHINA,       APL1_WORLD,	YES, YES, YES, YES,YES, YES,YES, 7000 },
64414779705SSam Leffler     {CTRY_COLOMBIA,    FCC1_FCCA,       YES,  NO, YES, YES,YES, YES, NO, 7000 },
64514779705SSam Leffler     {CTRY_COSTA_RICA,  NULL1_WORLD,     YES,  NO, YES, YES,YES, YES, NO, 7000 },
64614779705SSam Leffler     {CTRY_CROATIA,     ETSI3_WORLD,	YES,  NO, YES, YES,YES, YES, NO, 7000 },
64714779705SSam Leffler     {CTRY_CYPRUS,      ETSI1_WORLD,	YES, YES, YES, YES,YES, YES,YES, 7000 },
64814779705SSam Leffler     {CTRY_CZECH,       ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
64914779705SSam Leffler     {CTRY_DENMARK,     ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
65014779705SSam Leffler     {CTRY_DOMINICAN_REPUBLIC,FCC1_FCCA,	YES, YES, YES, YES,YES, YES,YES, 7000 },
65114779705SSam Leffler     {CTRY_ECUADOR,     NULL1_WORLD,	NO,   NO,  NO,  NO, NO,  NO, NO, 7000 },
65214779705SSam Leffler     {CTRY_EGYPT,       ETSI3_WORLD,	YES,  NO, YES, YES,YES, YES, NO, 7000 },
65314779705SSam Leffler     {CTRY_EL_SALVADOR, NULL1_WORLD,	YES,  NO, YES, YES,YES,  NO, NO, 7000 },
65414779705SSam Leffler     {CTRY_ESTONIA,     ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
65514779705SSam Leffler     {CTRY_FINLAND,     ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
65614779705SSam Leffler     {CTRY_FRANCE,      ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
65714779705SSam Leffler     {CTRY_FRANCE2,     ETSI3_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
65814779705SSam Leffler     {CTRY_GEORGIA,     ETSI4_WORLD,	YES, YES, YES, YES,YES, YES,YES, 7000 },
65914779705SSam Leffler     {CTRY_GERMANY,     ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
66014779705SSam Leffler     {CTRY_GREECE,      ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
66114779705SSam Leffler     {CTRY_GUATEMALA,   FCC1_FCCA,	YES, YES, YES, YES,YES, YES,YES, 7000 },
66214779705SSam Leffler     {CTRY_GZ901,       GZ901_WORLD,     YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
66314779705SSam Leffler     {CTRY_HONDURAS,    NULL1_WORLD,	YES, NO,  YES, YES,YES, YES, NO, 7000 },
66414779705SSam Leffler     {CTRY_HONG_KONG,   FCC2_WORLD,	YES, YES, YES, YES,YES, YES,YES, 7000 },
66514779705SSam Leffler     {CTRY_HUNGARY,     ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
66614779705SSam Leffler     {CTRY_ICELAND,     ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
66714779705SSam Leffler     {CTRY_INDIA,       APL6_WORLD,	YES,  NO, YES, YES,YES, YES, NO, 7000 },
66814779705SSam Leffler     {CTRY_INDONESIA,   APL1_WORLD,	YES,  NO, YES, YES,YES, YES, NO, 7000 },
66914779705SSam Leffler     {CTRY_IRAN,        APL1_WORLD,	YES, YES, YES, YES,YES, YES,YES, 7000 },
67014779705SSam Leffler     {CTRY_IRELAND,     ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
67114779705SSam Leffler     {CTRY_ISRAEL,      NULL1_WORLD,	YES,  NO, YES, YES,YES, YES, NO, 7000 },
67214779705SSam Leffler     {CTRY_ITALY,       ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
67314779705SSam Leffler     {CTRY_JAPAN,       MKK1_MKKA,	YES,  NO,  NO, YES, NO, YES, NO, 7000 },
67414779705SSam Leffler     {CTRY_JAPAN1,      MKK1_MKKB,	YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
67514779705SSam Leffler     {CTRY_JAPAN2,      MKK1_FCCA,	YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
67614779705SSam Leffler     {CTRY_JAPAN3,      MKK2_MKKA,	YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
67714779705SSam Leffler     {CTRY_JAPAN4,      MKK1_MKKA1,	YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
67814779705SSam Leffler     {CTRY_JAPAN5,      MKK1_MKKA2,	YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
67914779705SSam Leffler     {CTRY_JAPAN6,      MKK1_MKKC,	YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
68014779705SSam Leffler 
68114779705SSam Leffler     {CTRY_JAPAN7,      MKK3_MKKB,	YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
68214779705SSam Leffler     {CTRY_JAPAN8,      MKK3_MKKA2,	YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
68314779705SSam Leffler     {CTRY_JAPAN9,      MKK3_MKKC,	YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
68414779705SSam Leffler 
68514779705SSam Leffler     {CTRY_JAPAN10,     MKK4_MKKB,	YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
68614779705SSam Leffler     {CTRY_JAPAN11,     MKK4_MKKA2,	YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
68714779705SSam Leffler     {CTRY_JAPAN12,     MKK4_MKKC,	YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
68814779705SSam Leffler 
68914779705SSam Leffler     {CTRY_JAPAN13,     MKK5_MKKB,	YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
69014779705SSam Leffler     {CTRY_JAPAN14,     MKK5_MKKA2,	YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
69114779705SSam Leffler     {CTRY_JAPAN15,     MKK5_MKKC,	YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
69214779705SSam Leffler 
69314779705SSam Leffler     {CTRY_JAPAN16,     MKK6_MKKB,	YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
69414779705SSam Leffler     {CTRY_JAPAN17,     MKK6_MKKA2,	YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
69514779705SSam Leffler     {CTRY_JAPAN18,     MKK6_MKKC,	YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
69614779705SSam Leffler 
69714779705SSam Leffler     {CTRY_JAPAN19,     MKK7_MKKB,	YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
69814779705SSam Leffler     {CTRY_JAPAN20,     MKK7_MKKA2,	YES,  NO,  NO, YES, NO, YES, NO, 7000 },
69914779705SSam Leffler     {CTRY_JAPAN21,     MKK7_MKKC,	YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
70014779705SSam Leffler 
70114779705SSam Leffler     {CTRY_JAPAN22,     MKK8_MKKB,	YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
70214779705SSam Leffler     {CTRY_JAPAN23,     MKK8_MKKA2,	YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
70314779705SSam Leffler     {CTRY_JAPAN24,     MKK8_MKKC,	YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
70414779705SSam Leffler 
70514779705SSam Leffler     {CTRY_JORDAN,      APL4_WORLD,	YES,  NO, YES, YES,YES, YES, NO, 7000 },
70614779705SSam Leffler     {CTRY_KAZAKHSTAN,  NULL1_WORLD,	YES,  NO, YES, YES,YES,  NO, NO, 7000 },
70714779705SSam Leffler     {CTRY_KOREA_NORTH, APL2_WORLD,	YES, YES, YES, YES,YES, YES,YES, 7000 },
70814779705SSam Leffler     {CTRY_KOREA_ROC,   APL2_WORLD,	YES,  NO,  NO, YES, NO, YES, NO, 7000 },
70914779705SSam Leffler     {CTRY_KOREA_ROC2,  APL2_WORLD,	YES,  NO,  NO, YES, NO, YES, NO, 7000 },
71014779705SSam Leffler     {CTRY_KOREA_ROC3,  APL9_WORLD,	YES,  NO,  NO, YES, NO, YES, NO, 7000 },
71114779705SSam Leffler     {CTRY_KUWAIT,      NULL1_WORLD,	YES,  NO, YES, YES,YES, YES, NO, 7000 },
71214779705SSam Leffler     {CTRY_LATVIA,      ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
71314779705SSam Leffler     {CTRY_LEBANON,     NULL1_WORLD,	YES,  NO, YES, YES,YES, YES, NO, 7000 },
71414779705SSam Leffler     {CTRY_LIECHTENSTEIN,ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
71514779705SSam Leffler     {CTRY_LITHUANIA,   ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
71614779705SSam Leffler     {CTRY_LUXEMBOURG,  ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
71714779705SSam Leffler     {CTRY_MACAU,       FCC2_WORLD,	YES, YES, YES, YES,YES, YES,YES, 7000 },
71814779705SSam Leffler     {CTRY_MACEDONIA,   NULL1_WORLD,	YES,  NO, YES, YES,YES,  NO, NO, 7000 },
71914779705SSam Leffler     {CTRY_MALAYSIA,    APL8_WORLD,	YES,  NO,  NO, YES, NO, YES, NO, 7000 },
72014779705SSam Leffler     {CTRY_MALTA,       ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
72114779705SSam Leffler     {CTRY_MEXICO,      FCC1_FCCA,	YES, YES, YES, YES,YES, YES,YES, 7000 },
72214779705SSam Leffler     {CTRY_MONACO,      ETSI4_WORLD,	YES, YES, YES, YES,YES, YES,YES, 7000 },
72314779705SSam Leffler     {CTRY_MOROCCO,     NULL1_WORLD,	YES,  NO, YES, YES,YES,  NO, NO, 7000 },
72414779705SSam Leffler     {CTRY_NETHERLANDS, ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
72514779705SSam Leffler     {CTRY_NEW_ZEALAND, FCC2_ETSIC,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
72614779705SSam Leffler     {CTRY_NORWAY,      ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
72714779705SSam Leffler     {CTRY_OMAN,        APL6_WORLD,	YES,  NO, YES, YES,YES, YES, NO, 7000 },
72814779705SSam Leffler     {CTRY_PAKISTAN,    NULL1_WORLD,	YES,  NO, YES, YES,YES,  NO, NO, 7000 },
72914779705SSam Leffler     {CTRY_PANAMA,      FCC1_FCCA,	YES, YES, YES, YES,YES, YES,YES, 7000 },
73014779705SSam Leffler     {CTRY_PERU,        APL1_WORLD,	YES,  NO, YES, YES,YES, YES, NO, 7000 },
73114779705SSam Leffler     {CTRY_PHILIPPINES, FCC3_WORLD,	YES, YES, YES, YES,YES, YES,YES, 7000 },
73214779705SSam Leffler     {CTRY_POLAND,      ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
73314779705SSam Leffler     {CTRY_PORTUGAL,    ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
73414779705SSam Leffler     {CTRY_PUERTO_RICO, FCC1_FCCA,	YES, YES, YES, YES,YES, YES,YES, 7000 },
73514779705SSam Leffler     {CTRY_QATAR,       NULL1_WORLD,	YES,  NO, YES, YES,YES,  NO, NO, 7000 },
73614779705SSam Leffler     {CTRY_ROMANIA,     NULL1_WORLD,	YES,  NO, YES, YES,YES,  NO, NO, 7000 },
73714779705SSam Leffler     {CTRY_RUSSIA,      NULL1_WORLD,	YES,  NO, YES, YES,YES,  NO, NO, 7000 },
73814779705SSam Leffler     {CTRY_SAUDI_ARABIA,FCC2_WORLD,	YES,  NO, YES, YES,YES, YES, NO, 7000 },
73914779705SSam Leffler     {CTRY_SINGAPORE,   APL6_WORLD,	YES, YES, YES, YES,YES, YES,YES, 7000 },
74014779705SSam Leffler     {CTRY_SLOVAKIA,    ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
74114779705SSam Leffler     {CTRY_SLOVENIA,    ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
74214779705SSam Leffler     {CTRY_SOUTH_AFRICA,FCC3_WORLD,	YES,  NO, YES, YES,YES, YES, NO, 7000 },
74314779705SSam Leffler     {CTRY_SPAIN,       ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
74414779705SSam Leffler     {CTRY_SR9,         SR9_WORLD,       YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
74514779705SSam Leffler     {CTRY_SWEDEN,      ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
74614779705SSam Leffler     {CTRY_SWITZERLAND, ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
74714779705SSam Leffler     {CTRY_SYRIA,       NULL1_WORLD,	YES,  NO, YES, YES,YES, YES, NO, 7000 },
74814779705SSam Leffler     {CTRY_TAIWAN,      APL3_FCCA,	YES, YES, YES, YES,YES, YES,YES, 7000 },
74914779705SSam Leffler     {CTRY_THAILAND,    NULL1_WORLD,	YES,  NO, YES, YES,YES,  NO, NO, 7000 },
75014779705SSam Leffler     {CTRY_TRINIDAD_Y_TOBAGO,ETSI4_WORLD,YES,  NO, YES, YES,YES, YES, NO, 7000 },
75114779705SSam Leffler     {CTRY_TUNISIA,     ETSI3_WORLD,	YES,  NO, YES, YES,YES, YES, NO, 7000 },
75214779705SSam Leffler     {CTRY_TURKEY,      ETSI3_WORLD,	YES,  NO, YES, YES,YES, YES, NO, 7000 },
75314779705SSam Leffler     {CTRY_UKRAINE,     NULL1_WORLD,	YES,  NO, YES, YES,YES,  NO, NO, 7000 },
75414779705SSam Leffler     {CTRY_UAE,         NULL1_WORLD,	YES,  NO, YES, YES,YES,  NO, NO, 7000 },
75514779705SSam Leffler     {CTRY_UNITED_KINGDOM, ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES, NO, 7000 },
75614779705SSam Leffler     {CTRY_UNITED_STATES, FCC1_FCCA,	YES, YES, YES, YES,YES, YES,YES, 5825 },
75714779705SSam Leffler     {CTRY_UNITED_STATES_FCC49,FCC4_FCCA,YES, YES, YES, YES,YES, YES,YES, 7000 },
75814779705SSam Leffler     {CTRY_URUGUAY,     FCC1_WORLD,	YES,  NO, YES, YES,YES, YES, NO, 7000 },
75914779705SSam Leffler     {CTRY_UZBEKISTAN,  FCC3_FCCA,	YES, YES, YES, YES,YES, YES,YES, 7000 },
76014779705SSam Leffler     {CTRY_VENEZUELA,   APL2_ETSIC,	YES,  NO, YES, YES,YES, YES, NO, 7000 },
76114779705SSam Leffler     {CTRY_VIET_NAM,    NULL1_WORLD,	YES,  NO, YES, YES,YES,  NO, NO, 7000 },
76214779705SSam Leffler     {CTRY_XR9,         XR9_WORLD,       YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
76314779705SSam Leffler     {CTRY_YEMEN,       NULL1_WORLD,	YES,  NO, YES, YES,YES,  NO, NO, 7000 },
76414779705SSam Leffler     {CTRY_ZIMBABWE,    NULL1_WORLD,	YES,  NO, YES, YES,YES,  NO, NO, 7000 }
76514779705SSam Leffler };
76614779705SSam Leffler 
76714779705SSam Leffler /* Bit masks for DFS per regdomain */
76814779705SSam Leffler enum {
76914779705SSam Leffler 	NO_DFS   = 0x0000000000000000ULL,	/* NB: must be zero */
77014779705SSam Leffler 	DFS_FCC3 = 0x0000000000000001ULL,
77114779705SSam Leffler 	DFS_ETSI = 0x0000000000000002ULL,
77214779705SSam Leffler 	DFS_MKK4 = 0x0000000000000004ULL,
77314779705SSam Leffler };
77414779705SSam Leffler 
77514779705SSam Leffler #define	AFTER(x)	((x)+1)
77614779705SSam Leffler 
77714779705SSam Leffler /*
77814779705SSam Leffler  * Frequency band collections are defined using bitmasks.  Each bit
77914779705SSam Leffler  * in a mask is the index of an entry in one of the following tables.
78014779705SSam Leffler  * Bitmasks are BMLEN*64 bits so if a table grows beyond that the bit
78114779705SSam Leffler  * vectors must be enlarged or the tables split somehow (e.g. split
78214779705SSam Leffler  * 1/2 and 1/4 rate channels into a separate table).
78314779705SSam Leffler  *
78414779705SSam Leffler  * Beware of ordering; the indices are defined relative to the preceding
78514779705SSam Leffler  * entry so if things get off there will be confusion.  A good way to
78614779705SSam Leffler  * check the indices is to collect them in a switch statement in a stub
78714779705SSam Leffler  * function so the compiler checks for duplicates.
78814779705SSam Leffler  */
78914779705SSam Leffler 
79014779705SSam Leffler typedef struct {
79114779705SSam Leffler 	uint16_t	lowChannel;	/* Low channel center in MHz */
79214779705SSam Leffler 	uint16_t	highChannel;	/* High Channel center in MHz */
79314779705SSam Leffler 	uint8_t		powerDfs;	/* Max power (dBm) for channel
79414779705SSam Leffler 					   range when using DFS */
79514779705SSam Leffler 	uint8_t		antennaMax;	/* Max allowed antenna gain */
79614779705SSam Leffler 	uint8_t		channelBW;	/* Bandwidth of the channel */
79714779705SSam Leffler 	uint8_t		channelSep;	/* Channel separation within
79814779705SSam Leffler 					   the band */
79914779705SSam Leffler 	uint64_t	useDfs;		/* Use DFS in the RegDomain
80014779705SSam Leffler 					   if corresponding bit is set */
80114779705SSam Leffler 	uint64_t	usePassScan;	/* Use Passive Scan in the RegDomain
80214779705SSam Leffler 					   if corresponding bit is set */
80314779705SSam Leffler 	uint8_t		regClassId;	/* Regulatory class id */
80414779705SSam Leffler } REG_DMN_FREQ_BAND;
80514779705SSam Leffler 
80614779705SSam Leffler /*
80714779705SSam Leffler  * 5GHz 11A channel tags
80814779705SSam Leffler  */
80914779705SSam Leffler static REG_DMN_FREQ_BAND regDmn5GhzFreq[] = {
81014779705SSam Leffler 	{ 4915, 4925, 23, 0, 10,  5, NO_DFS, PSCAN_MKK2, 16 },
81114779705SSam Leffler #define	F1_4915_4925	0
81214779705SSam Leffler 	{ 4935, 4945, 23, 0, 10,  5, NO_DFS, PSCAN_MKK2, 16 },
81314779705SSam Leffler #define	F1_4935_4945	AFTER(F1_4915_4925)
81414779705SSam Leffler 	{ 4920, 4980, 23, 0, 20, 20, NO_DFS, PSCAN_MKK2, 7 },
81514779705SSam Leffler #define	F1_4920_4980	AFTER(F1_4935_4945)
81614779705SSam Leffler 	{ 4942, 4987, 27, 6,  5,  5, NO_DFS, PSCAN_FCC, 0 },
81714779705SSam Leffler #define	F1_4942_4987	AFTER(F1_4920_4980)
81814779705SSam Leffler 	{ 4945, 4985, 30, 6, 10,  5, NO_DFS, PSCAN_FCC, 0 },
81914779705SSam Leffler #define	F1_4945_4985	AFTER(F1_4942_4987)
82014779705SSam Leffler 	{ 4950, 4980, 33, 6, 20,  5, NO_DFS, PSCAN_FCC, 0 },
82114779705SSam Leffler #define	F1_4950_4980	AFTER(F1_4945_4985)
82214779705SSam Leffler 	{ 5035, 5040, 23, 0, 10,  5, NO_DFS, PSCAN_MKK2, 12 },
82314779705SSam Leffler #define	F1_5035_5040	AFTER(F1_4950_4980)
82414779705SSam Leffler 	{ 5040, 5080, 23, 0, 20, 20, NO_DFS, PSCAN_MKK2, 2 },
82514779705SSam Leffler #define	F1_5040_5080	AFTER(F1_5035_5040)
82614779705SSam Leffler 	{ 5055, 5055, 23, 0, 10,  5, NO_DFS, PSCAN_MKK2, 12 },
82714779705SSam Leffler #define	F1_5055_5055	AFTER(F1_5040_5080)
82814779705SSam Leffler 
82914779705SSam Leffler 	{ 5120, 5240, 5,  6, 20, 20, NO_DFS, NO_PSCAN, 0 },
83014779705SSam Leffler #define	F1_5120_5240	AFTER(F1_5055_5055)
83114779705SSam Leffler 	{ 5120, 5240, 5,  6, 10, 10, NO_DFS, NO_PSCAN, 0 },
83214779705SSam Leffler #define	F2_5120_5240	AFTER(F1_5120_5240)
83314779705SSam Leffler 	{ 5120, 5240, 5,  6,  5,  5, NO_DFS, NO_PSCAN, 0 },
83414779705SSam Leffler #define	F3_5120_5240	AFTER(F2_5120_5240)
83514779705SSam Leffler 
83614779705SSam Leffler 	{ 5170, 5230, 23, 0, 20, 20, NO_DFS, PSCAN_MKK1 | PSCAN_MKK2, 1 },
83714779705SSam Leffler #define	F1_5170_5230	AFTER(F3_5120_5240)
83814779705SSam Leffler 	{ 5170, 5230, 20, 0, 20, 20, NO_DFS, PSCAN_MKK1 | PSCAN_MKK2, 1 },
83914779705SSam Leffler #define	F2_5170_5230	AFTER(F1_5170_5230)
84014779705SSam Leffler 
84114779705SSam Leffler 	{ 5180, 5240, 15, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI, 0 },
84214779705SSam Leffler #define	F1_5180_5240	AFTER(F2_5170_5230)
84314779705SSam Leffler 	{ 5180, 5240, 17, 6, 20, 20, NO_DFS, PSCAN_FCC, 1 },
84414779705SSam Leffler #define	F2_5180_5240	AFTER(F1_5180_5240)
84514779705SSam Leffler 	{ 5180, 5240, 18, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI, 0 },
84614779705SSam Leffler #define	F3_5180_5240	AFTER(F2_5180_5240)
84714779705SSam Leffler 	{ 5180, 5240, 20, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI, 0 },
84814779705SSam Leffler #define	F4_5180_5240	AFTER(F3_5180_5240)
84914779705SSam Leffler 	{ 5180, 5240, 23, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI, 0 },
85014779705SSam Leffler #define	F5_5180_5240	AFTER(F4_5180_5240)
85114779705SSam Leffler 	{ 5180, 5240, 23, 6, 20, 20, NO_DFS, PSCAN_FCC, 0 },
85214779705SSam Leffler #define	F6_5180_5240	AFTER(F5_5180_5240)
85314779705SSam Leffler 	{ 5180, 5240, 17, 6, 20, 10, NO_DFS, PSCAN_FCC, 1 },
85414779705SSam Leffler #define	F7_5180_5240	AFTER(F6_5180_5240)
85514779705SSam Leffler 	{ 5180, 5240, 17, 6, 20,  5, NO_DFS, PSCAN_FCC, 1 },
85614779705SSam Leffler #define	F8_5180_5240	AFTER(F7_5180_5240)
85714779705SSam Leffler 
85814779705SSam Leffler 	{ 5180, 5320, 20, 6, 20, 20, DFS_ETSI, PSCAN_ETSI, 0 },
85914779705SSam Leffler #define	F1_5180_5320	AFTER(F8_5180_5240)
86014779705SSam Leffler 
86114779705SSam Leffler 	{ 5240, 5280, 23, 0, 20, 20, DFS_FCC3, PSCAN_FCC | PSCAN_ETSI, 0 },
86214779705SSam Leffler #define	F1_5240_5280	AFTER(F1_5180_5320)
86314779705SSam Leffler 
86414779705SSam Leffler 	{ 5260, 5280, 23, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI, 0 },
86514779705SSam Leffler #define	F1_5260_5280	AFTER(F1_5240_5280)
86614779705SSam Leffler 
86714779705SSam Leffler 	{ 5260, 5320, 18, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI, 0 },
86814779705SSam Leffler #define	F1_5260_5320	AFTER(F1_5260_5280)
86914779705SSam Leffler 
87014779705SSam Leffler 	{ 5260, 5320, 20, 0, 20, 20, DFS_FCC3 | DFS_ETSI | DFS_MKK4, PSCAN_FCC | PSCAN_ETSI | PSCAN_MKK3 , 0 },
87114779705SSam Leffler #define	F2_5260_5320	AFTER(F1_5260_5320)
87214779705SSam Leffler 
87314779705SSam Leffler 	{ 5260, 5320, 20, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 2 },
87414779705SSam Leffler #define	F3_5260_5320	AFTER(F2_5260_5320)
87514779705SSam Leffler 	{ 5260, 5320, 23, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 2 },
87614779705SSam Leffler #define	F4_5260_5320	AFTER(F3_5260_5320)
87714779705SSam Leffler 	{ 5260, 5320, 23, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 0 },
87814779705SSam Leffler #define	F5_5260_5320	AFTER(F4_5260_5320)
87914779705SSam Leffler 	{ 5260, 5320, 30, 0, 20, 20, NO_DFS, NO_PSCAN, 0 },
88014779705SSam Leffler #define	F6_5260_5320	AFTER(F5_5260_5320)
88114779705SSam Leffler 	{ 5260, 5320, 23, 6, 20, 10, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 2 },
88214779705SSam Leffler #define	F7_5260_5320	AFTER(F6_5260_5320)
88314779705SSam Leffler 	{ 5260, 5320, 23, 6, 20,  5, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 2 },
88414779705SSam Leffler #define	F8_5260_5320	AFTER(F7_5260_5320)
88514779705SSam Leffler 
88614779705SSam Leffler 	{ 5260, 5700, 5,  6, 20, 20, DFS_FCC3 | DFS_ETSI, NO_PSCAN, 0 },
88714779705SSam Leffler #define	F1_5260_5700	AFTER(F8_5260_5320)
88814779705SSam Leffler 	{ 5260, 5700, 5,  6, 10, 10, DFS_FCC3 | DFS_ETSI, NO_PSCAN, 0 },
88914779705SSam Leffler #define	F2_5260_5700	AFTER(F1_5260_5700)
89014779705SSam Leffler 	{ 5260, 5700, 5,  6,  5,  5, DFS_FCC3 | DFS_ETSI, NO_PSCAN, 0 },
89114779705SSam Leffler #define	F3_5260_5700	AFTER(F2_5260_5700)
89214779705SSam Leffler 
89314779705SSam Leffler 	{ 5280, 5320, 17, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 0 },
89414779705SSam Leffler #define	F1_5280_5320	AFTER(F3_5260_5700)
89514779705SSam Leffler 
89614779705SSam Leffler 	{ 5500, 5620, 30, 6, 20, 20, DFS_ETSI, PSCAN_ETSI, 0 },
89714779705SSam Leffler #define	F1_5500_5620	AFTER(F1_5280_5320)
89814779705SSam Leffler 
89914779705SSam Leffler 	{ 5500, 5700, 20, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 4 },
90014779705SSam Leffler #define	F1_5500_5700	AFTER(F1_5500_5620)
90114779705SSam Leffler 	{ 5500, 5700, 27, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI, 0 },
90214779705SSam Leffler #define	F2_5500_5700	AFTER(F1_5500_5700)
90314779705SSam Leffler 	{ 5500, 5700, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI, 0 },
90414779705SSam Leffler #define	F3_5500_5700	AFTER(F2_5500_5700)
90514779705SSam Leffler 	{ 5500, 5700, 23, 0, 20, 20, DFS_FCC3 | DFS_ETSI | DFS_MKK4, PSCAN_MKK3 | PSCAN_FCC, 0 },
90614779705SSam Leffler #define	F4_5500_5700	AFTER(F3_5500_5700)
90714779705SSam Leffler 
90814779705SSam Leffler 	{ 5745, 5805, 23, 0, 20, 20, NO_DFS, NO_PSCAN, 0 },
90914779705SSam Leffler #define	F1_5745_5805	AFTER(F4_5500_5700)
91014779705SSam Leffler 	{ 5745, 5805, 30, 6, 20, 20, NO_DFS, NO_PSCAN, 0 },
91114779705SSam Leffler #define	F2_5745_5805	AFTER(F1_5745_5805)
91214779705SSam Leffler 	{ 5745, 5805, 30, 6, 20, 20, DFS_ETSI, PSCAN_ETSI, 0 },
91314779705SSam Leffler #define	F3_5745_5805	AFTER(F2_5745_5805)
91414779705SSam Leffler 	{ 5745, 5825, 5,  6, 20, 20, NO_DFS, NO_PSCAN, 0 },
91514779705SSam Leffler #define	F1_5745_5825	AFTER(F3_5745_5805)
91614779705SSam Leffler 	{ 5745, 5825, 17, 0, 20, 20, NO_DFS, NO_PSCAN, 0 },
91714779705SSam Leffler #define	F2_5745_5825	AFTER(F1_5745_5825)
91814779705SSam Leffler 	{ 5745, 5825, 20, 0, 20, 20, NO_DFS, NO_PSCAN, 0 },
91914779705SSam Leffler #define	F3_5745_5825	AFTER(F2_5745_5825)
92014779705SSam Leffler 	{ 5745, 5825, 30, 0, 20, 20, NO_DFS, NO_PSCAN, 0 },
92114779705SSam Leffler #define	F4_5745_5825	AFTER(F3_5745_5825)
92214779705SSam Leffler 	{ 5745, 5825, 30, 6, 20, 20, NO_DFS, NO_PSCAN, 3 },
92314779705SSam Leffler #define	F5_5745_5825	AFTER(F4_5745_5825)
92414779705SSam Leffler 	{ 5745, 5825, 30, 6, 20, 20, NO_DFS, NO_PSCAN, 0 },
92514779705SSam Leffler #define	F6_5745_5825	AFTER(F5_5745_5825)
92614779705SSam Leffler 	{ 5745, 5825, 5,  6, 10, 10, NO_DFS, NO_PSCAN, 0 },
92714779705SSam Leffler #define	F7_5745_5825	AFTER(F6_5745_5825)
92814779705SSam Leffler 	{ 5745, 5825, 5,  6,  5,  5, NO_DFS, NO_PSCAN, 0 },
92914779705SSam Leffler #define	F8_5745_5825	AFTER(F7_5745_5825)
93014779705SSam Leffler 	{ 5745, 5825, 30, 6, 20, 10, NO_DFS, NO_PSCAN, 3 },
93114779705SSam Leffler #define	F9_5745_5825	AFTER(F8_5745_5825)
93214779705SSam Leffler 	{ 5745, 5825, 30, 6, 20,  5, NO_DFS, NO_PSCAN, 3 },
93314779705SSam Leffler #define	F10_5745_5825	AFTER(F9_5745_5825)
93414779705SSam Leffler 
93514779705SSam Leffler 	/*
93614779705SSam Leffler 	 * Below are the world roaming channels
93714779705SSam Leffler 	 * All WWR domains have no power limit, instead use the card's CTL
93814779705SSam Leffler 	 * or max power settings.
93914779705SSam Leffler 	 */
94014779705SSam Leffler 	{ 4920, 4980, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0 },
94114779705SSam Leffler #define	W1_4920_4980	AFTER(F10_5745_5825)
94214779705SSam Leffler 	{ 5040, 5080, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0 },
94314779705SSam Leffler #define	W1_5040_5080	AFTER(W1_4920_4980)
94414779705SSam Leffler 	{ 5170, 5230, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0 },
94514779705SSam Leffler #define	W1_5170_5230	AFTER(W1_5040_5080)
94614779705SSam Leffler 	{ 5180, 5240, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0 },
94714779705SSam Leffler #define	W1_5180_5240	AFTER(W1_5170_5230)
94814779705SSam Leffler 	{ 5260, 5320, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0 },
94914779705SSam Leffler #define	W1_5260_5320	AFTER(W1_5180_5240)
95014779705SSam Leffler 	{ 5745, 5825, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0 },
95114779705SSam Leffler #define	W1_5745_5825	AFTER(W1_5260_5320)
95214779705SSam Leffler 	{ 5500, 5700, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0 },
95314779705SSam Leffler #define	W1_5500_5700	AFTER(W1_5745_5825)
95414779705SSam Leffler 	{ 5260, 5320, 30, 0, 20, 20, NO_DFS, NO_PSCAN,  0 },
95514779705SSam Leffler #define	W2_5260_5320	AFTER(W1_5500_5700)
95614779705SSam Leffler 	{ 5180, 5240, 30, 0, 20, 20, NO_DFS, NO_PSCAN,  0 },
95714779705SSam Leffler #define	W2_5180_5240	AFTER(W2_5260_5320)
95814779705SSam Leffler 	{ 5825, 5825, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0 },
95914779705SSam Leffler #define	W2_5825_5825	AFTER(W2_5180_5240)
96014779705SSam Leffler };
96114779705SSam Leffler 
96214779705SSam Leffler /*
96314779705SSam Leffler  * 5GHz Turbo (dynamic & static) tags
96414779705SSam Leffler  */
96514779705SSam Leffler static REG_DMN_FREQ_BAND regDmn5GhzTurboFreq[] = {
96614779705SSam Leffler 	{ 5130, 5210, 5,  6, 40, 40, NO_DFS, NO_PSCAN, 0},
96714779705SSam Leffler #define	T1_5130_5210	0
96814779705SSam Leffler 	{ 5250, 5330, 5,  6, 40, 40, DFS_FCC3, NO_PSCAN, 0},
96914779705SSam Leffler #define	T1_5250_5330	AFTER(T1_5130_5210)
97014779705SSam Leffler 	{ 5370, 5490, 5,  6, 40, 40, NO_DFS, NO_PSCAN, 0},
97114779705SSam Leffler #define	T1_5370_5490	AFTER(T1_5250_5330)
97214779705SSam Leffler 	{ 5530, 5650, 5,  6, 40, 40, DFS_FCC3, NO_PSCAN, 0},
97314779705SSam Leffler #define	T1_5530_5650	AFTER(T1_5370_5490)
97414779705SSam Leffler 
97514779705SSam Leffler 	{ 5150, 5190, 5,  6, 40, 40, NO_DFS, NO_PSCAN, 0},
97614779705SSam Leffler #define	T1_5150_5190	AFTER(T1_5530_5650)
97714779705SSam Leffler 	{ 5230, 5310, 5,  6, 40, 40, DFS_FCC3, NO_PSCAN, 0},
97814779705SSam Leffler #define	T1_5230_5310	AFTER(T1_5150_5190)
97914779705SSam Leffler 	{ 5350, 5470, 5,  6, 40, 40, NO_DFS, NO_PSCAN, 0},
98014779705SSam Leffler #define	T1_5350_5470	AFTER(T1_5230_5310)
98114779705SSam Leffler 	{ 5510, 5670, 5,  6, 40, 40, DFS_FCC3, NO_PSCAN, 0},
98214779705SSam Leffler #define	T1_5510_5670	AFTER(T1_5350_5470)
98314779705SSam Leffler 
98414779705SSam Leffler 	{ 5200, 5240, 17, 6, 40, 40, NO_DFS, NO_PSCAN, 0},
98514779705SSam Leffler #define	T1_5200_5240	AFTER(T1_5510_5670)
98614779705SSam Leffler 	{ 5200, 5240, 23, 6, 40, 40, NO_DFS, NO_PSCAN, 0},
98714779705SSam Leffler #define	T2_5200_5240	AFTER(T1_5200_5240)
98814779705SSam Leffler 	{ 5210, 5210, 17, 6, 40, 40, NO_DFS, NO_PSCAN, 0},
98914779705SSam Leffler #define	T1_5210_5210	AFTER(T2_5200_5240)
99014779705SSam Leffler 	{ 5210, 5210, 23, 0, 40, 40, NO_DFS, NO_PSCAN, 0},
99114779705SSam Leffler #define	T2_5210_5210	AFTER(T1_5210_5210)
99214779705SSam Leffler 
99314779705SSam Leffler 	{ 5280, 5280, 23, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0},
99414779705SSam Leffler #define	T1_5280_5280	AFTER(T2_5210_5210)
99514779705SSam Leffler 	{ 5280, 5280, 20, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0},
99614779705SSam Leffler #define	T2_5280_5280	AFTER(T1_5280_5280)
99714779705SSam Leffler 	{ 5250, 5250, 17, 0, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0},
99814779705SSam Leffler #define	T1_5250_5250	AFTER(T2_5280_5280)
99914779705SSam Leffler 	{ 5290, 5290, 20, 0, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0},
100014779705SSam Leffler #define	T1_5290_5290	AFTER(T1_5250_5250)
100114779705SSam Leffler 	{ 5250, 5290, 20, 0, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0},
100214779705SSam Leffler #define	T1_5250_5290	AFTER(T1_5290_5290)
100314779705SSam Leffler 	{ 5250, 5290, 23, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0},
100414779705SSam Leffler #define	T2_5250_5290	AFTER(T1_5250_5290)
100514779705SSam Leffler 
100614779705SSam Leffler 	{ 5540, 5660, 20, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0},
100714779705SSam Leffler #define	T1_5540_5660	AFTER(T2_5250_5290)
100814779705SSam Leffler 	{ 5760, 5800, 20, 0, 40, 40, NO_DFS, NO_PSCAN, 0},
100914779705SSam Leffler #define	T1_5760_5800	AFTER(T1_5540_5660)
101014779705SSam Leffler 	{ 5760, 5800, 30, 6, 40, 40, NO_DFS, NO_PSCAN, 0},
101114779705SSam Leffler #define	T2_5760_5800	AFTER(T1_5760_5800)
101214779705SSam Leffler 
101314779705SSam Leffler 	{ 5765, 5805, 30, 6, 40, 40, NO_DFS, NO_PSCAN, 0},
101414779705SSam Leffler #define	T1_5765_5805	AFTER(T2_5760_5800)
101514779705SSam Leffler 
101614779705SSam Leffler 	/*
101714779705SSam Leffler 	 * Below are the WWR frequencies
101814779705SSam Leffler 	 */
101914779705SSam Leffler 	{ 5210, 5250, 15, 0, 40, 40, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0},
102014779705SSam Leffler #define	WT1_5210_5250	AFTER(T1_5765_5805)
102114779705SSam Leffler 	{ 5290, 5290, 18, 0, 40, 40, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0},
102214779705SSam Leffler #define	WT1_5290_5290	AFTER(WT1_5210_5250)
102314779705SSam Leffler 	{ 5540, 5660, 20, 0, 40, 40, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0},
102414779705SSam Leffler #define	WT1_5540_5660	AFTER(WT1_5290_5290)
102514779705SSam Leffler 	{ 5760, 5800, 20, 0, 40, 40, NO_DFS, PSCAN_WWR, 0},
102614779705SSam Leffler #define	WT1_5760_5800	AFTER(WT1_5540_5660)
102714779705SSam Leffler };
102814779705SSam Leffler 
102914779705SSam Leffler /*
103014779705SSam Leffler  * 2GHz 11b channel tags
103114779705SSam Leffler  */
103214779705SSam Leffler static REG_DMN_FREQ_BAND regDmn2GhzFreq[] = {
103314779705SSam Leffler 	{ 2312, 2372, 5,  6, 20, 5, NO_DFS, NO_PSCAN, 0},
103414779705SSam Leffler #define	F1_2312_2372	0
103514779705SSam Leffler 	{ 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
103614779705SSam Leffler #define	F2_2312_2372	AFTER(F1_2312_2372)
103714779705SSam Leffler 
103814779705SSam Leffler 	{ 2412, 2472, 5,  6, 20, 5, NO_DFS, NO_PSCAN, 0},
103914779705SSam Leffler #define	F1_2412_2472	AFTER(F2_2312_2372)
104014779705SSam Leffler 	{ 2412, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA, 0},
104114779705SSam Leffler #define	F2_2412_2472	AFTER(F1_2412_2472)
104214779705SSam Leffler 	{ 2412, 2472, 30, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
104314779705SSam Leffler #define	F3_2412_2472	AFTER(F2_2412_2472)
104414779705SSam Leffler 
104514779705SSam Leffler 	{ 2412, 2462, 27, 6, 20, 5, NO_DFS, NO_PSCAN, 0},
104614779705SSam Leffler #define	F1_2412_2462	AFTER(F3_2412_2472)
104714779705SSam Leffler 	{ 2412, 2462, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA, 0},
104814779705SSam Leffler #define	F2_2412_2462	AFTER(F1_2412_2462)
104914779705SSam Leffler 
105014779705SSam Leffler 	{ 2432, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
105114779705SSam Leffler #define	F1_2432_2442	AFTER(F2_2412_2462)
105214779705SSam Leffler 
105314779705SSam Leffler 	{ 2457, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
105414779705SSam Leffler #define	F1_2457_2472	AFTER(F1_2432_2442)
105514779705SSam Leffler 
105614779705SSam Leffler 	{ 2467, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA2 | PSCAN_MKKA, 0},
105714779705SSam Leffler #define	F1_2467_2472	AFTER(F1_2457_2472)
105814779705SSam Leffler 
105914779705SSam Leffler 	{ 2484, 2484, 5,  6, 20, 5, NO_DFS, NO_PSCAN, 0},
106014779705SSam Leffler #define	F1_2484_2484	AFTER(F1_2467_2472)
106114779705SSam Leffler 	{ 2484, 2484, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA | PSCAN_MKKA1 | PSCAN_MKKA2, 0},
106214779705SSam Leffler #define	F2_2484_2484	AFTER(F1_2484_2484)
106314779705SSam Leffler 
106414779705SSam Leffler 	{ 2512, 2732, 5,  6, 20, 5, NO_DFS, NO_PSCAN, 0},
106514779705SSam Leffler #define	F1_2512_2732	AFTER(F2_2484_2484)
106614779705SSam Leffler 
106714779705SSam Leffler 	/*
106814779705SSam Leffler 	 * WWR have powers opened up to 20dBm.
106914779705SSam Leffler 	 * Limits should often come from CTL/Max powers
107014779705SSam Leffler 	 */
107114779705SSam Leffler 	{ 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
107214779705SSam Leffler #define	W1_2312_2372	AFTER(F1_2512_2732)
107314779705SSam Leffler 	{ 2412, 2412, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
107414779705SSam Leffler #define	W1_2412_2412	AFTER(W1_2312_2372)
107514779705SSam Leffler 	{ 2417, 2432, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
107614779705SSam Leffler #define	W1_2417_2432	AFTER(W1_2412_2412)
107714779705SSam Leffler 	{ 2437, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
107814779705SSam Leffler #define	W1_2437_2442	AFTER(W1_2417_2432)
107914779705SSam Leffler 	{ 2447, 2457, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
108014779705SSam Leffler #define	W1_2447_2457	AFTER(W1_2437_2442)
108114779705SSam Leffler 	{ 2462, 2462, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
108214779705SSam Leffler #define	W1_2462_2462	AFTER(W1_2447_2457)
108314779705SSam Leffler 	{ 2467, 2467, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0},
108414779705SSam Leffler #define	W1_2467_2467	AFTER(W1_2462_2462)
108514779705SSam Leffler 	{ 2467, 2467, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0},
108614779705SSam Leffler #define	W2_2467_2467	AFTER(W1_2467_2467)
108714779705SSam Leffler 	{ 2472, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0},
108814779705SSam Leffler #define	W1_2472_2472	AFTER(W2_2467_2467)
108914779705SSam Leffler 	{ 2472, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0},
109014779705SSam Leffler #define	W2_2472_2472	AFTER(W1_2472_2472)
109114779705SSam Leffler 	{ 2484, 2484, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0},
109214779705SSam Leffler #define	W1_2484_2484	AFTER(W2_2472_2472)
109314779705SSam Leffler 	{ 2484, 2484, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0},
109414779705SSam Leffler #define	W2_2484_2484	AFTER(W1_2484_2484)
109514779705SSam Leffler };
109614779705SSam Leffler 
109714779705SSam Leffler /*
109814779705SSam Leffler  * 2GHz 11g channel tags
109914779705SSam Leffler  */
110014779705SSam Leffler static REG_DMN_FREQ_BAND regDmn2Ghz11gFreq[] = {
110114779705SSam Leffler 	{ 2312, 2372, 5,  6, 20, 5, NO_DFS, NO_PSCAN, 0},
110214779705SSam Leffler #define	G1_2312_2372	0
110314779705SSam Leffler 	{ 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
110414779705SSam Leffler #define	G2_2312_2372	AFTER(G1_2312_2372)
110514779705SSam Leffler 	{ 2312, 2372, 5,  6, 10, 5, NO_DFS, NO_PSCAN, 0},
110614779705SSam Leffler #define	G3_2312_2372	AFTER(G2_2312_2372)
110714779705SSam Leffler 	{ 2312, 2372, 5,  6,  5, 5, NO_DFS, NO_PSCAN, 0},
110814779705SSam Leffler #define	G4_2312_2372	AFTER(G3_2312_2372)
110914779705SSam Leffler 
111014779705SSam Leffler 	{ 2412, 2472, 5,  6, 20, 5, NO_DFS, NO_PSCAN, 0},
111114779705SSam Leffler #define	G1_2412_2472	AFTER(G4_2312_2372)
111214779705SSam Leffler 	{ 2412, 2472, 20, 0, 20, 5,  NO_DFS, PSCAN_MKKA_G, 0},
111314779705SSam Leffler #define	G2_2412_2472	AFTER(G1_2412_2472)
111414779705SSam Leffler 	{ 2412, 2472, 30, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
111514779705SSam Leffler #define	G3_2412_2472	AFTER(G2_2412_2472)
111614779705SSam Leffler 	{ 2412, 2472, 5,  6, 10, 5, NO_DFS, NO_PSCAN, 0},
111714779705SSam Leffler #define	G4_2412_2472	AFTER(G3_2412_2472)
111814779705SSam Leffler 	{ 2412, 2472, 5,  6,  5, 5, NO_DFS, NO_PSCAN, 0},
111914779705SSam Leffler #define	G5_2412_2472	AFTER(G4_2412_2472)
112014779705SSam Leffler 
112114779705SSam Leffler 	{ 2412, 2462, 27, 6, 20, 5, NO_DFS, NO_PSCAN, 0},
112214779705SSam Leffler #define	G1_2412_2462	AFTER(G5_2412_2472)
112314779705SSam Leffler 	{ 2412, 2462, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA_G, 0},
112414779705SSam Leffler #define	G2_2412_2462	AFTER(G1_2412_2462)
112514779705SSam Leffler 	{ 2412, 2462, 27, 6, 10, 5, NO_DFS, NO_PSCAN, 0},
112614779705SSam Leffler #define	G3_2412_2462	AFTER(G2_2412_2462)
112714779705SSam Leffler 	{ 2412, 2462, 27, 6,  5, 5, NO_DFS, NO_PSCAN, 0},
112814779705SSam Leffler #define	G4_2412_2462	AFTER(G3_2412_2462)
112914779705SSam Leffler 
113014779705SSam Leffler 	{ 2432, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
113114779705SSam Leffler #define	G1_2432_2442	AFTER(G4_2412_2462)
113214779705SSam Leffler 
113314779705SSam Leffler 	{ 2457, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
113414779705SSam Leffler #define	G1_2457_2472	AFTER(G1_2432_2442)
113514779705SSam Leffler 
113614779705SSam Leffler 	{ 2512, 2732, 5,  6, 20, 5, NO_DFS, NO_PSCAN, 0},
113714779705SSam Leffler #define	G1_2512_2732	AFTER(G1_2457_2472)
113814779705SSam Leffler 	{ 2512, 2732, 5,  6, 10, 5, NO_DFS, NO_PSCAN, 0},
113914779705SSam Leffler #define	G2_2512_2732	AFTER(G1_2512_2732)
114014779705SSam Leffler 	{ 2512, 2732, 5,  6,  5, 5, NO_DFS, NO_PSCAN, 0},
114114779705SSam Leffler #define	G3_2512_2732	AFTER(G2_2512_2732)
114214779705SSam Leffler 
114314779705SSam Leffler 	{ 2467, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA2 | PSCAN_MKKA, 0 },
114414779705SSam Leffler #define	G1_2467_2472	AFTER(G3_2512_2732)
114514779705SSam Leffler 
114614779705SSam Leffler 	/*
114714779705SSam Leffler 	 * WWR open up the power to 20dBm
114814779705SSam Leffler 	 */
114914779705SSam Leffler 	{ 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
115014779705SSam Leffler #define	WG1_2312_2372	AFTER(G1_2467_2472)
115114779705SSam Leffler 	{ 2412, 2412, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
115214779705SSam Leffler #define	WG1_2412_2412	AFTER(WG1_2312_2372)
115314779705SSam Leffler 	{ 2417, 2432, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
115414779705SSam Leffler #define	WG1_2417_2432	AFTER(WG1_2412_2412)
115514779705SSam Leffler 	{ 2437, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
115614779705SSam Leffler #define	WG1_2437_2442	AFTER(WG1_2417_2432)
115714779705SSam Leffler 	{ 2447, 2457, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
115814779705SSam Leffler #define	WG1_2447_2457	AFTER(WG1_2437_2442)
115914779705SSam Leffler 	{ 2462, 2462, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
116014779705SSam Leffler #define	WG1_2462_2462	AFTER(WG1_2447_2457)
116114779705SSam Leffler 	{ 2467, 2467, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0},
116214779705SSam Leffler #define	WG1_2467_2467	AFTER(WG1_2462_2462)
116314779705SSam Leffler 	{ 2467, 2467, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0},
116414779705SSam Leffler #define	WG2_2467_2467	AFTER(WG1_2467_2467)
116514779705SSam Leffler 	{ 2472, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0},
116614779705SSam Leffler #define	WG1_2472_2472	AFTER(WG2_2467_2467)
116714779705SSam Leffler 	{ 2472, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0},
116814779705SSam Leffler #define	WG2_2472_2472	AFTER(WG1_2472_2472)
116914779705SSam Leffler 
117014779705SSam Leffler 	/*
117114779705SSam Leffler 	 * Mapping for 900MHz cards like Ubiquiti SR9 and XR9
117214779705SSam Leffler 	 * and ZComax GZ-901.
117314779705SSam Leffler 	 */
117414779705SSam Leffler 	{ 2422, 2437, 30, 0,  5, 5, NO_DFS, PSCAN_FCC, 0 },
117514779705SSam Leffler #define	S1_907_922_5	AFTER(WG2_2472_2472)
117614779705SSam Leffler 	{ 2422, 2437, 30, 0, 10, 5, NO_DFS, PSCAN_FCC, 0 },
117714779705SSam Leffler #define	S1_907_922_10	AFTER(S1_907_922_5)
117814779705SSam Leffler 	{ 2427, 2432, 30, 0, 20, 5, NO_DFS, PSCAN_FCC, 0 },
117914779705SSam Leffler #define	S1_912_917	AFTER(S1_907_922_10)
118014779705SSam Leffler 	{ 2427, 2442, 30, 0,  5, 5, NO_DFS, PSCAN_FCC, 0 },
118114779705SSam Leffler #define	S2_907_922_5	AFTER(S1_912_917)
118214779705SSam Leffler 	{ 2427, 2442, 30, 0, 10, 5, NO_DFS, PSCAN_FCC, 0 },
118314779705SSam Leffler #define	S2_907_922_10	AFTER(S2_907_922_5)
118414779705SSam Leffler 	{ 2432, 2437, 30, 0, 20, 5, NO_DFS, PSCAN_FCC, 0 },
118514779705SSam Leffler #define	S2_912_917	AFTER(S2_907_922_10)
118614779705SSam Leffler 	{ 2452, 2467, 30, 0,  5, 5, NO_DFS, PSCAN_FCC, 0 },
118714779705SSam Leffler #define	S1_908_923_5	AFTER(S2_912_917)
118814779705SSam Leffler 	{ 2457, 2467, 30, 0, 10, 5, NO_DFS, PSCAN_FCC, 0 },
118914779705SSam Leffler #define	S1_913_918_10	AFTER(S1_908_923_5)
119014779705SSam Leffler 	{ 2457, 2467, 30, 0, 20, 5, NO_DFS, PSCAN_FCC, 0 },
119114779705SSam Leffler #define	S1_913_918	AFTER(S1_913_918_10)
119214779705SSam Leffler };
119314779705SSam Leffler 
119414779705SSam Leffler /*
119514779705SSam Leffler  * 2GHz Dynamic turbo tags
119614779705SSam Leffler  */
119714779705SSam Leffler static REG_DMN_FREQ_BAND regDmn2Ghz11gTurboFreq[] = {
119814779705SSam Leffler 	{ 2312, 2372, 5,  6, 40, 40, NO_DFS, NO_PSCAN, 0},
119914779705SSam Leffler #define	T1_2312_2372	0
120014779705SSam Leffler 	{ 2437, 2437, 5,  6, 40, 40, NO_DFS, NO_PSCAN, 0},
120114779705SSam Leffler #define	T1_2437_2437	AFTER(T1_2312_2372)
120214779705SSam Leffler 	{ 2437, 2437, 20, 6, 40, 40, NO_DFS, NO_PSCAN, 0},
120314779705SSam Leffler #define	T2_2437_2437	AFTER(T1_2437_2437)
120414779705SSam Leffler 	{ 2437, 2437, 18, 6, 40, 40, NO_DFS, PSCAN_WWR, 0},
120514779705SSam Leffler #define	T3_2437_2437	AFTER(T2_2437_2437)
120614779705SSam Leffler 	{ 2512, 2732, 5,  6, 40, 40, NO_DFS, NO_PSCAN, 0},
120714779705SSam Leffler #define	T1_2512_2732	AFTER(T3_2437_2437)
120814779705SSam Leffler };
120914779705SSam Leffler 
121014779705SSam Leffler typedef struct regDomain {
121114779705SSam Leffler 	uint16_t regDmnEnum;		/* value from EnumRd table */
121214779705SSam Leffler 	uint8_t conformanceTestLimit;
121314779705SSam Leffler 	uint32_t flags;			/* Requirement flags (AdHoc disallow,
121414779705SSam Leffler 					   noise floor cal needed, etc) */
121514779705SSam Leffler 	uint64_t dfsMask;		/* DFS bitmask for 5Ghz tables */
121614779705SSam Leffler 	uint64_t pscan;			/* Bitmask for passive scan */
121714779705SSam Leffler 	chanbmask_t chan11a;		/* 11a channels */
121814779705SSam Leffler 	chanbmask_t chan11a_turbo;	/* 11a static turbo channels */
121914779705SSam Leffler 	chanbmask_t chan11a_dyn_turbo;	/* 11a dynamic turbo channels */
122014779705SSam Leffler 	chanbmask_t chan11a_half;	/* 11a 1/2 width channels */
122114779705SSam Leffler 	chanbmask_t chan11a_quarter;	/* 11a 1/4 width channels */
122214779705SSam Leffler 	chanbmask_t chan11b;		/* 11b channels */
122314779705SSam Leffler 	chanbmask_t chan11g;		/* 11g channels */
122414779705SSam Leffler 	chanbmask_t chan11g_turbo;	/* 11g dynamic turbo channels */
122514779705SSam Leffler 	chanbmask_t chan11g_half;	/* 11g 1/2 width channels */
122614779705SSam Leffler 	chanbmask_t chan11g_quarter;	/* 11g 1/4 width channels */
122714779705SSam Leffler } REG_DOMAIN;
122814779705SSam Leffler 
122914779705SSam Leffler static REG_DOMAIN regDomains[] = {
123014779705SSam Leffler 
123114779705SSam Leffler 	{.regDmnEnum		= DEBUG_REG_DMN,
123214779705SSam Leffler 	 .conformanceTestLimit	= FCC,
123314779705SSam Leffler 	 .dfsMask		= DFS_FCC3,
123414779705SSam Leffler 	 .chan11a		= BM3(F1_5120_5240, F1_5260_5700, F1_5745_5825),
123514779705SSam Leffler 	 .chan11a_half		= BM3(F2_5120_5240, F2_5260_5700, F7_5745_5825),
123614779705SSam Leffler 	 .chan11a_quarter	= BM3(F3_5120_5240, F3_5260_5700, F8_5745_5825),
123714779705SSam Leffler 	 .chan11a_turbo		= BM8(T1_5130_5210,
123814779705SSam Leffler 				      T1_5250_5330,
123914779705SSam Leffler 				      T1_5370_5490,
124014779705SSam Leffler 				      T1_5530_5650,
124114779705SSam Leffler 				      T1_5150_5190,
124214779705SSam Leffler 				      T1_5230_5310,
124314779705SSam Leffler 				      T1_5350_5470,
124414779705SSam Leffler 				      T1_5510_5670),
124514779705SSam Leffler 	 .chan11a_dyn_turbo	= BM4(T1_5200_5240,
124614779705SSam Leffler 				      T1_5280_5280,
124714779705SSam Leffler 				      T1_5540_5660,
124814779705SSam Leffler 				      T1_5765_5805),
124914779705SSam Leffler 	 .chan11b		= BM4(F1_2312_2372,
125014779705SSam Leffler 				      F1_2412_2472,
125114779705SSam Leffler 				      F1_2484_2484,
125214779705SSam Leffler 				      F1_2512_2732),
125314779705SSam Leffler 	 .chan11g		= BM3(G1_2312_2372, G1_2412_2472, G1_2512_2732),
125414779705SSam Leffler 	 .chan11g_turbo		= BM3(T1_2312_2372, T1_2437_2437, T1_2512_2732),
125514779705SSam Leffler 	 .chan11g_half		= BM3(G2_2312_2372, G4_2412_2472, G2_2512_2732),
125614779705SSam Leffler 	 .chan11g_quarter	= BM3(G3_2312_2372, G5_2412_2472, G3_2512_2732),
125714779705SSam Leffler 	},
125814779705SSam Leffler 
125914779705SSam Leffler 	{.regDmnEnum		= APL1,
126014779705SSam Leffler 	 .conformanceTestLimit	= FCC,
126114779705SSam Leffler 	 .chan11a		= BM1(F4_5745_5825),
126214779705SSam Leffler 	},
126314779705SSam Leffler 
126414779705SSam Leffler 	{.regDmnEnum		= APL2,
126514779705SSam Leffler 	 .conformanceTestLimit	= FCC,
126614779705SSam Leffler 	 .chan11a		= BM1(F1_5745_5805),
126714779705SSam Leffler 	},
126814779705SSam Leffler 
126914779705SSam Leffler 	{.regDmnEnum		= APL3,
127014779705SSam Leffler 	 .conformanceTestLimit	= FCC,
127114779705SSam Leffler 	 .chan11a		= BM2(F1_5280_5320, F2_5745_5805),
127214779705SSam Leffler 	},
127314779705SSam Leffler 
127414779705SSam Leffler 	{.regDmnEnum		= APL4,
127514779705SSam Leffler 	 .conformanceTestLimit	= FCC,
127614779705SSam Leffler 	 .chan11a		= BM2(F4_5180_5240, F3_5745_5825),
127714779705SSam Leffler 	},
127814779705SSam Leffler 
127914779705SSam Leffler 	{.regDmnEnum		= APL5,
128014779705SSam Leffler 	 .conformanceTestLimit	= FCC,
128114779705SSam Leffler 	 .chan11a		= BM1(F2_5745_5825),
128214779705SSam Leffler 	},
128314779705SSam Leffler 
128414779705SSam Leffler 	{.regDmnEnum		= APL6,
128514779705SSam Leffler 	 .conformanceTestLimit	= ETSI,
128614779705SSam Leffler 	 .dfsMask		= DFS_ETSI,
128714779705SSam Leffler 	 .pscan			= PSCAN_FCC_T | PSCAN_FCC,
128814779705SSam Leffler 	 .chan11a		= BM3(F4_5180_5240, F2_5260_5320, F3_5745_5825),
128914779705SSam Leffler 	 .chan11a_turbo		= BM3(T2_5210_5210, T1_5250_5290, T1_5760_5800),
129014779705SSam Leffler 	},
129114779705SSam Leffler 
129214779705SSam Leffler 	{.regDmnEnum		= APL8,
129314779705SSam Leffler 	 .conformanceTestLimit	= ETSI,
129414779705SSam Leffler 	 .flags			= DISALLOW_ADHOC_11A|DISALLOW_ADHOC_11A_TURB,
129514779705SSam Leffler 	 .chan11a		= BM2(F6_5260_5320, F4_5745_5825),
129614779705SSam Leffler 	},
129714779705SSam Leffler 
129814779705SSam Leffler 	{.regDmnEnum		= APL9,
129914779705SSam Leffler 	 .conformanceTestLimit	= ETSI,
130014779705SSam Leffler 	 .dfsMask		= DFS_ETSI,
130114779705SSam Leffler 	 .pscan			= PSCAN_ETSI,
130214779705SSam Leffler 	 .flags			= DISALLOW_ADHOC_11A|DISALLOW_ADHOC_11A_TURB,
130314779705SSam Leffler 	 .chan11a		= BM3(F1_5180_5320, F1_5500_5620, F3_5745_5805),
130414779705SSam Leffler 	},
130514779705SSam Leffler 
130614779705SSam Leffler 	{.regDmnEnum		= ETSI1,
130714779705SSam Leffler 	 .conformanceTestLimit	= ETSI,
130814779705SSam Leffler 	 .dfsMask		= DFS_ETSI,
130914779705SSam Leffler 	 .pscan			= PSCAN_ETSI,
131014779705SSam Leffler 	 .flags			= DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
131114779705SSam Leffler 	 .chan11a		= BM3(W2_5180_5240, F2_5260_5320, F2_5500_5700),
131214779705SSam Leffler 	},
131314779705SSam Leffler 
131414779705SSam Leffler 	{.regDmnEnum		= ETSI2,
131514779705SSam Leffler 	 .conformanceTestLimit	= ETSI,
131614779705SSam Leffler 	 .dfsMask		= DFS_ETSI,
131714779705SSam Leffler 	 .pscan			= PSCAN_ETSI,
131814779705SSam Leffler 	 .flags			= DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
131914779705SSam Leffler 	 .chan11a		= BM1(F3_5180_5240),
132014779705SSam Leffler 	},
132114779705SSam Leffler 
132214779705SSam Leffler 	{.regDmnEnum		= ETSI3,
132314779705SSam Leffler 	 .conformanceTestLimit	= ETSI,
132414779705SSam Leffler 	 .dfsMask		= DFS_ETSI,
132514779705SSam Leffler 	 .pscan			= PSCAN_ETSI,
132614779705SSam Leffler 	 .flags			= DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
132714779705SSam Leffler 	 .chan11a		= BM2(W2_5180_5240, F2_5260_5320),
132814779705SSam Leffler 	},
132914779705SSam Leffler 
133014779705SSam Leffler 	{.regDmnEnum		= ETSI4,
133114779705SSam Leffler 	 .conformanceTestLimit	= ETSI,
133214779705SSam Leffler 	 .dfsMask		= DFS_ETSI,
133314779705SSam Leffler 	 .pscan			= PSCAN_ETSI,
133414779705SSam Leffler 	 .flags			= DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
133514779705SSam Leffler 	 .chan11a		= BM2(F3_5180_5240, F1_5260_5320),
133614779705SSam Leffler 	},
133714779705SSam Leffler 
133814779705SSam Leffler 	{.regDmnEnum		= ETSI5,
133914779705SSam Leffler 	 .conformanceTestLimit	= ETSI,
134014779705SSam Leffler 	 .dfsMask		= DFS_ETSI,
134114779705SSam Leffler 	 .pscan			= PSCAN_ETSI,
134214779705SSam Leffler 	 .flags			= DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
134314779705SSam Leffler 	 .chan11a		= BM1(F1_5180_5240),
134414779705SSam Leffler 	},
134514779705SSam Leffler 
134614779705SSam Leffler 	{.regDmnEnum		= ETSI6,
134714779705SSam Leffler 	 .conformanceTestLimit	= ETSI,
134814779705SSam Leffler 	 .dfsMask		= DFS_ETSI,
134914779705SSam Leffler 	 .pscan			= PSCAN_ETSI,
135014779705SSam Leffler 	 .flags			= DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
135114779705SSam Leffler 	 .chan11a		= BM3(F5_5180_5240, F1_5260_5280, F3_5500_5700),
135214779705SSam Leffler 	},
135314779705SSam Leffler 
135414779705SSam Leffler 	{.regDmnEnum		= FCC1,
135514779705SSam Leffler 	 .conformanceTestLimit	= FCC,
135614779705SSam Leffler 	 .chan11a		= BM3(F2_5180_5240, F4_5260_5320, F5_5745_5825),
135714779705SSam Leffler 	 .chan11a_turbo		= BM3(T1_5210_5210, T2_5250_5290, T2_5760_5800),
135814779705SSam Leffler 	 .chan11a_dyn_turbo	= BM3(T1_5200_5240, T1_5280_5280, T1_5765_5805),
135914779705SSam Leffler 	},
136014779705SSam Leffler 
136114779705SSam Leffler 	{.regDmnEnum		= FCC2,
136214779705SSam Leffler 	 .conformanceTestLimit	= FCC,
136314779705SSam Leffler 	 .chan11a		= BM3(F6_5180_5240, F5_5260_5320, F6_5745_5825),
136414779705SSam Leffler 	 .chan11a_dyn_turbo	= BM3(T2_5200_5240, T1_5280_5280, T1_5765_5805),
136514779705SSam Leffler 	},
136614779705SSam Leffler 
136714779705SSam Leffler 	{.regDmnEnum		= FCC3,
136814779705SSam Leffler 	 .conformanceTestLimit	= FCC,
136914779705SSam Leffler 	 .dfsMask		= DFS_FCC3,
137014779705SSam Leffler 	 .pscan			= PSCAN_FCC | PSCAN_FCC_T,
137114779705SSam Leffler 	 .chan11a		= BM4(F2_5180_5240,
137214779705SSam Leffler 				      F3_5260_5320,
137314779705SSam Leffler 				      F1_5500_5700,
137414779705SSam Leffler 				      F5_5745_5825),
137514779705SSam Leffler 	 .chan11a_turbo		= BM4(T1_5210_5210,
137614779705SSam Leffler 				      T1_5250_5250,
137714779705SSam Leffler 				      T1_5290_5290,
137814779705SSam Leffler 				      T2_5760_5800),
137914779705SSam Leffler 	 .chan11a_dyn_turbo	= BM3(T1_5200_5240, T2_5280_5280, T1_5540_5660),
138014779705SSam Leffler 	},
138114779705SSam Leffler 
138214779705SSam Leffler 	{.regDmnEnum		= FCC4,
138314779705SSam Leffler 	 .conformanceTestLimit	= FCC,
138414779705SSam Leffler 	 .dfsMask		= DFS_FCC3,
138514779705SSam Leffler 	 .pscan			= PSCAN_FCC | PSCAN_FCC_T,
138614779705SSam Leffler 	 .chan11a		= BM1(F1_4950_4980),
138714779705SSam Leffler 	 .chan11a_half		= BM1(F1_4945_4985),
138814779705SSam Leffler 	 .chan11a_quarter	= BM1(F1_4942_4987),
138914779705SSam Leffler 	},
139014779705SSam Leffler 
139114779705SSam Leffler 	/* FCC1 w/ 1/2 and 1/4 width channels */
139214779705SSam Leffler 	{.regDmnEnum		= FCC5,
139314779705SSam Leffler 	 .conformanceTestLimit	= FCC,
139414779705SSam Leffler 	 .chan11a		= BM3(F2_5180_5240, F4_5260_5320, F5_5745_5825),
139514779705SSam Leffler 	 .chan11a_turbo		= BM3(T1_5210_5210, T2_5250_5290, T2_5760_5800),
139614779705SSam Leffler 	 .chan11a_dyn_turbo	= BM3(T1_5200_5240, T1_5280_5280, T1_5765_5805),
139714779705SSam Leffler 	 .chan11a_half		= BM3(F7_5180_5240, F7_5260_5320, F9_5745_5825),
139814779705SSam Leffler 	 .chan11a_quarter	= BM3(F8_5180_5240, F8_5260_5320,F10_5745_5825),
139914779705SSam Leffler 	},
140014779705SSam Leffler 
140114779705SSam Leffler 	{.regDmnEnum		= MKK1,
140214779705SSam Leffler 	 .conformanceTestLimit	= MKK,
140314779705SSam Leffler 	 .pscan			= PSCAN_MKK1,
140414779705SSam Leffler 	 .flags			= DISALLOW_ADHOC_11A_TURB,
140514779705SSam Leffler 	 .chan11a		= BM1(F1_5170_5230),
140614779705SSam Leffler 	},
140714779705SSam Leffler 
140814779705SSam Leffler 	{.regDmnEnum		= MKK2,
140914779705SSam Leffler 	 .conformanceTestLimit	= MKK,
141014779705SSam Leffler 	 .pscan			= PSCAN_MKK2,
141114779705SSam Leffler 	 .flags			= DISALLOW_ADHOC_11A_TURB,
141214779705SSam Leffler 	 .chan11a		= BM3(F1_4920_4980, F1_5040_5080, F1_5170_5230),
141314779705SSam Leffler 	.chan11a_half		= BM4(F1_4915_4925,
141414779705SSam Leffler 				      F1_4935_4945,
141514779705SSam Leffler 				      F1_5035_5040,
141614779705SSam Leffler 				      F1_5055_5055),
141714779705SSam Leffler 	},
141814779705SSam Leffler 
141914779705SSam Leffler 	/* UNI-1 even */
142014779705SSam Leffler 	{.regDmnEnum		= MKK3,
142114779705SSam Leffler 	 .conformanceTestLimit	= MKK,
142214779705SSam Leffler 	 .pscan			= PSCAN_MKK3,
142314779705SSam Leffler 	 .flags			= DISALLOW_ADHOC_11A_TURB,
142414779705SSam Leffler 	 .chan11a		= BM1(F4_5180_5240),
142514779705SSam Leffler 	},
142614779705SSam Leffler 
142714779705SSam Leffler 	/* UNI-1 even + UNI-2 */
142814779705SSam Leffler 	{.regDmnEnum		= MKK4,
142914779705SSam Leffler 	 .conformanceTestLimit	= MKK,
143014779705SSam Leffler 	 .dfsMask		= DFS_MKK4,
143114779705SSam Leffler 	 .pscan			= PSCAN_MKK3,
143214779705SSam Leffler 	 .flags			= DISALLOW_ADHOC_11A_TURB,
143314779705SSam Leffler 	 .chan11a		= BM2(F4_5180_5240, F2_5260_5320),
143414779705SSam Leffler 	},
143514779705SSam Leffler 
143614779705SSam Leffler 	/* UNI-1 even + UNI-2 + mid-band */
143714779705SSam Leffler 	{.regDmnEnum		= MKK5,
143814779705SSam Leffler 	 .conformanceTestLimit	= MKK,
143914779705SSam Leffler 	 .dfsMask		= DFS_MKK4,
144014779705SSam Leffler 	 .pscan			= PSCAN_MKK3,
144114779705SSam Leffler 	 .flags			= DISALLOW_ADHOC_11A_TURB,
144214779705SSam Leffler 	 .chan11a		= BM3(F4_5180_5240, F2_5260_5320, F4_5500_5700),
144314779705SSam Leffler 	},
144414779705SSam Leffler 
144514779705SSam Leffler 	/* UNI-1 odd + even */
144614779705SSam Leffler 	{.regDmnEnum		= MKK6,
144714779705SSam Leffler 	 .conformanceTestLimit	= MKK,
144814779705SSam Leffler 	 .pscan			= PSCAN_MKK1,
144914779705SSam Leffler 	 .flags			= DISALLOW_ADHOC_11A_TURB,
145014779705SSam Leffler 	 .chan11a		= BM2(F2_5170_5230, F4_5180_5240),
145114779705SSam Leffler 	},
145214779705SSam Leffler 
145314779705SSam Leffler 	/* UNI-1 odd + UNI-1 even + UNI-2 */
145414779705SSam Leffler 	{.regDmnEnum		= MKK7,
145514779705SSam Leffler 	 .conformanceTestLimit	= MKK,
145614779705SSam Leffler 	 .dfsMask		= DFS_MKK4,
145714779705SSam Leffler 	 .pscan			= PSCAN_MKK1 | PSCAN_MKK3,
145814779705SSam Leffler 	 .flags			= DISALLOW_ADHOC_11A_TURB,
145914779705SSam Leffler 	 .chan11a		= BM3(F1_5170_5230, F4_5180_5240, F2_5260_5320),
146014779705SSam Leffler 	},
146114779705SSam Leffler 
146214779705SSam Leffler 	/* UNI-1 odd + UNI-1 even + UNI-2 + mid-band */
146314779705SSam Leffler 	{.regDmnEnum		= MKK8,
146414779705SSam Leffler 	 .conformanceTestLimit	= MKK,
146514779705SSam Leffler 	 .dfsMask		= DFS_MKK4,
146614779705SSam Leffler 	 .pscan			= PSCAN_MKK1 | PSCAN_MKK3,
146714779705SSam Leffler 	 .flags			= DISALLOW_ADHOC_11A_TURB,
146814779705SSam Leffler 	 .chan11a		= BM4(F1_5170_5230,
146914779705SSam Leffler 				      F4_5180_5240,
147014779705SSam Leffler 				      F2_5260_5320,
147114779705SSam Leffler 				      F4_5500_5700),
147214779705SSam Leffler 	},
147314779705SSam Leffler 
147414779705SSam Leffler         /* UNI-1 even + 4.9 GHZ */
147514779705SSam Leffler         {.regDmnEnum		= MKK9,
147614779705SSam Leffler 	 .conformanceTestLimit	= MKK,
147714779705SSam Leffler 	 .pscan			= PSCAN_MKK3,
147814779705SSam Leffler 	 .flags			= DISALLOW_ADHOC_11A_TURB,
147914779705SSam Leffler          .chan11a		= BM7(F1_4915_4925,
148014779705SSam Leffler 				      F1_4935_4945,
148114779705SSam Leffler 				      F1_4920_4980,
148214779705SSam Leffler 				      F1_5035_5040,
148314779705SSam Leffler 				      F1_5055_5055,
148414779705SSam Leffler 				      F1_5040_5080,
148514779705SSam Leffler 				      F4_5180_5240),
148614779705SSam Leffler         },
148714779705SSam Leffler 
148814779705SSam Leffler         /* UNI-1 even + UNI-2 + 4.9 GHZ */
148914779705SSam Leffler         {.regDmnEnum		= MKK10,
149014779705SSam Leffler 	 .conformanceTestLimit	= MKK,
149114779705SSam Leffler 	 .dfsMask		= DFS_MKK4,
149214779705SSam Leffler 	 .pscan			= PSCAN_MKK3,
149314779705SSam Leffler 	 .flags			= DISALLOW_ADHOC_11A_TURB,
149414779705SSam Leffler          .chan11a		= BM8(F1_4915_4925,
149514779705SSam Leffler 				      F1_4935_4945,
149614779705SSam Leffler 				      F1_4920_4980,
149714779705SSam Leffler 				      F1_5035_5040,
149814779705SSam Leffler 				      F1_5055_5055,
149914779705SSam Leffler 				      F1_5040_5080,
150014779705SSam Leffler 				      F4_5180_5240,
150114779705SSam Leffler 				      F2_5260_5320),
150214779705SSam Leffler         },
150314779705SSam Leffler 
150414779705SSam Leffler 	/* Defined here to use when 2G channels are authorised for country K2 */
150514779705SSam Leffler 	{.regDmnEnum		= APLD,
150614779705SSam Leffler 	 .conformanceTestLimit	= NO_CTL,
150714779705SSam Leffler 	 .chan11b		= BM2(F2_2312_2372,F2_2412_2472),
150814779705SSam Leffler 	 .chan11g		= BM2(G2_2312_2372,G2_2412_2472),
150914779705SSam Leffler 	},
151014779705SSam Leffler 
151114779705SSam Leffler 	{.regDmnEnum		= ETSIA,
151214779705SSam Leffler 	 .conformanceTestLimit	= NO_CTL,
151314779705SSam Leffler 	 .pscan			= PSCAN_ETSIA,
151414779705SSam Leffler 	 .flags			= DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
151514779705SSam Leffler 	 .chan11b		= BM1(F1_2457_2472),
151614779705SSam Leffler 	 .chan11g		= BM1(G1_2457_2472),
151714779705SSam Leffler 	 .chan11g_turbo		= BM1(T2_2437_2437)
151814779705SSam Leffler 	},
151914779705SSam Leffler 
152014779705SSam Leffler 	{.regDmnEnum		= ETSIB,
152114779705SSam Leffler 	 .conformanceTestLimit	= ETSI,
152214779705SSam Leffler 	 .pscan			= PSCAN_ETSIB,
152314779705SSam Leffler 	 .flags			= DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
152414779705SSam Leffler 	 .chan11b		= BM1(F1_2432_2442),
152514779705SSam Leffler 	 .chan11g		= BM1(G1_2432_2442),
152614779705SSam Leffler 	 .chan11g_turbo		= BM1(T2_2437_2437)
152714779705SSam Leffler 	},
152814779705SSam Leffler 
152914779705SSam Leffler 	{.regDmnEnum		= ETSIC,
153014779705SSam Leffler 	 .conformanceTestLimit	= ETSI,
153114779705SSam Leffler 	 .pscan			= PSCAN_ETSIC,
153214779705SSam Leffler 	 .flags			= DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
153314779705SSam Leffler 	 .chan11b		= BM1(F3_2412_2472),
153414779705SSam Leffler 	 .chan11g		= BM1(G3_2412_2472),
153514779705SSam Leffler 	 .chan11g_turbo		= BM1(T2_2437_2437)
153614779705SSam Leffler 	},
153714779705SSam Leffler 
153814779705SSam Leffler 	{.regDmnEnum		= FCCA,
153914779705SSam Leffler 	 .conformanceTestLimit	= FCC,
154014779705SSam Leffler 	 .chan11b		= BM1(F1_2412_2462),
154114779705SSam Leffler 	 .chan11g		= BM1(G1_2412_2462),
154214779705SSam Leffler 	 .chan11g_turbo		= BM1(T2_2437_2437),
154314779705SSam Leffler 	},
154414779705SSam Leffler 
154514779705SSam Leffler 	/* FCCA w/ 1/2 and 1/4 width channels */
154614779705SSam Leffler 	{.regDmnEnum		= FCCB,
154714779705SSam Leffler 	 .conformanceTestLimit	= FCC,
154814779705SSam Leffler 	 .chan11b		= BM1(F1_2412_2462),
154914779705SSam Leffler 	 .chan11g		= BM1(G1_2412_2462),
155014779705SSam Leffler 	 .chan11g_turbo		= BM1(T2_2437_2437),
155114779705SSam Leffler 	 .chan11g_half		= BM1(G3_2412_2462),
155214779705SSam Leffler 	 .chan11g_quarter	= BM1(G4_2412_2462),
155314779705SSam Leffler 	},
155414779705SSam Leffler 
155514779705SSam Leffler 	{.regDmnEnum		= MKKA,
155614779705SSam Leffler 	 .conformanceTestLimit	= MKK,
155714779705SSam Leffler 	 .pscan			= PSCAN_MKKA | PSCAN_MKKA_G
155814779705SSam Leffler 				| PSCAN_MKKA1 | PSCAN_MKKA1_G
155914779705SSam Leffler 				| PSCAN_MKKA2 | PSCAN_MKKA2_G,
156014779705SSam Leffler 	 .flags			= DISALLOW_ADHOC_11A_TURB,
156114779705SSam Leffler 	 .chan11b		= BM3(F2_2412_2462, F1_2467_2472, F2_2484_2484),
156214779705SSam Leffler 	 .chan11g		= BM2(G2_2412_2462, G1_2467_2472),
156314779705SSam Leffler 	 .chan11g_turbo		= BM1(T2_2437_2437)
156414779705SSam Leffler 	},
156514779705SSam Leffler 
156614779705SSam Leffler 	{.regDmnEnum		= MKKC,
156714779705SSam Leffler 	 .conformanceTestLimit	= MKK,
156814779705SSam Leffler 	 .chan11b		= BM1(F2_2412_2472),
156914779705SSam Leffler 	 .chan11g		= BM1(G2_2412_2472),
157014779705SSam Leffler 	 .chan11g_turbo		= BM1(T2_2437_2437)
157114779705SSam Leffler 	},
157214779705SSam Leffler 
157314779705SSam Leffler 	{.regDmnEnum		= WORLD,
157414779705SSam Leffler 	 .conformanceTestLimit	= ETSI,
157514779705SSam Leffler 	 .chan11b		= BM1(F2_2412_2472),
157614779705SSam Leffler 	 .chan11g		= BM1(G2_2412_2472),
157714779705SSam Leffler 	 .chan11g_turbo		= BM1(T2_2437_2437)
157814779705SSam Leffler 	},
157914779705SSam Leffler 
158014779705SSam Leffler 	{.regDmnEnum		= WOR0_WORLD,
158114779705SSam Leffler 	 .conformanceTestLimit	= NO_CTL,
158214779705SSam Leffler 	 .dfsMask		= DFS_FCC3 | DFS_ETSI,
158314779705SSam Leffler 	 .pscan			= PSCAN_WWR,
158414779705SSam Leffler 	 .flags			= ADHOC_PER_11D,
158514779705SSam Leffler 	 .chan11a		= BM5(W1_5260_5320,
158614779705SSam Leffler 				      W1_5180_5240,
158714779705SSam Leffler 				      W1_5170_5230,
158814779705SSam Leffler 				      W1_5745_5825,
158914779705SSam Leffler 				      W1_5500_5700),
159014779705SSam Leffler 	 .chan11a_turbo		= BM3(WT1_5210_5250,
159114779705SSam Leffler 				      WT1_5290_5290,
159214779705SSam Leffler 				      WT1_5760_5800),
159314779705SSam Leffler 	 .chan11b		= BM8(W1_2412_2412,
159414779705SSam Leffler 				      W1_2437_2442,
159514779705SSam Leffler 				      W1_2462_2462,
159614779705SSam Leffler 				      W1_2472_2472,
159714779705SSam Leffler 				      W1_2417_2432,
159814779705SSam Leffler 				      W1_2447_2457,
159914779705SSam Leffler 				      W1_2467_2467,
160014779705SSam Leffler 				      W1_2484_2484),
160114779705SSam Leffler 	 .chan11g		= BM7(WG1_2412_2412,
160214779705SSam Leffler 				      WG1_2437_2442,
160314779705SSam Leffler 				      WG1_2462_2462,
160414779705SSam Leffler 				      WG1_2472_2472,
160514779705SSam Leffler 				      WG1_2417_2432,
160614779705SSam Leffler 				      WG1_2447_2457,
160714779705SSam Leffler 				      WG1_2467_2467),
160814779705SSam Leffler 	 .chan11g_turbo		= BM1(T3_2437_2437)
160914779705SSam Leffler 	},
161014779705SSam Leffler 
161114779705SSam Leffler 	{.regDmnEnum		= WOR01_WORLD,
161214779705SSam Leffler 	 .conformanceTestLimit	= NO_CTL,
161314779705SSam Leffler 	 .dfsMask		= DFS_FCC3 | DFS_ETSI,
161414779705SSam Leffler 	 .pscan			= PSCAN_WWR,
161514779705SSam Leffler 	 .flags			= ADHOC_PER_11D,
161614779705SSam Leffler 	 .chan11a		= BM5(W1_5260_5320,
161714779705SSam Leffler 				      W1_5180_5240,
161814779705SSam Leffler 				      W1_5170_5230,
161914779705SSam Leffler 				      W1_5745_5825,
162014779705SSam Leffler 				      W1_5500_5700),
162114779705SSam Leffler 	 .chan11a_turbo		= BM3(WT1_5210_5250,
162214779705SSam Leffler 				      WT1_5290_5290,
162314779705SSam Leffler 				      WT1_5760_5800),
162414779705SSam Leffler 	 .chan11b		= BM5(W1_2412_2412,
162514779705SSam Leffler 				      W1_2437_2442,
162614779705SSam Leffler 				      W1_2462_2462,
162714779705SSam Leffler 				      W1_2417_2432,
162814779705SSam Leffler 				      W1_2447_2457),
162914779705SSam Leffler 	 .chan11g		= BM5(WG1_2412_2412,
163014779705SSam Leffler 				      WG1_2437_2442,
163114779705SSam Leffler 				      WG1_2462_2462,
163214779705SSam Leffler 				      WG1_2417_2432,
163314779705SSam Leffler 				      WG1_2447_2457),
163414779705SSam Leffler 	 .chan11g_turbo		= BM1(T3_2437_2437)},
163514779705SSam Leffler 
163614779705SSam Leffler 	{.regDmnEnum		= WOR02_WORLD,
163714779705SSam Leffler 	 .conformanceTestLimit	= NO_CTL,
163814779705SSam Leffler 	 .dfsMask		= DFS_FCC3 | DFS_ETSI,
163914779705SSam Leffler 	 .pscan			= PSCAN_WWR,
164014779705SSam Leffler 	 .flags			= ADHOC_PER_11D,
164114779705SSam Leffler 	 .chan11a		= BM5(W1_5260_5320,
164214779705SSam Leffler 				      W1_5180_5240,
164314779705SSam Leffler 				      W1_5170_5230,
164414779705SSam Leffler 				      W1_5745_5825,
164514779705SSam Leffler 				      W1_5500_5700),
164614779705SSam Leffler 	 .chan11a_turbo		= BM3(WT1_5210_5250,
164714779705SSam Leffler 				      WT1_5290_5290,
164814779705SSam Leffler 				      WT1_5760_5800),
164914779705SSam Leffler 	 .chan11b		= BM7(W1_2412_2412,
165014779705SSam Leffler 				      W1_2437_2442,
165114779705SSam Leffler 				      W1_2462_2462,
165214779705SSam Leffler 				      W1_2472_2472,
165314779705SSam Leffler 				      W1_2417_2432,
165414779705SSam Leffler 				      W1_2447_2457,
165514779705SSam Leffler 				      W1_2467_2467),
165614779705SSam Leffler 	 .chan11g		= BM7(WG1_2412_2412,
165714779705SSam Leffler 				      WG1_2437_2442,
165814779705SSam Leffler 				      WG1_2462_2462,
165914779705SSam Leffler 				      WG1_2472_2472,
166014779705SSam Leffler 				      WG1_2417_2432,
166114779705SSam Leffler 				      WG1_2447_2457,
166214779705SSam Leffler 				      WG1_2467_2467),
166314779705SSam Leffler 	 .chan11g_turbo		= BM1(T3_2437_2437)},
166414779705SSam Leffler 
166514779705SSam Leffler 	{.regDmnEnum		= EU1_WORLD,
166614779705SSam Leffler 	 .conformanceTestLimit	= NO_CTL,
166714779705SSam Leffler 	 .dfsMask		= DFS_FCC3 | DFS_ETSI,
166814779705SSam Leffler 	 .pscan			= PSCAN_WWR,
166914779705SSam Leffler 	 .flags			= ADHOC_PER_11D,
167014779705SSam Leffler 	 .chan11a		= BM5(W1_5260_5320,
167114779705SSam Leffler 				      W1_5180_5240,
167214779705SSam Leffler 				      W1_5170_5230,
167314779705SSam Leffler 				      W1_5745_5825,
167414779705SSam Leffler 				      W1_5500_5700),
167514779705SSam Leffler 	 .chan11a_turbo		= BM3(WT1_5210_5250,
167614779705SSam Leffler 				      WT1_5290_5290,
167714779705SSam Leffler 				      WT1_5760_5800),
167814779705SSam Leffler 	 .chan11b		= BM7(W1_2412_2412,
167914779705SSam Leffler 				      W1_2437_2442,
168014779705SSam Leffler 				      W1_2462_2462,
168114779705SSam Leffler 				      W2_2472_2472,
168214779705SSam Leffler 				      W1_2417_2432,
168314779705SSam Leffler 				      W1_2447_2457,
168414779705SSam Leffler 				      W2_2467_2467),
168514779705SSam Leffler 	 .chan11g		= BM7(WG1_2412_2412,
168614779705SSam Leffler 				      WG1_2437_2442,
168714779705SSam Leffler 				      WG1_2462_2462,
168814779705SSam Leffler 				      WG2_2472_2472,
168914779705SSam Leffler 				      WG1_2417_2432,
169014779705SSam Leffler 				      WG1_2447_2457,
169114779705SSam Leffler 				      WG2_2467_2467),
169214779705SSam Leffler 	 .chan11g_turbo		= BM1(T3_2437_2437)},
169314779705SSam Leffler 
169414779705SSam Leffler 	{.regDmnEnum		= WOR1_WORLD,
169514779705SSam Leffler 	 .conformanceTestLimit	= NO_CTL,
169614779705SSam Leffler 	 .dfsMask		= DFS_FCC3 | DFS_ETSI,
169714779705SSam Leffler 	 .pscan			= PSCAN_WWR,
169814779705SSam Leffler 	 .flags			= ADHOC_NO_11A,
169914779705SSam Leffler 	 .chan11a		= BM5(W1_5260_5320,
170014779705SSam Leffler 				      W1_5180_5240,
170114779705SSam Leffler 				      W1_5170_5230,
170214779705SSam Leffler 				      W1_5745_5825,
170314779705SSam Leffler 				      W1_5500_5700),
170414779705SSam Leffler 	 .chan11b		= BM8(W1_2412_2412,
170514779705SSam Leffler 				      W1_2437_2442,
170614779705SSam Leffler 				      W1_2462_2462,
170714779705SSam Leffler 				      W1_2472_2472,
170814779705SSam Leffler 				      W1_2417_2432,
170914779705SSam Leffler 				      W1_2447_2457,
171014779705SSam Leffler 				      W1_2467_2467,
171114779705SSam Leffler 				      W1_2484_2484),
171214779705SSam Leffler 	 .chan11g		= BM7(WG1_2412_2412,
171314779705SSam Leffler 				      WG1_2437_2442,
171414779705SSam Leffler 				      WG1_2462_2462,
171514779705SSam Leffler 				      WG1_2472_2472,
171614779705SSam Leffler 				      WG1_2417_2432,
171714779705SSam Leffler 				      WG1_2447_2457,
171814779705SSam Leffler 				      WG1_2467_2467),
171914779705SSam Leffler 	 .chan11g_turbo		= BM1(T3_2437_2437)
172014779705SSam Leffler 	},
172114779705SSam Leffler 
172214779705SSam Leffler 	{.regDmnEnum		= WOR2_WORLD,
172314779705SSam Leffler 	 .conformanceTestLimit	= NO_CTL,
172414779705SSam Leffler 	 .dfsMask		= DFS_FCC3 | DFS_ETSI,
172514779705SSam Leffler 	 .pscan			= PSCAN_WWR,
172614779705SSam Leffler 	 .flags			= ADHOC_NO_11A,
172714779705SSam Leffler 	 .chan11a		= BM5(W1_5260_5320,
172814779705SSam Leffler 				      W1_5180_5240,
172914779705SSam Leffler 				      W1_5170_5230,
173014779705SSam Leffler 				      W1_5745_5825,
173114779705SSam Leffler 				      W1_5500_5700),
173214779705SSam Leffler 	 .chan11a_turbo		= BM3(WT1_5210_5250,
173314779705SSam Leffler 				      WT1_5290_5290,
173414779705SSam Leffler 				      WT1_5760_5800),
173514779705SSam Leffler 	 .chan11b		= BM8(W1_2412_2412,
173614779705SSam Leffler 				      W1_2437_2442,
173714779705SSam Leffler 				      W1_2462_2462,
173814779705SSam Leffler 				      W1_2472_2472,
173914779705SSam Leffler 				      W1_2417_2432,
174014779705SSam Leffler 				      W1_2447_2457,
174114779705SSam Leffler 				      W1_2467_2467,
174214779705SSam Leffler 				      W1_2484_2484),
174314779705SSam Leffler 	 .chan11g		= BM7(WG1_2412_2412,
174414779705SSam Leffler 				      WG1_2437_2442,
174514779705SSam Leffler 				      WG1_2462_2462,
174614779705SSam Leffler 				      WG1_2472_2472,
174714779705SSam Leffler 				      WG1_2417_2432,
174814779705SSam Leffler 				      WG1_2447_2457,
174914779705SSam Leffler 				      WG1_2467_2467),
175014779705SSam Leffler 	 .chan11g_turbo		= BM1(T3_2437_2437)},
175114779705SSam Leffler 
175214779705SSam Leffler 	{.regDmnEnum		= WOR3_WORLD,
175314779705SSam Leffler 	 .conformanceTestLimit	= NO_CTL,
175414779705SSam Leffler 	 .dfsMask		= DFS_FCC3 | DFS_ETSI,
175514779705SSam Leffler 	 .pscan			= PSCAN_WWR,
175614779705SSam Leffler 	 .flags			= ADHOC_PER_11D,
175714779705SSam Leffler 	 .chan11a		= BM4(W1_5260_5320,
175814779705SSam Leffler 				      W1_5180_5240,
175914779705SSam Leffler 				      W1_5170_5230,
176014779705SSam Leffler 				      W1_5745_5825),
176114779705SSam Leffler 	 .chan11a_turbo		= BM3(WT1_5210_5250,
176214779705SSam Leffler 				      WT1_5290_5290,
176314779705SSam Leffler 				      WT1_5760_5800),
176414779705SSam Leffler 	 .chan11b		= BM7(W1_2412_2412,
176514779705SSam Leffler 				      W1_2437_2442,
176614779705SSam Leffler 				      W1_2462_2462,
176714779705SSam Leffler 				      W1_2472_2472,
176814779705SSam Leffler 				      W1_2417_2432,
176914779705SSam Leffler 				      W1_2447_2457,
177014779705SSam Leffler 				      W1_2467_2467),
177114779705SSam Leffler 	 .chan11g		= BM7(WG1_2412_2412,
177214779705SSam Leffler 				      WG1_2437_2442,
177314779705SSam Leffler 				      WG1_2462_2462,
177414779705SSam Leffler 				      WG1_2472_2472,
177514779705SSam Leffler 				      WG1_2417_2432,
177614779705SSam Leffler 				      WG1_2447_2457,
177714779705SSam Leffler 				      WG1_2467_2467),
177814779705SSam Leffler 	 .chan11g_turbo		= BM1(T3_2437_2437)},
177914779705SSam Leffler 
178014779705SSam Leffler 	{.regDmnEnum		= WOR4_WORLD,
178114779705SSam Leffler 	 .conformanceTestLimit	= NO_CTL,
178214779705SSam Leffler 	 .dfsMask		= DFS_FCC3 | DFS_ETSI,
178314779705SSam Leffler 	 .pscan			= PSCAN_WWR,
178414779705SSam Leffler 	 .flags			= ADHOC_NO_11A,
178514779705SSam Leffler 	 .chan11a		= BM4(W2_5260_5320,
178614779705SSam Leffler 				      W2_5180_5240,
178714779705SSam Leffler 				      F2_5745_5805,
178814779705SSam Leffler 				      W2_5825_5825),
178914779705SSam Leffler 	 .chan11a_turbo		= BM3(WT1_5210_5250,
179014779705SSam Leffler 				      WT1_5290_5290,
179114779705SSam Leffler 				      WT1_5760_5800),
179214779705SSam Leffler 	 .chan11b		= BM5(W1_2412_2412,
179314779705SSam Leffler 				      W1_2437_2442,
179414779705SSam Leffler 				      W1_2462_2462,
179514779705SSam Leffler 				      W1_2417_2432,
179614779705SSam Leffler 				      W1_2447_2457),
179714779705SSam Leffler 	 .chan11g		= BM5(WG1_2412_2412,
179814779705SSam Leffler 				      WG1_2437_2442,
179914779705SSam Leffler 				      WG1_2462_2462,
180014779705SSam Leffler 				      WG1_2417_2432,
180114779705SSam Leffler 				      WG1_2447_2457),
180214779705SSam Leffler 	 .chan11g_turbo		= BM1(T3_2437_2437)},
180314779705SSam Leffler 
180414779705SSam Leffler 	{.regDmnEnum		= WOR5_ETSIC,
180514779705SSam Leffler 	 .conformanceTestLimit	= NO_CTL,
180614779705SSam Leffler 	 .dfsMask		= DFS_FCC3 | DFS_ETSI,
180714779705SSam Leffler 	 .pscan			= PSCAN_WWR,
180814779705SSam Leffler 	 .flags			= ADHOC_NO_11A,
180914779705SSam Leffler 	 .chan11a		= BM3(W1_5260_5320, W2_5180_5240, F6_5745_5825),
181014779705SSam Leffler 	 .chan11b		= BM7(W1_2412_2412,
181114779705SSam Leffler 				      W1_2437_2442,
181214779705SSam Leffler 				      W1_2462_2462,
181314779705SSam Leffler 				      W2_2472_2472,
181414779705SSam Leffler 				      W1_2417_2432,
181514779705SSam Leffler 				      W1_2447_2457,
181614779705SSam Leffler 				      W2_2467_2467),
181714779705SSam Leffler 	 .chan11g		= BM7(WG1_2412_2412,
181814779705SSam Leffler 				      WG1_2437_2442,
181914779705SSam Leffler 				      WG1_2462_2462,
182014779705SSam Leffler 				      WG2_2472_2472,
182114779705SSam Leffler 				      WG1_2417_2432,
182214779705SSam Leffler 				      WG1_2447_2457,
182314779705SSam Leffler 				      WG2_2467_2467),
182414779705SSam Leffler 	 .chan11g_turbo		= BM1(T3_2437_2437)},
182514779705SSam Leffler 
182614779705SSam Leffler 	{.regDmnEnum		= WOR9_WORLD,
182714779705SSam Leffler 	 .conformanceTestLimit	= NO_CTL,
182814779705SSam Leffler 	 .dfsMask		= DFS_FCC3 | DFS_ETSI,
182914779705SSam Leffler 	 .pscan			= PSCAN_WWR,
183014779705SSam Leffler 	 .flags			= ADHOC_NO_11A,
183114779705SSam Leffler 	 .chan11a		= BM4(W1_5260_5320,
183214779705SSam Leffler 				      W1_5180_5240,
183314779705SSam Leffler 				      W1_5745_5825,
183414779705SSam Leffler 				      W1_5500_5700),
183514779705SSam Leffler 	 .chan11a_turbo		= BM3(WT1_5210_5250,
183614779705SSam Leffler 				      WT1_5290_5290,
183714779705SSam Leffler 				      WT1_5760_5800),
183814779705SSam Leffler 	 .chan11b		= BM5(W1_2412_2412,
183914779705SSam Leffler 				      W1_2437_2442,
184014779705SSam Leffler 				      W1_2462_2462,
184114779705SSam Leffler 				      W1_2417_2432,
184214779705SSam Leffler 				      W1_2447_2457),
184314779705SSam Leffler 	 .chan11g		= BM5(WG1_2412_2412,
184414779705SSam Leffler 				      WG1_2437_2442,
184514779705SSam Leffler 				      WG1_2462_2462,
184614779705SSam Leffler 				      WG1_2417_2432,
184714779705SSam Leffler 				      WG1_2447_2457),
184814779705SSam Leffler 	 .chan11g_turbo		= BM1(T3_2437_2437)},
184914779705SSam Leffler 
185014779705SSam Leffler 	{.regDmnEnum		= WORA_WORLD,
185114779705SSam Leffler 	 .conformanceTestLimit	= NO_CTL,
185214779705SSam Leffler 	 .dfsMask		= DFS_FCC3 | DFS_ETSI,
185314779705SSam Leffler 	 .pscan			= PSCAN_WWR,
185414779705SSam Leffler 	 .flags			= ADHOC_NO_11A,
185514779705SSam Leffler 	 .chan11a		= BM4(W1_5260_5320,
185614779705SSam Leffler 				      W1_5180_5240,
185714779705SSam Leffler 				      W1_5745_5825,
185814779705SSam Leffler 				      W1_5500_5700),
185914779705SSam Leffler 	 .chan11b		= BM7(W1_2412_2412,
186014779705SSam Leffler 				      W1_2437_2442,
186114779705SSam Leffler 				      W1_2462_2462,
186214779705SSam Leffler 				      W1_2472_2472,
186314779705SSam Leffler 				      W1_2417_2432,
186414779705SSam Leffler 				      W1_2447_2457,
186514779705SSam Leffler 				      W1_2467_2467),
186614779705SSam Leffler 	 .chan11g		= BM7(WG1_2412_2412,
186714779705SSam Leffler 				      WG1_2437_2442,
186814779705SSam Leffler 				      WG1_2462_2462,
186914779705SSam Leffler 				      WG1_2472_2472,
187014779705SSam Leffler 				      WG1_2417_2432,
187114779705SSam Leffler 				      WG1_2447_2457,
187214779705SSam Leffler 				      WG1_2467_2467),
187314779705SSam Leffler 	 .chan11g_turbo		= BM1(T3_2437_2437)},
187414779705SSam Leffler 
187514779705SSam Leffler 	{.regDmnEnum		= SR9_WORLD,
187614779705SSam Leffler 	 .conformanceTestLimit	= NO_CTL,
187714779705SSam Leffler 	 .pscan			= PSCAN_FCC | PSCAN_FCC_T,
187814779705SSam Leffler 	 .chan11g		= BM1(S1_912_917),
187914779705SSam Leffler 	 .chan11g_half		= BM1(S1_907_922_10),
188014779705SSam Leffler 	 .chan11g_quarter	= BM1(S1_907_922_5),
188114779705SSam Leffler 	},
188214779705SSam Leffler 
188314779705SSam Leffler 	{.regDmnEnum		= XR9_WORLD,
188414779705SSam Leffler 	 .conformanceTestLimit	= NO_CTL,
188514779705SSam Leffler 	 .pscan			= PSCAN_FCC | PSCAN_FCC_T,
188614779705SSam Leffler 	 .chan11g		= BM1(S2_912_917),
188714779705SSam Leffler 	 .chan11g_half		= BM1(S2_907_922_10),
188814779705SSam Leffler 	 .chan11g_quarter	= BM1(S2_907_922_5),
188914779705SSam Leffler 	},
189014779705SSam Leffler 
189114779705SSam Leffler 	{.regDmnEnum		= GZ901_WORLD,
189214779705SSam Leffler 	 .conformanceTestLimit	= NO_CTL,
189314779705SSam Leffler 	 .pscan			= PSCAN_FCC | PSCAN_FCC_T,
189414779705SSam Leffler 	 .chan11g		= BM1(S1_913_918),
189514779705SSam Leffler 	 .chan11g_half		= BM1(S1_913_918_10),
189614779705SSam Leffler 	 .chan11g_quarter	= BM1(S1_908_923_5),
189714779705SSam Leffler 	},
189814779705SSam Leffler 
189914779705SSam Leffler 	{.regDmnEnum		= NULL1,
190014779705SSam Leffler 	 .conformanceTestLimit	= NO_CTL,
190114779705SSam Leffler 	}
190214779705SSam Leffler };
190314779705SSam Leffler 
190414779705SSam Leffler struct cmode {
190514779705SSam Leffler 	u_int	mode;
190614779705SSam Leffler 	u_int	flags;
190714779705SSam Leffler };
190814779705SSam Leffler 
190914779705SSam Leffler static const struct cmode modes[] = {
191014779705SSam Leffler 	{ HAL_MODE_TURBO,	CHANNEL_ST},	/* NB: 11a Static Turbo */
191114779705SSam Leffler 	{ HAL_MODE_11A,		CHANNEL_A},
191214779705SSam Leffler 	{ HAL_MODE_11B,		CHANNEL_B},
191314779705SSam Leffler 	{ HAL_MODE_11G,		CHANNEL_G},
191414779705SSam Leffler 	{ HAL_MODE_11G_TURBO,	CHANNEL_108G},
191514779705SSam Leffler 	{ HAL_MODE_11A_TURBO,	CHANNEL_108A},
191614779705SSam Leffler 	{ HAL_MODE_11A_QUARTER_RATE,	CHANNEL_A | CHANNEL_QUARTER},
191714779705SSam Leffler 	{ HAL_MODE_11A_HALF_RATE,	CHANNEL_A | CHANNEL_HALF},
191814779705SSam Leffler 	{ HAL_MODE_11G_QUARTER_RATE,	CHANNEL_G | CHANNEL_QUARTER},
191914779705SSam Leffler 	{ HAL_MODE_11G_HALF_RATE,	CHANNEL_G | CHANNEL_HALF},
192014779705SSam Leffler 	{ HAL_MODE_11NG_HT20,	CHANNEL_G_HT20},
192114779705SSam Leffler 	{ HAL_MODE_11NG_HT40PLUS,	CHANNEL_G_HT40PLUS},
192214779705SSam Leffler 	{ HAL_MODE_11NG_HT40MINUS,	CHANNEL_G_HT40MINUS},
192314779705SSam Leffler 	{ HAL_MODE_11NA_HT20,	CHANNEL_A_HT20},
192414779705SSam Leffler 	{ HAL_MODE_11NA_HT40PLUS,	CHANNEL_A_HT40PLUS},
192514779705SSam Leffler 	{ HAL_MODE_11NA_HT40MINUS,	CHANNEL_A_HT40MINUS},
192614779705SSam Leffler };
192714779705SSam Leffler 
192814779705SSam Leffler static int
192914779705SSam Leffler chansort(const void *a, const void *b)
193014779705SSam Leffler {
193114779705SSam Leffler #define CHAN_FLAGS	(CHANNEL_ALL|CHANNEL_HALF|CHANNEL_QUARTER)
193214779705SSam Leffler 	const HAL_CHANNEL_INTERNAL *ca = a;
193314779705SSam Leffler 	const HAL_CHANNEL_INTERNAL *cb = b;
193414779705SSam Leffler 
193514779705SSam Leffler 	return (ca->channel == cb->channel) ?
193614779705SSam Leffler 		(ca->channelFlags & CHAN_FLAGS) -
193714779705SSam Leffler 			(cb->channelFlags & CHAN_FLAGS) :
193814779705SSam Leffler 		ca->channel - cb->channel;
193914779705SSam Leffler #undef CHAN_FLAGS
194014779705SSam Leffler }
194114779705SSam Leffler typedef int ath_hal_cmp_t(const void *, const void *);
194214779705SSam Leffler static	void ath_hal_sort(void *a, size_t n, size_t es, ath_hal_cmp_t *cmp);
194314779705SSam Leffler static COUNTRY_CODE_TO_ENUM_RD* findCountry(HAL_CTRY_CODE countryCode);
194414779705SSam Leffler static HAL_BOOL getWmRD(struct ath_hal *ah, COUNTRY_CODE_TO_ENUM_RD *country, uint16_t channelFlag, REG_DOMAIN *rd);
194514779705SSam Leffler 
194614779705SSam Leffler 
194714779705SSam Leffler static uint16_t
194814779705SSam Leffler getEepromRD(struct ath_hal *ah)
194914779705SSam Leffler {
195014779705SSam Leffler 	return AH_PRIVATE(ah)->ah_currentRD &~ WORLDWIDE_ROAMING_FLAG;
195114779705SSam Leffler }
195214779705SSam Leffler 
195314779705SSam Leffler /*
195414779705SSam Leffler  * Test to see if the bitmask array is all zeros
195514779705SSam Leffler  */
195614779705SSam Leffler static HAL_BOOL
195714779705SSam Leffler isChanBitMaskZero(const uint64_t *bitmask)
195814779705SSam Leffler {
195914779705SSam Leffler #if BMLEN > 2
196014779705SSam Leffler #error	"add more cases"
196114779705SSam Leffler #endif
196214779705SSam Leffler #if BMLEN > 1
196314779705SSam Leffler 	if (bitmask[1] != 0)
196414779705SSam Leffler 		return AH_FALSE;
196514779705SSam Leffler #endif
196614779705SSam Leffler 	return (bitmask[0] == 0);
196714779705SSam Leffler }
196814779705SSam Leffler 
196914779705SSam Leffler /*
197014779705SSam Leffler  * Return whether or not the regulatory domain/country in EEPROM
197114779705SSam Leffler  * is acceptable.
197214779705SSam Leffler  */
197314779705SSam Leffler static HAL_BOOL
197414779705SSam Leffler isEepromValid(struct ath_hal *ah)
197514779705SSam Leffler {
197614779705SSam Leffler 	uint16_t rd = getEepromRD(ah);
197714779705SSam Leffler 	int i;
197814779705SSam Leffler 
197914779705SSam Leffler 	if (rd & COUNTRY_ERD_FLAG) {
198014779705SSam Leffler 		uint16_t cc = rd &~ COUNTRY_ERD_FLAG;
198114779705SSam Leffler 		for (i = 0; i < N(allCountries); i++)
198214779705SSam Leffler 			if (allCountries[i].countryCode == cc)
198314779705SSam Leffler 				return AH_TRUE;
198414779705SSam Leffler 	} else {
198514779705SSam Leffler 		for (i = 0; i < N(regDomainPairs); i++)
198614779705SSam Leffler 			if (regDomainPairs[i].regDmnEnum == rd)
198714779705SSam Leffler 				return AH_TRUE;
198814779705SSam Leffler 	}
198914779705SSam Leffler 	HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
199014779705SSam Leffler 	    "%s: invalid regulatory domain/country code 0x%x\n", __func__, rd);
199114779705SSam Leffler 	return AH_FALSE;
199214779705SSam Leffler }
199314779705SSam Leffler 
199414779705SSam Leffler /*
199514779705SSam Leffler  * Returns whether or not the specified country code
199614779705SSam Leffler  * is allowed by the EEPROM setting
199714779705SSam Leffler  */
199814779705SSam Leffler static HAL_BOOL
199914779705SSam Leffler isCountryCodeValid(struct ath_hal *ah, HAL_CTRY_CODE cc)
200014779705SSam Leffler {
200114779705SSam Leffler 	uint16_t rd;
200214779705SSam Leffler 
200314779705SSam Leffler 	/* Default setting requires no checks */
200414779705SSam Leffler 	if (cc == CTRY_DEFAULT)
200514779705SSam Leffler 		return AH_TRUE;
200614779705SSam Leffler #ifdef AH_DEBUG_COUNTRY
200714779705SSam Leffler 	if (cc == CTRY_DEBUG)
200814779705SSam Leffler 		return AH_TRUE;
200914779705SSam Leffler #endif
201014779705SSam Leffler 	rd = getEepromRD(ah);
201114779705SSam Leffler 	HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, "%s: EEPROM regdomain 0x%x\n",
201214779705SSam Leffler 	    __func__, rd);
201314779705SSam Leffler 
201414779705SSam Leffler 	if (rd & COUNTRY_ERD_FLAG) {
201514779705SSam Leffler 		/* EEP setting is a country - config shall match */
201614779705SSam Leffler 		HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
201714779705SSam Leffler 		    "%s: EEPROM setting is country code %u\n", __func__,
201814779705SSam Leffler 		    rd &~ COUNTRY_ERD_FLAG);
201914779705SSam Leffler 		return (cc == (rd & ~COUNTRY_ERD_FLAG));
202014779705SSam Leffler 	} else if (rd == DEBUG_REG_DMN || rd == NO_ENUMRD) {
202114779705SSam Leffler 		/* Set to Debug or AllowAnyCountry mode - allow any setting */
202214779705SSam Leffler 		HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, "%s: rd %d allowed\n",
202314779705SSam Leffler 		    __func__, rd);
202414779705SSam Leffler 		return AH_TRUE;
202514779705SSam Leffler #ifdef AH_SUPPORT_11D
202614779705SSam Leffler 	} else	if ((rd & WORLD_SKU_MASK) == WORLD_SKU_PREFIX) {
202714779705SSam Leffler 		int i;
202814779705SSam Leffler 		for (i=0; i < N(allCountries); i++) {
202914779705SSam Leffler 			if (cc == allCountries[i].countryCode)
203014779705SSam Leffler 				return AH_TRUE;
203114779705SSam Leffler 		}
203214779705SSam Leffler #endif
203314779705SSam Leffler 	} else {
203414779705SSam Leffler 		int i;
203514779705SSam Leffler 		for (i = 0; i < N(allCountries); i++) {
203614779705SSam Leffler 			if (cc == allCountries[i].countryCode &&
203714779705SSam Leffler 			    allCountries[i].regDmnEnum == rd)
203814779705SSam Leffler 				return AH_TRUE;
203914779705SSam Leffler 		}
204014779705SSam Leffler 	}
204114779705SSam Leffler 	return AH_FALSE;
204214779705SSam Leffler }
204314779705SSam Leffler 
204414779705SSam Leffler /*
204514779705SSam Leffler  * Return the mask of available modes based on the hardware
204614779705SSam Leffler  * capabilities and the specified country code and reg domain.
204714779705SSam Leffler  */
204814779705SSam Leffler static u_int
204914779705SSam Leffler ath_hal_getwmodesnreg(struct ath_hal *ah,
205014779705SSam Leffler     const COUNTRY_CODE_TO_ENUM_RD *country, const REG_DOMAIN *rd5GHz)
205114779705SSam Leffler {
205214779705SSam Leffler #define	HAL_MODE_11G_ALL \
205314779705SSam Leffler 	(HAL_MODE_11G | HAL_MODE_11G_TURBO | HAL_MODE_11G_QUARTER_RATE | \
205414779705SSam Leffler 	 HAL_MODE_11G_HALF_RATE)
205514779705SSam Leffler #define	HAL_MODE_11A_ALL \
205614779705SSam Leffler 	(HAL_MODE_11A | HAL_MODE_11A_TURBO | HAL_MODE_TURBO | \
205714779705SSam Leffler 	 HAL_MODE_11A_QUARTER_RATE | HAL_MODE_11A_HALF_RATE)
205814779705SSam Leffler 	u_int modesAvail;
205914779705SSam Leffler 
206014779705SSam Leffler 	/* Get modes that HW is capable of */
206114779705SSam Leffler 	modesAvail = ath_hal_getWirelessModes(ah);
206214779705SSam Leffler 
206314779705SSam Leffler 	HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
206414779705SSam Leffler 	    "%s: wireless modes 0x%x cc %u rd %u\n",
206514779705SSam Leffler 	    __func__, modesAvail, country->countryCode, country->regDmnEnum);
206614779705SSam Leffler 
206714779705SSam Leffler 	/* Check country regulations for allowed modes */
206814779705SSam Leffler 	if (!country->allow11g && (modesAvail & HAL_MODE_11G_ALL)) {
206914779705SSam Leffler 		HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
207014779705SSam Leffler 		    "%s: disallow all 11g\n", __func__);
207114779705SSam Leffler 		modesAvail &= ~HAL_MODE_11G_ALL;
207214779705SSam Leffler 	}
207314779705SSam Leffler 	if (isChanBitMaskZero(rd5GHz->chan11a) &&
207414779705SSam Leffler 	    (modesAvail & HAL_MODE_11A_ALL)) {
207514779705SSam Leffler 		HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
207614779705SSam Leffler 		    "%s: disallow all 11a\n", __func__);
207714779705SSam Leffler 		modesAvail &= ~HAL_MODE_11A_ALL;
207814779705SSam Leffler 	}
207914779705SSam Leffler 	if ((modesAvail & (HAL_MODE_11A_TURBO | HAL_MODE_TURBO)) &&
208014779705SSam Leffler 	    !country->allow11aTurbo) {
208114779705SSam Leffler 		HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
208214779705SSam Leffler 		    "%s: disallow 11aTurbo\n", __func__);
208314779705SSam Leffler 		modesAvail &= ~(HAL_MODE_11A_TURBO | HAL_MODE_TURBO);
208414779705SSam Leffler 	}
208514779705SSam Leffler 	if ((modesAvail & HAL_MODE_11G_TURBO) && !country->allow11gTurbo) {
208614779705SSam Leffler 		HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
208714779705SSam Leffler 		    "%s: disallow 11gTurbo\n", __func__);
208814779705SSam Leffler 		modesAvail &= ~HAL_MODE_11G_TURBO;
208914779705SSam Leffler 	}
209014779705SSam Leffler 
209114779705SSam Leffler 	/* Check 11n operation */
209214779705SSam Leffler 	if ((modesAvail & HAL_MODE_11NG_HT20) && !country->allow11ng20) {
209314779705SSam Leffler 		HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
209414779705SSam Leffler 		    "%s: disallow 11g HT20\n", __func__);
209514779705SSam Leffler 		modesAvail &= ~HAL_MODE_11NG_HT20;
209614779705SSam Leffler 	}
209714779705SSam Leffler 	if ((modesAvail & HAL_MODE_11NA_HT20) && !country->allow11na20) {
209814779705SSam Leffler 		HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
209914779705SSam Leffler 		    "%s: disallow 11a HT20\n", __func__);
210014779705SSam Leffler 		modesAvail &= ~HAL_MODE_11NA_HT20;
210114779705SSam Leffler 	}
210214779705SSam Leffler 	if ((modesAvail & HAL_MODE_11NG_HT40PLUS) && !country->allow11ng40) {
210314779705SSam Leffler 		HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
210414779705SSam Leffler 		    "%s: disallow 11g HT40+\n", __func__);
210514779705SSam Leffler 		modesAvail &= ~HAL_MODE_11NG_HT40PLUS;
210614779705SSam Leffler 	}
210714779705SSam Leffler 	if ((modesAvail & HAL_MODE_11NG_HT40MINUS) && !country->allow11ng40) {
210814779705SSam Leffler 		HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
210914779705SSam Leffler 		    "%s: disallow 11g HT40-\n", __func__);
211014779705SSam Leffler 		modesAvail &= ~HAL_MODE_11NG_HT40MINUS;
211114779705SSam Leffler 	}
211214779705SSam Leffler 	if ((modesAvail & HAL_MODE_11NA_HT40PLUS) && !country->allow11na40) {
211314779705SSam Leffler 		HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
211414779705SSam Leffler 		    "%s: disallow 11a HT40+\n", __func__);
211514779705SSam Leffler 		modesAvail &= ~HAL_MODE_11NA_HT40PLUS;
211614779705SSam Leffler 	}
211714779705SSam Leffler 	if ((modesAvail & HAL_MODE_11NA_HT40MINUS) && !country->allow11na40) {
211814779705SSam Leffler 		HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
211914779705SSam Leffler 		    "%s: disallow 11a HT40-\n", __func__);
212014779705SSam Leffler 		modesAvail &= ~HAL_MODE_11NA_HT40MINUS;
212114779705SSam Leffler 	}
212214779705SSam Leffler 
212314779705SSam Leffler 	return modesAvail;
212414779705SSam Leffler #undef HAL_MODE_11A_ALL
212514779705SSam Leffler #undef HAL_MODE_11G_ALL
212614779705SSam Leffler }
212714779705SSam Leffler 
212814779705SSam Leffler /*
212914779705SSam Leffler  * Return the mask of available modes based on the hardware
213014779705SSam Leffler  * capabilities and the specified country code.
213114779705SSam Leffler  */
213214779705SSam Leffler 
213314779705SSam Leffler u_int
213414779705SSam Leffler ath_hal_getwirelessmodes(struct ath_hal *ah, HAL_CTRY_CODE cc)
213514779705SSam Leffler {
213614779705SSam Leffler 	COUNTRY_CODE_TO_ENUM_RD *country = AH_NULL;
213714779705SSam Leffler 	u_int mode = 0;
213814779705SSam Leffler 	REG_DOMAIN rd;
213914779705SSam Leffler 
214014779705SSam Leffler 	country = findCountry(cc);
214114779705SSam Leffler 	if (country != AH_NULL) {
214214779705SSam Leffler 		if (getWmRD(ah, country, ~CHANNEL_2GHZ, &rd))
214314779705SSam Leffler 			mode = ath_hal_getwmodesnreg(ah, country, &rd);
214414779705SSam Leffler 	}
214514779705SSam Leffler 	return mode;
214614779705SSam Leffler }
214714779705SSam Leffler 
214814779705SSam Leffler /*
214914779705SSam Leffler  * Return if device is public safety.
215014779705SSam Leffler  */
215114779705SSam Leffler HAL_BOOL
215214779705SSam Leffler ath_hal_ispublicsafetysku(struct ath_hal *ah)
215314779705SSam Leffler {
215414779705SSam Leffler 	uint16_t rd = getEepromRD(ah);
215514779705SSam Leffler 
215614779705SSam Leffler 	switch (rd) {
215714779705SSam Leffler 	case FCC4_FCCA:
215814779705SSam Leffler 	case CTRY_UNITED_STATES_FCC49 | COUNTRY_ERD_FLAG:
215914779705SSam Leffler 		return AH_TRUE;
216014779705SSam Leffler 	case DEBUG_REG_DMN:
216114779705SSam Leffler 	case NO_ENUMRD:
216214779705SSam Leffler 		if (AH_PRIVATE(ah)->ah_countryCode == CTRY_UNITED_STATES_FCC49)
216314779705SSam Leffler 			return AH_TRUE;
216414779705SSam Leffler 		break;
216514779705SSam Leffler 	}
216614779705SSam Leffler 	return AH_FALSE;
216714779705SSam Leffler }
216814779705SSam Leffler 
216914779705SSam Leffler /*
217014779705SSam Leffler  * Return if device is actually operating in 900 MHz band.
217114779705SSam Leffler  */
217214779705SSam Leffler HAL_BOOL
217314779705SSam Leffler ath_hal_isgsmsku(struct ath_hal *ah)
217414779705SSam Leffler {
217514779705SSam Leffler 	uint16_t rd = getEepromRD(ah);
217614779705SSam Leffler 
217714779705SSam Leffler 	switch (rd) {
217814779705SSam Leffler 	case SR9_WORLD:
217914779705SSam Leffler 	case XR9_WORLD:
218014779705SSam Leffler 	case GZ901_WORLD:
218114779705SSam Leffler 	case CTRY_SR9 | COUNTRY_ERD_FLAG:
218214779705SSam Leffler 	case CTRY_XR9 | COUNTRY_ERD_FLAG:
218314779705SSam Leffler 	case CTRY_GZ901 | COUNTRY_ERD_FLAG:
218414779705SSam Leffler 		return AH_TRUE;
218514779705SSam Leffler 	case DEBUG_REG_DMN:
218614779705SSam Leffler 	case NO_ENUMRD:
218714779705SSam Leffler 		return AH_PRIVATE(ah)->ah_countryCode == CTRY_SR9
218814779705SSam Leffler 		       || AH_PRIVATE(ah)->ah_countryCode == CTRY_XR9
218914779705SSam Leffler 		       || AH_PRIVATE(ah)->ah_countryCode == CTRY_GZ901
219014779705SSam Leffler 		       ;
219114779705SSam Leffler 	}
219214779705SSam Leffler 	return AH_FALSE;
219314779705SSam Leffler }
219414779705SSam Leffler 
219514779705SSam Leffler /*
219614779705SSam Leffler  * Find the pointer to the country element in the country table
219714779705SSam Leffler  * corresponding to the country code
219814779705SSam Leffler  */
219914779705SSam Leffler static COUNTRY_CODE_TO_ENUM_RD*
220014779705SSam Leffler findCountry(HAL_CTRY_CODE countryCode)
220114779705SSam Leffler {
220214779705SSam Leffler 	int i;
220314779705SSam Leffler 
220414779705SSam Leffler 	for (i = 0; i < N(allCountries); i++) {
220514779705SSam Leffler 		if (allCountries[i].countryCode == countryCode)
220614779705SSam Leffler 			return &allCountries[i];
220714779705SSam Leffler 	}
220814779705SSam Leffler 	return AH_NULL;		/* Not found */
220914779705SSam Leffler }
221014779705SSam Leffler 
221114779705SSam Leffler /*
221214779705SSam Leffler  * Calculate a default country based on the EEPROM setting.
221314779705SSam Leffler  */
221414779705SSam Leffler static HAL_CTRY_CODE
221514779705SSam Leffler getDefaultCountry(struct ath_hal *ah)
221614779705SSam Leffler {
221714779705SSam Leffler 	uint16_t rd;
221814779705SSam Leffler 	int i;
221914779705SSam Leffler 
222014779705SSam Leffler 	rd = getEepromRD(ah);
222114779705SSam Leffler 	if (rd & COUNTRY_ERD_FLAG) {
222214779705SSam Leffler 		COUNTRY_CODE_TO_ENUM_RD *country = AH_NULL;
222314779705SSam Leffler 		uint16_t cc = rd & ~COUNTRY_ERD_FLAG;
222414779705SSam Leffler 
222514779705SSam Leffler 		country = findCountry(cc);
222614779705SSam Leffler 		if (country != AH_NULL)
222714779705SSam Leffler 			return cc;
222814779705SSam Leffler 	}
222914779705SSam Leffler 	/*
223014779705SSam Leffler 	 * Check reg domains that have only one country
223114779705SSam Leffler 	 */
223214779705SSam Leffler 	for (i = 0; i < N(regDomainPairs); i++)
223314779705SSam Leffler 		if (regDomainPairs[i].regDmnEnum == rd) {
223414779705SSam Leffler 			if (regDomainPairs[i].singleCC != 0)
223514779705SSam Leffler 				return regDomainPairs[i].singleCC;
223614779705SSam Leffler 			else
223714779705SSam Leffler 				i = N(regDomainPairs);
223814779705SSam Leffler 		}
223914779705SSam Leffler 	return CTRY_DEFAULT;
224014779705SSam Leffler }
224114779705SSam Leffler 
224214779705SSam Leffler static HAL_BOOL
224314779705SSam Leffler isValidRegDmn(int regDmn, REG_DOMAIN *rd)
224414779705SSam Leffler {
224514779705SSam Leffler 	int i;
224614779705SSam Leffler 
224714779705SSam Leffler 	for (i = 0; i < N(regDomains); i++) {
224814779705SSam Leffler 		if (regDomains[i].regDmnEnum == regDmn) {
224914779705SSam Leffler 			if (rd != AH_NULL) {
225014779705SSam Leffler 				OS_MEMCPY(rd, &regDomains[i],
225114779705SSam Leffler 					  sizeof(REG_DOMAIN));
225214779705SSam Leffler 			}
225314779705SSam Leffler 			return AH_TRUE;
225414779705SSam Leffler 		}
225514779705SSam Leffler 	}
225614779705SSam Leffler 	return AH_FALSE;
225714779705SSam Leffler }
225814779705SSam Leffler 
225914779705SSam Leffler static HAL_BOOL
226014779705SSam Leffler isValidRegDmnPair(int regDmnPair)
226114779705SSam Leffler {
226214779705SSam Leffler 	int i;
226314779705SSam Leffler 
226414779705SSam Leffler 	if (regDmnPair == NO_ENUMRD)
226514779705SSam Leffler 		return AH_FALSE;
226614779705SSam Leffler 	for (i = 0; i < N(regDomainPairs); i++) {
226714779705SSam Leffler 		if (regDomainPairs[i].regDmnEnum == regDmnPair)
226814779705SSam Leffler 			return AH_TRUE;
226914779705SSam Leffler 	}
227014779705SSam Leffler 	return AH_FALSE;
227114779705SSam Leffler }
227214779705SSam Leffler 
227314779705SSam Leffler /*
227414779705SSam Leffler  * Return the Wireless Mode Regulatory Domain based
227514779705SSam Leffler  * on the country code and the wireless mode.
227614779705SSam Leffler  */
227714779705SSam Leffler static HAL_BOOL
227814779705SSam Leffler getWmRD(struct ath_hal *ah, COUNTRY_CODE_TO_ENUM_RD *country,
227914779705SSam Leffler 	uint16_t channelFlag, REG_DOMAIN *rd)
228014779705SSam Leffler {
228114779705SSam Leffler 	int regDmn;
228214779705SSam Leffler 	REG_DMN_PAIR_MAPPING *regPair;
228314779705SSam Leffler 	uint64_t flags;
228414779705SSam Leffler 
228514779705SSam Leffler 	if (country->countryCode == CTRY_DEFAULT) {
228614779705SSam Leffler 		uint16_t rdnum = getEepromRD(ah);
228714779705SSam Leffler 
228814779705SSam Leffler 		if ((rdnum & COUNTRY_ERD_FLAG) == 0) {
228914779705SSam Leffler 			if (isValidRegDmn(rdnum, AH_NULL) ||
229014779705SSam Leffler 			    isValidRegDmnPair(rdnum))
229114779705SSam Leffler 				regDmn = rdnum;
229214779705SSam Leffler 			else
229314779705SSam Leffler 				regDmn = country->regDmnEnum;
229414779705SSam Leffler 		} else
229514779705SSam Leffler 			regDmn = country->regDmnEnum;
229614779705SSam Leffler 	} else
229714779705SSam Leffler 		regDmn = country->regDmnEnum;
229814779705SSam Leffler 	regPair = AH_NULL;
229914779705SSam Leffler 	flags = NO_REQ;
230014779705SSam Leffler 	if ((regDmn & MULTI_DOMAIN_MASK) == 0) {
230114779705SSam Leffler 		int i;
230214779705SSam Leffler 
230314779705SSam Leffler 		for (i = 0; i < N(regDomainPairs); i++) {
230414779705SSam Leffler 			if (regDomainPairs[i].regDmnEnum == regDmn) {
230514779705SSam Leffler 				regPair = &regDomainPairs[i];
230614779705SSam Leffler 				break;
230714779705SSam Leffler 			}
230814779705SSam Leffler 		}
230914779705SSam Leffler 		if (regPair == AH_NULL) {
231014779705SSam Leffler 			HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
231114779705SSam Leffler 			    "%s: Failed to find reg domain pair %u\n",
231214779705SSam Leffler 			    __func__, regDmn);
231314779705SSam Leffler 			return AH_FALSE;
231414779705SSam Leffler 		}
231514779705SSam Leffler 		if (channelFlag & CHANNEL_2GHZ) {
231614779705SSam Leffler 			regDmn = regPair->regDmn2GHz;
231714779705SSam Leffler 			flags = regPair->flags2GHz;
231814779705SSam Leffler 		} else {
231914779705SSam Leffler 			regDmn = regPair->regDmn5GHz;
232014779705SSam Leffler 			flags = regPair->flags5GHz;
232114779705SSam Leffler 		}
232214779705SSam Leffler 	}
232314779705SSam Leffler 
232414779705SSam Leffler 	/*
232514779705SSam Leffler 	 * We either started with a unitary reg domain or we've found the
232614779705SSam Leffler 	 * unitary reg domain of the pair
232714779705SSam Leffler 	 */
232814779705SSam Leffler 	if (isValidRegDmn(regDmn, rd)) {
232914779705SSam Leffler 		if (regPair != AH_NULL)
233014779705SSam Leffler 			rd->pscan &= regPair->pscanMask;
233114779705SSam Leffler 		if ((country->regDmnEnum & MULTI_DOMAIN_MASK) == 0 &&
233214779705SSam Leffler 		    flags != NO_REQ)
233314779705SSam Leffler 			rd->flags = flags;
233414779705SSam Leffler 		return AH_TRUE;
233514779705SSam Leffler 	} else {
233614779705SSam Leffler 		HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
233714779705SSam Leffler 		    "%s: Failed to find unitary reg domain %u\n", __func__,
233814779705SSam Leffler 		    country->regDmnEnum);
233914779705SSam Leffler 		return AH_FALSE;
234014779705SSam Leffler 	}
234114779705SSam Leffler }
234214779705SSam Leffler 
234314779705SSam Leffler static HAL_BOOL
234414779705SSam Leffler IS_BIT_SET(int bit, const uint64_t bitmask[])
234514779705SSam Leffler {
234614779705SSam Leffler 	int byteOffset, bitnum;
234714779705SSam Leffler 	uint64_t val;
234814779705SSam Leffler 
234914779705SSam Leffler 	byteOffset = bit/64;
235014779705SSam Leffler 	bitnum = bit - byteOffset*64;
235114779705SSam Leffler 	val = ((uint64_t) 1) << bitnum;
235214779705SSam Leffler 	return (bitmask[byteOffset] & val) != 0;
235314779705SSam Leffler }
235414779705SSam Leffler 
235514779705SSam Leffler /* Add given regclassid into regclassids array upto max of maxregids */
235614779705SSam Leffler static void
235714779705SSam Leffler ath_add_regclassid(uint8_t *regclassids, u_int maxregids,
235814779705SSam Leffler 	u_int *nregids, uint8_t regclassid)
235914779705SSam Leffler {
236014779705SSam Leffler 	int i;
236114779705SSam Leffler 
236214779705SSam Leffler 	/* Is regclassid valid? */
236314779705SSam Leffler 	if (regclassid == 0)
236414779705SSam Leffler 		return;
236514779705SSam Leffler 
236614779705SSam Leffler 	for (i = 0; i < maxregids; i++) {
236714779705SSam Leffler 		if (regclassids[i] == regclassid)	/* already present */
236814779705SSam Leffler 			return;
236914779705SSam Leffler 		if (regclassids[i] == 0) {		/* free slot */
237014779705SSam Leffler 			regclassids[i] = regclassid;
237114779705SSam Leffler 			(*nregids)++;
237214779705SSam Leffler 			return;
237314779705SSam Leffler 		}
237414779705SSam Leffler 	}
237514779705SSam Leffler }
237614779705SSam Leffler 
237714779705SSam Leffler /*
237814779705SSam Leffler  * Setup the channel list based on the information in the EEPROM and
237914779705SSam Leffler  * any supplied country code.  Note that we also do a bunch of EEPROM
238014779705SSam Leffler  * verification here and setup certain regulatory-related access
238114779705SSam Leffler  * control data used later on.
238214779705SSam Leffler  */
238314779705SSam Leffler 
238414779705SSam Leffler HAL_BOOL
238514779705SSam Leffler ath_hal_init_channels(struct ath_hal *ah,
238614779705SSam Leffler 		      HAL_CHANNEL *chans, u_int maxchans, u_int *nchans,
238714779705SSam Leffler 		      uint8_t *regclassids, u_int maxregids, u_int *nregids,
238814779705SSam Leffler 		      HAL_CTRY_CODE cc, u_int modeSelect,
238914779705SSam Leffler 		      HAL_BOOL enableOutdoor, HAL_BOOL enableExtendedChannels)
239014779705SSam Leffler {
239114779705SSam Leffler #define CHANNEL_HALF_BW		10
239214779705SSam Leffler #define CHANNEL_QUARTER_BW	5
239314779705SSam Leffler 	u_int modesAvail;
239414779705SSam Leffler 	uint16_t maxChan;
239514779705SSam Leffler 	COUNTRY_CODE_TO_ENUM_RD *country = AH_NULL;
239614779705SSam Leffler 	REG_DOMAIN rd5GHz, rd2GHz;
239714779705SSam Leffler 	const struct cmode *cm;
239814779705SSam Leffler 	HAL_CHANNEL_INTERNAL *ichans = &AH_PRIVATE(ah)->ah_channels[0];
239914779705SSam Leffler 	int next, b;
240014779705SSam Leffler 	uint8_t ctl;
240114779705SSam Leffler 
240214779705SSam Leffler 	HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, "%s: cc %u mode 0x%x%s%s\n",
240314779705SSam Leffler 	    __func__, cc, modeSelect, enableOutdoor? " Enable outdoor" : " ",
240414779705SSam Leffler 	    enableExtendedChannels ? " Enable ecm" : "");
240514779705SSam Leffler 
240614779705SSam Leffler 	/*
240714779705SSam Leffler 	 * Validate the EEPROM setting and setup defaults
240814779705SSam Leffler 	 */
240914779705SSam Leffler 	if (!isEepromValid(ah)) {
241014779705SSam Leffler 		/*
241114779705SSam Leffler 		 * Don't return any channels if the EEPROM has an
241214779705SSam Leffler 		 * invalid regulatory domain/country code setting.
241314779705SSam Leffler 		 */
241414779705SSam Leffler 		HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
241514779705SSam Leffler 		    "%s: invalid EEPROM contents\n",__func__);
241614779705SSam Leffler 		return AH_FALSE;
241714779705SSam Leffler 	}
241814779705SSam Leffler 
241914779705SSam Leffler 	AH_PRIVATE(ah)->ah_countryCode = getDefaultCountry(ah);
242014779705SSam Leffler 
242114779705SSam Leffler #ifndef AH_SUPPORT_11D
242214779705SSam Leffler 	if (AH_PRIVATE(ah)->ah_countryCode == CTRY_DEFAULT) {
242314779705SSam Leffler #endif
242414779705SSam Leffler 		/*
242514779705SSam Leffler 		 * We now have enough state to validate any country code
242614779705SSam Leffler 		 * passed in by the caller.
242714779705SSam Leffler 		 */
242814779705SSam Leffler 		if (!isCountryCodeValid(ah, cc)) {
242914779705SSam Leffler 			/* NB: Atheros silently ignores invalid country codes */
243014779705SSam Leffler 			HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
243114779705SSam Leffler 			    "%s: invalid country code %d\n", __func__, cc);
243214779705SSam Leffler 			return AH_FALSE;
243314779705SSam Leffler 		}
243414779705SSam Leffler 		AH_PRIVATE(ah)->ah_countryCode = cc & COUNTRY_CODE_MASK;
243514779705SSam Leffler #ifndef AH_SUPPORT_11D
243614779705SSam Leffler 	}
243714779705SSam Leffler #endif
243814779705SSam Leffler 
243914779705SSam Leffler 	/* Get pointers to the country element and the reg domain elements */
244014779705SSam Leffler 	country = findCountry(AH_PRIVATE(ah)->ah_countryCode);
244114779705SSam Leffler 
244214779705SSam Leffler 	if (country == AH_NULL) {
244314779705SSam Leffler 		HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, "NULL Country!, cc= %d\n",
244414779705SSam Leffler 		    AH_PRIVATE(ah)->ah_countryCode);
244514779705SSam Leffler 		return AH_FALSE;
244614779705SSam Leffler 	}
244714779705SSam Leffler 
244814779705SSam Leffler 	if (!getWmRD(ah, country, ~CHANNEL_2GHZ, &rd5GHz)) {
244914779705SSam Leffler 		HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
245014779705SSam Leffler 		    "%s: no unitary 5GHz regdomain for country %u\n",
245114779705SSam Leffler 		     __func__, AH_PRIVATE(ah)->ah_countryCode);
245214779705SSam Leffler 		return AH_FALSE;
245314779705SSam Leffler 	}
245414779705SSam Leffler 	if (!getWmRD(ah, country, CHANNEL_2GHZ, &rd2GHz)) {
245514779705SSam Leffler 		HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
245614779705SSam Leffler 		    "%s: no unitary 2GHz regdomain for country %u\n",
245714779705SSam Leffler 		    __func__, AH_PRIVATE(ah)->ah_countryCode);
245814779705SSam Leffler 		return AH_FALSE;
245914779705SSam Leffler 	}
246014779705SSam Leffler 
246114779705SSam Leffler 	modesAvail = ath_hal_getwmodesnreg(ah, country, &rd5GHz);
246214779705SSam Leffler 	maxChan = !enableOutdoor ? country->outdoorChanStart : 7000;
246314779705SSam Leffler 
246414779705SSam Leffler 	if (maxchans > N(AH_PRIVATE(ah)->ah_channels))
246514779705SSam Leffler 		maxchans = N(AH_PRIVATE(ah)->ah_channels);
246614779705SSam Leffler 	next = 0;
246714779705SSam Leffler 	for (cm = modes; cm < &modes[N(modes)]; cm++) {
246814779705SSam Leffler 		uint16_t c, c_hi, c_lo;
246914779705SSam Leffler 		uint64_t *channelBM = AH_NULL;
247014779705SSam Leffler 		REG_DOMAIN *rd = AH_NULL;
247114779705SSam Leffler 		REG_DMN_FREQ_BAND *fband = AH_NULL,*freqs;
247214779705SSam Leffler 		int low_adj, hi_adj, channelSep, lastc;
247314779705SSam Leffler 
247414779705SSam Leffler 		if ((cm->mode & modeSelect) == 0) {
247514779705SSam Leffler 			HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
247614779705SSam Leffler 			    "%s: skip mode 0x%x flags 0x%x\n",
247714779705SSam Leffler 			    __func__, cm->mode, cm->flags);
247814779705SSam Leffler 			continue;
247914779705SSam Leffler 		}
248014779705SSam Leffler 		if ((cm->mode & modesAvail) == 0) {
248114779705SSam Leffler 			HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
248214779705SSam Leffler 			    "%s: !avail mode 0x%x (0x%x) flags 0x%x\n",
248314779705SSam Leffler 			    __func__, modesAvail, cm->mode, cm->flags);
248414779705SSam Leffler 			continue;
248514779705SSam Leffler 		}
248614779705SSam Leffler 		if (!ath_hal_getChannelEdges(ah, cm->flags, &c_lo, &c_hi)) {
248714779705SSam Leffler 			/* channel not supported by hardware, skip it */
248814779705SSam Leffler 			HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
248914779705SSam Leffler 			    "%s: channels 0x%x not supported by hardware\n",
249014779705SSam Leffler 			    __func__,cm->flags);
249114779705SSam Leffler 			continue;
249214779705SSam Leffler 		}
249314779705SSam Leffler 		switch (cm->mode) {
249414779705SSam Leffler 		case HAL_MODE_TURBO:
249514779705SSam Leffler 			rd = &rd5GHz;
249614779705SSam Leffler 			channelBM = rd->chan11a_turbo;
249714779705SSam Leffler 			freqs = &regDmn5GhzTurboFreq[0];
249814779705SSam Leffler 			ctl = rd->conformanceTestLimit | CTL_TURBO;
249914779705SSam Leffler 			break;
250014779705SSam Leffler 		case HAL_MODE_11A:
250114779705SSam Leffler 		case HAL_MODE_11A_HALF_RATE:
250214779705SSam Leffler 		case HAL_MODE_11A_QUARTER_RATE:
250314779705SSam Leffler 		case HAL_MODE_11NA_HT20:
250414779705SSam Leffler 		case HAL_MODE_11NA_HT40PLUS:
250514779705SSam Leffler 		case HAL_MODE_11NA_HT40MINUS:
250614779705SSam Leffler 			rd = &rd5GHz;
250714779705SSam Leffler 			if (cm->mode == HAL_MODE_11A_HALF_RATE)
250814779705SSam Leffler 				channelBM = rd->chan11a_half;
250914779705SSam Leffler 			else if (cm->mode == HAL_MODE_11A_QUARTER_RATE)
251014779705SSam Leffler 				channelBM = rd->chan11a_quarter;
251114779705SSam Leffler 			else
251214779705SSam Leffler 				channelBM = rd->chan11a;
251314779705SSam Leffler 			freqs = &regDmn5GhzFreq[0];
251414779705SSam Leffler 			ctl = rd->conformanceTestLimit;
251514779705SSam Leffler 			break;
251614779705SSam Leffler 		case HAL_MODE_11B:
251714779705SSam Leffler 			rd = &rd2GHz;
251814779705SSam Leffler 			channelBM = rd->chan11b;
251914779705SSam Leffler 			freqs = &regDmn2GhzFreq[0];
252014779705SSam Leffler 			ctl = rd->conformanceTestLimit | CTL_11B;
252114779705SSam Leffler 			break;
252214779705SSam Leffler 		case HAL_MODE_11G:
252314779705SSam Leffler 		case HAL_MODE_11G_HALF_RATE:
252414779705SSam Leffler 		case HAL_MODE_11G_QUARTER_RATE:
252514779705SSam Leffler 		case HAL_MODE_11NG_HT20:
252614779705SSam Leffler 		case HAL_MODE_11NG_HT40PLUS:
252714779705SSam Leffler 		case HAL_MODE_11NG_HT40MINUS:
252814779705SSam Leffler 			rd = &rd2GHz;
252914779705SSam Leffler 			if (cm->mode == HAL_MODE_11G_HALF_RATE)
253014779705SSam Leffler 				channelBM = rd->chan11g_half;
253114779705SSam Leffler 			else if (cm->mode == HAL_MODE_11G_QUARTER_RATE)
253214779705SSam Leffler 				channelBM = rd->chan11g_quarter;
253314779705SSam Leffler 			else
253414779705SSam Leffler 				channelBM = rd->chan11g;
253514779705SSam Leffler 			freqs = &regDmn2Ghz11gFreq[0];
253614779705SSam Leffler 			ctl = rd->conformanceTestLimit | CTL_11G;
253714779705SSam Leffler 			break;
253814779705SSam Leffler 		case HAL_MODE_11G_TURBO:
253914779705SSam Leffler 			rd = &rd2GHz;
254014779705SSam Leffler 			channelBM = rd->chan11g_turbo;
254114779705SSam Leffler 			freqs = &regDmn2Ghz11gTurboFreq[0];
254214779705SSam Leffler 			ctl = rd->conformanceTestLimit | CTL_108G;
254314779705SSam Leffler 			break;
254414779705SSam Leffler 		case HAL_MODE_11A_TURBO:
254514779705SSam Leffler 			rd = &rd5GHz;
254614779705SSam Leffler 			channelBM = rd->chan11a_dyn_turbo;
254714779705SSam Leffler 			freqs = &regDmn5GhzTurboFreq[0];
254814779705SSam Leffler 			ctl = rd->conformanceTestLimit | CTL_108G;
254914779705SSam Leffler 			break;
255014779705SSam Leffler 		default:
255114779705SSam Leffler 			HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
255214779705SSam Leffler 			    "%s: Unkonwn HAL mode 0x%x\n", __func__, cm->mode);
255314779705SSam Leffler 			continue;
255414779705SSam Leffler 		}
255514779705SSam Leffler 		if (isChanBitMaskZero(channelBM))
255614779705SSam Leffler 			continue;
255714779705SSam Leffler 		/*
255814779705SSam Leffler 		 * Setup special handling for HT40 channels; e.g.
255914779705SSam Leffler 		 * 5G HT40 channels require 40Mhz channel separation.
256014779705SSam Leffler 		 */
256114779705SSam Leffler 		hi_adj = (cm->mode == HAL_MODE_11NA_HT40PLUS ||
256214779705SSam Leffler 		    cm->mode == HAL_MODE_11NG_HT40PLUS) ? -20 : 0;
256314779705SSam Leffler 		low_adj = (cm->mode == HAL_MODE_11NA_HT40MINUS ||
256414779705SSam Leffler 		    cm->mode == HAL_MODE_11NG_HT40MINUS) ? 20 : 0;
256514779705SSam Leffler 		channelSep = (cm->mode == HAL_MODE_11NA_HT40PLUS ||
256614779705SSam Leffler 		    cm->mode == HAL_MODE_11NA_HT40MINUS) ? 40 : 0;
256714779705SSam Leffler 
256814779705SSam Leffler 		for (b = 0; b < 64*BMLEN; b++) {
256914779705SSam Leffler 			if (!IS_BIT_SET(b, channelBM))
257014779705SSam Leffler 				continue;
257114779705SSam Leffler 			fband = &freqs[b];
257214779705SSam Leffler 			lastc = 0;
257314779705SSam Leffler 
257414779705SSam Leffler 			ath_add_regclassid(regclassids, maxregids,
257514779705SSam Leffler 					nregids, fband->regClassId);
257614779705SSam Leffler 
257714779705SSam Leffler 			for (c = fband->lowChannel + low_adj;
257814779705SSam Leffler 			     c <= fband->highChannel + hi_adj;
257914779705SSam Leffler 			     c += fband->channelSep) {
258014779705SSam Leffler 				HAL_CHANNEL_INTERNAL icv;
258114779705SSam Leffler 
258214779705SSam Leffler 				if (!(c_lo <= c && c <= c_hi)) {
258314779705SSam Leffler 					HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
258414779705SSam Leffler 					    "%s: c %u out of range [%u..%u]\n",
258514779705SSam Leffler 					    __func__, c, c_lo, c_hi);
258614779705SSam Leffler 					continue;
258714779705SSam Leffler 				}
258814779705SSam Leffler 				if (((c+fband->channelSep)/2) > (maxChan+HALF_MAXCHANBW)) {
258914779705SSam Leffler 					HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
259014779705SSam Leffler 					    "%s: c %u > maxChan %u\n",
259114779705SSam Leffler 					    __func__, c, maxChan);
259214779705SSam Leffler 					continue;
259314779705SSam Leffler 				}
259414779705SSam Leffler 				if (next >= maxchans){
259514779705SSam Leffler 					HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
259614779705SSam Leffler 					    "%s: too many channels for channel table\n",
259714779705SSam Leffler 					    __func__);
259814779705SSam Leffler 					goto done;
259914779705SSam Leffler 				}
260014779705SSam Leffler 				if ((fband->usePassScan & IS_ECM_CHAN) &&
260114779705SSam Leffler 				    !enableExtendedChannels) {
260214779705SSam Leffler 					HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
260314779705SSam Leffler 					    "Skipping ecm channel\n");
260414779705SSam Leffler 					continue;
260514779705SSam Leffler 				}
260614779705SSam Leffler 				/* XXX needs to be in ath_hal_checkchannel */
260714779705SSam Leffler 				if ((rd->flags & NO_HOSTAP) &&
260814779705SSam Leffler 				    (AH_PRIVATE(ah)->ah_opmode == HAL_M_HOSTAP)) {
260914779705SSam Leffler 					HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
261014779705SSam Leffler 					    "Skipping HOSTAP channel\n");
261114779705SSam Leffler 					continue;
261214779705SSam Leffler 				}
261314779705SSam Leffler 				/*
261414779705SSam Leffler 				 * Make sure that channel separation
261514779705SSam Leffler 				 * meets the requirement.
261614779705SSam Leffler 				 */
261714779705SSam Leffler 				if (lastc && channelSep &&
261814779705SSam Leffler 				    (c-lastc) < channelSep)
261914779705SSam Leffler 					continue;
262014779705SSam Leffler 
262114779705SSam Leffler 				OS_MEMZERO(&icv, sizeof(icv));
262214779705SSam Leffler 				icv.channel = c;
262314779705SSam Leffler 				icv.channelFlags = cm->flags;
262414779705SSam Leffler 				icv.maxRegTxPower = fband->powerDfs;
262514779705SSam Leffler 				icv.antennaMax = fband->antennaMax;
262614779705SSam Leffler 				icv.regDmnFlags = rd->flags;
262714779705SSam Leffler 				icv.conformanceTestLimit = ctl;
262814779705SSam Leffler 				if (fband->usePassScan & rd->pscan)
262914779705SSam Leffler 					icv.channelFlags |= CHANNEL_PASSIVE;
263014779705SSam Leffler 				else
263114779705SSam Leffler 					icv.channelFlags &= ~CHANNEL_PASSIVE;
263214779705SSam Leffler 				lastc = c;
263314779705SSam Leffler 				if (fband->useDfs & rd->dfsMask) {
263414779705SSam Leffler 					/* DFS and HT40 don't mix */
263514779705SSam Leffler 					if (cm->mode == HAL_MODE_11NA_HT40PLUS ||
263614779705SSam Leffler 					    cm->mode == HAL_MODE_11NA_HT40MINUS)
263714779705SSam Leffler 						continue;
263814779705SSam Leffler 					icv.privFlags = CHANNEL_DFS;
263914779705SSam Leffler 				} else
264014779705SSam Leffler 					icv.privFlags = 0;
264114779705SSam Leffler 				if (rd->flags & LIMIT_FRAME_4MS)
264214779705SSam Leffler 					icv.privFlags |= CHANNEL_4MS_LIMIT;
264314779705SSam Leffler 
264414779705SSam Leffler 				ichans[next++] = icv;
264514779705SSam Leffler 			}
264614779705SSam Leffler 		}
264714779705SSam Leffler 	}
264814779705SSam Leffler done:
264914779705SSam Leffler 	if (next != 0) {
265014779705SSam Leffler 		int i;
265114779705SSam Leffler 
265214779705SSam Leffler 		/* XXX maxchans set above so this cannot happen? */
265314779705SSam Leffler 		if (next > N(AH_PRIVATE(ah)->ah_channels)) {
265414779705SSam Leffler 			HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
265514779705SSam Leffler 			    "%s: too many channels %u; truncating to %u\n",
265614779705SSam Leffler 			    __func__, next,
265714779705SSam Leffler 			    (int) N(AH_PRIVATE(ah)->ah_channels));
265814779705SSam Leffler 			next = N(AH_PRIVATE(ah)->ah_channels);
265914779705SSam Leffler 		}
266014779705SSam Leffler 
266114779705SSam Leffler 		/*
266214779705SSam Leffler 		 * Keep a private copy of the channel list so we can
266314779705SSam Leffler 		 * constrain future requests to only these channels
266414779705SSam Leffler 		 */
266514779705SSam Leffler 		ath_hal_sort(ichans, next, sizeof(HAL_CHANNEL_INTERNAL),
266614779705SSam Leffler 		    chansort);
266714779705SSam Leffler 		AH_PRIVATE(ah)->ah_nchan = next;
266814779705SSam Leffler 
266914779705SSam Leffler 		/*
267014779705SSam Leffler 		 * Copy the channel list to the public channel list
267114779705SSam Leffler 		 */
267214779705SSam Leffler 		for (i = 0; i < next; i++) {
267314779705SSam Leffler 			chans[i].channel = ichans[i].channel;
267414779705SSam Leffler 			chans[i].channelFlags = ichans[i].channelFlags;
267514779705SSam Leffler 			chans[i].privFlags = ichans[i].privFlags;
267614779705SSam Leffler 			chans[i].maxRegTxPower = ichans[i].maxRegTxPower;
267714779705SSam Leffler 		}
267814779705SSam Leffler 		/*
267914779705SSam Leffler 		 * Retrieve power limits.
268014779705SSam Leffler 		 */
268114779705SSam Leffler 		ath_hal_getpowerlimits(ah, chans, next);
268214779705SSam Leffler 		for (i = 0; i < next; i++) {
268314779705SSam Leffler 			ichans[i].maxTxPower = chans[i].maxTxPower;
268414779705SSam Leffler 			ichans[i].minTxPower = chans[i].minTxPower;
268514779705SSam Leffler 		}
268614779705SSam Leffler 	}
268714779705SSam Leffler 	*nchans = next;
268814779705SSam Leffler 	/* XXX copy private setting to public area */
268914779705SSam Leffler 	ah->ah_countryCode = AH_PRIVATE(ah)->ah_countryCode;
269014779705SSam Leffler 	return (next != 0);
269114779705SSam Leffler #undef CHANNEL_HALF_BW
269214779705SSam Leffler #undef CHANNEL_QUARTER_BW
269314779705SSam Leffler }
269414779705SSam Leffler 
269514779705SSam Leffler /*
269614779705SSam Leffler  * Return whether or not the specified channel is ok to use
269714779705SSam Leffler  * based on the current regulatory domain constraints and
269814779705SSam Leffler  * DFS interference.
269914779705SSam Leffler  */
270014779705SSam Leffler HAL_CHANNEL_INTERNAL *
270114779705SSam Leffler ath_hal_checkchannel(struct ath_hal *ah, const HAL_CHANNEL *c)
270214779705SSam Leffler {
270314779705SSam Leffler #define CHAN_FLAGS	(CHANNEL_ALL|CHANNEL_HALF|CHANNEL_QUARTER)
270414779705SSam Leffler 	HAL_CHANNEL_INTERNAL *base, *cc;
270514779705SSam Leffler 	/* NB: be wary of user-specified channel flags */
270614779705SSam Leffler 	int flags = c->channelFlags & CHAN_FLAGS;
270714779705SSam Leffler 	int n, lim, d;
270814779705SSam Leffler 
270914779705SSam Leffler 	/*
271014779705SSam Leffler 	 * Check current channel to avoid the lookup.
271114779705SSam Leffler 	 */
271214779705SSam Leffler 	cc = AH_PRIVATE(ah)->ah_curchan;
271314779705SSam Leffler 	if (cc != AH_NULL && cc->channel == c->channel &&
271414779705SSam Leffler 	    (cc->channelFlags & CHAN_FLAGS) == flags) {
271514779705SSam Leffler 		if ((cc->privFlags & CHANNEL_INTERFERENCE) &&
271614779705SSam Leffler 		    (cc->channelFlags & CHANNEL_DFS))
271714779705SSam Leffler 			return AH_NULL;
271814779705SSam Leffler 		else
271914779705SSam Leffler 			return cc;
272014779705SSam Leffler 	}
272114779705SSam Leffler 
272214779705SSam Leffler 	/* binary search based on known sorting order */
272314779705SSam Leffler 	base = AH_PRIVATE(ah)->ah_channels;
272414779705SSam Leffler 	n = AH_PRIVATE(ah)->ah_nchan;
272514779705SSam Leffler 	/* binary search based on known sorting order */
272614779705SSam Leffler 	for (lim = n; lim != 0; lim >>= 1) {
272714779705SSam Leffler 		cc = &base[lim>>1];
272814779705SSam Leffler 		d = c->channel - cc->channel;
272914779705SSam Leffler 		if (d == 0) {
273014779705SSam Leffler 			if ((cc->channelFlags & CHAN_FLAGS) == flags) {
273114779705SSam Leffler 				if ((cc->privFlags & CHANNEL_INTERFERENCE) &&
273214779705SSam Leffler 				    (cc->channelFlags & CHANNEL_DFS))
273314779705SSam Leffler 					return AH_NULL;
273414779705SSam Leffler 				else
273514779705SSam Leffler 					return cc;
273614779705SSam Leffler 			}
273714779705SSam Leffler 			d = flags - (cc->channelFlags & CHAN_FLAGS);
273814779705SSam Leffler 		}
273914779705SSam Leffler 		if (d > 0) {
274014779705SSam Leffler 			base = cc + 1;
274114779705SSam Leffler 			lim--;
274214779705SSam Leffler 		}
274314779705SSam Leffler 	}
274414779705SSam Leffler 	HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, "%s: no match for %u/0x%x\n",
274514779705SSam Leffler 	   __func__, c->channel, c->channelFlags);
274614779705SSam Leffler 	return AH_NULL;
274714779705SSam Leffler #undef CHAN_FLAGS
274814779705SSam Leffler }
274914779705SSam Leffler 
275014779705SSam Leffler /*
275114779705SSam Leffler  * Return the max allowed antenna gain and apply any regulatory
275214779705SSam Leffler  * domain specific changes.
275314779705SSam Leffler  *
275414779705SSam Leffler  * NOTE: a negative reduction is possible in RD's that only
275514779705SSam Leffler  * measure radiated power (e.g., ETSI) which would increase
275614779705SSam Leffler  * that actual conducted output power (though never beyond
275714779705SSam Leffler  * the calibrated target power).
275814779705SSam Leffler  */
275914779705SSam Leffler u_int
276014779705SSam Leffler ath_hal_getantennareduction(struct ath_hal *ah, HAL_CHANNEL *chan, u_int twiceGain)
276114779705SSam Leffler {
276214779705SSam Leffler 	HAL_CHANNEL_INTERNAL *ichan=AH_NULL;
276314779705SSam Leffler 	int8_t antennaMax;
276414779705SSam Leffler 
276514779705SSam Leffler 	if ((ichan = ath_hal_checkchannel(ah, chan)) != AH_NULL) {
276614779705SSam Leffler 		antennaMax = twiceGain - ichan->antennaMax*2;
276714779705SSam Leffler 		return (antennaMax < 0) ? 0 : antennaMax;
276814779705SSam Leffler 	} else {
276914779705SSam Leffler 		/* Failed to find the correct index - may be a debug channel */
277014779705SSam Leffler 		return 0;
277114779705SSam Leffler 	}
277214779705SSam Leffler }
277314779705SSam Leffler 
277414779705SSam Leffler 
277514779705SSam Leffler /* XXX - maybe move ctl decision into channel set area or
277614779705SSam Leffler  into the tables so no decision is needed in the code */
277714779705SSam Leffler 
277814779705SSam Leffler #define isWwrSKU(_ah) \
277914779705SSam Leffler 	((getEepromRD((_ah)) & WORLD_SKU_MASK) == WORLD_SKU_PREFIX || \
278014779705SSam Leffler 	  getEepromRD(_ah) == WORLD)
278114779705SSam Leffler 
278214779705SSam Leffler 
278314779705SSam Leffler /*
278414779705SSam Leffler  * Return the test group from the specified channel from
278514779705SSam Leffler  * the regulatory table.
278614779705SSam Leffler  *
278714779705SSam Leffler  * TODO: CTL for 11B CommonMode when regulatory domain is unknown
278814779705SSam Leffler  */
278914779705SSam Leffler u_int
279014779705SSam Leffler ath_hal_getctl(struct ath_hal *ah, HAL_CHANNEL *chan)
279114779705SSam Leffler {
279214779705SSam Leffler 	u_int ctl = NO_CTL;
279314779705SSam Leffler 	HAL_CHANNEL_INTERNAL *ichan;
279414779705SSam Leffler 
279514779705SSam Leffler 	/* Special CTL to signify WWR SKU without a known country */
279614779705SSam Leffler 	if (AH_PRIVATE(ah)->ah_countryCode == CTRY_DEFAULT && isWwrSKU(ah)) {
279714779705SSam Leffler 		if (IS_CHAN_B(chan)) {
279814779705SSam Leffler 			ctl = SD_NO_CTL | CTL_11B;
279914779705SSam Leffler 		} else if (IS_CHAN_G(chan)) {
280014779705SSam Leffler 			ctl = SD_NO_CTL | CTL_11G;
280114779705SSam Leffler 		} else if (IS_CHAN_108G(chan)) {
280214779705SSam Leffler 			ctl = SD_NO_CTL | CTL_108G;
280314779705SSam Leffler 		} else if (IS_CHAN_T(chan)) {
280414779705SSam Leffler 			ctl = SD_NO_CTL | CTL_TURBO;
280514779705SSam Leffler 		} else {
280614779705SSam Leffler 			ctl = SD_NO_CTL | CTL_11A;
280714779705SSam Leffler 		}
280814779705SSam Leffler 	} else {
280914779705SSam Leffler 		if ((ichan = ath_hal_checkchannel(ah, chan)) != AH_NULL) {
281014779705SSam Leffler 			ctl = ichan->conformanceTestLimit;
281114779705SSam Leffler 			/* limit 11G OFDM power */
281214779705SSam Leffler 			if (IS_CHAN_PUREG(chan) &&
281314779705SSam Leffler 			    (ctl & CTL_MODE_M) == CTL_11B)
281414779705SSam Leffler 				ctl = (ctl &~ CTL_MODE_M) | CTL_11G;
281514779705SSam Leffler 		}
281614779705SSam Leffler 	}
281714779705SSam Leffler 	return ctl;
281814779705SSam Leffler }
281914779705SSam Leffler 
282014779705SSam Leffler /*
282114779705SSam Leffler  * Return whether or not a noise floor check is required in
282214779705SSam Leffler  * the current regulatory domain for the specified channel.
282314779705SSam Leffler  */
282414779705SSam Leffler HAL_BOOL
282514779705SSam Leffler ath_hal_getnfcheckrequired(struct ath_hal *ah, HAL_CHANNEL *chan)
282614779705SSam Leffler {
282714779705SSam Leffler 	HAL_CHANNEL_INTERNAL *ichan;
282814779705SSam Leffler 
282914779705SSam Leffler 	if ((ichan = ath_hal_checkchannel(ah, chan)) != AH_NULL)
283014779705SSam Leffler 		return ((ichan->regDmnFlags & NEED_NFC) ? AH_TRUE : AH_FALSE);
283114779705SSam Leffler 	return AH_FALSE;
283214779705SSam Leffler }
283314779705SSam Leffler 
283414779705SSam Leffler /*
283514779705SSam Leffler  * Insertion sort.
283614779705SSam Leffler  */
283714779705SSam Leffler #define swap(_a, _b, _size) {			\
283814779705SSam Leffler 	uint8_t *s = _b;			\
283914779705SSam Leffler 	int i = _size;				\
284014779705SSam Leffler 	do {					\
284114779705SSam Leffler 		uint8_t tmp = *_a;		\
284214779705SSam Leffler 		*_a++ = *s;			\
284314779705SSam Leffler 		*s++ = tmp;			\
284414779705SSam Leffler 	} while (--i);				\
284514779705SSam Leffler 	_a -= _size;				\
284614779705SSam Leffler }
284714779705SSam Leffler 
284814779705SSam Leffler static void
284914779705SSam Leffler ath_hal_sort(void *a, size_t n, size_t size, ath_hal_cmp_t *cmp)
285014779705SSam Leffler {
285114779705SSam Leffler 	uint8_t *aa = a;
285214779705SSam Leffler 	uint8_t *ai, *t;
285314779705SSam Leffler 
285414779705SSam Leffler 	for (ai = aa+size; --n >= 1; ai += size)
285514779705SSam Leffler 		for (t = ai; t > aa; t -= size) {
285614779705SSam Leffler 			uint8_t *u = t - size;
285714779705SSam Leffler 			if (cmp(u, t) <= 0)
285814779705SSam Leffler 				break;
285914779705SSam Leffler 			swap(u, t, size);
286014779705SSam Leffler 		}
286114779705SSam Leffler }
2862