xref: /freebsd/sys/dev/ath/ath_hal/ah_internal.h (revision f5f7c05209ca2c3748fd8b27c5e80ffad49120eb)
1 /*
2  * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3  * Copyright (c) 2002-2008 Atheros Communications, Inc.
4  *
5  * Permission to use, copy, modify, and/or distribute this software for any
6  * purpose with or without fee is hereby granted, provided that the above
7  * copyright notice and this permission notice appear in all copies.
8  *
9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16  *
17  * $FreeBSD$
18  */
19 #ifndef _ATH_AH_INTERAL_H_
20 #define _ATH_AH_INTERAL_H_
21 /*
22  * Atheros Device Hardware Access Layer (HAL).
23  *
24  * Internal definitions.
25  */
26 #define	AH_NULL	0
27 #define	AH_MIN(a,b)	((a)<(b)?(a):(b))
28 #define	AH_MAX(a,b)	((a)>(b)?(a):(b))
29 
30 #include <net80211/_ieee80211.h>
31 #include "opt_ah.h"			/* needed for AH_SUPPORT_AR5416 */
32 
33 #ifndef	AH_SUPPORT_AR5416
34 #define	AH_SUPPORT_AR5416	1
35 #endif
36 
37 #ifndef NBBY
38 #define	NBBY	8			/* number of bits/byte */
39 #endif
40 
41 #ifndef roundup
42 #define	roundup(x, y)	((((x)+((y)-1))/(y))*(y))  /* to any y */
43 #endif
44 #ifndef howmany
45 #define	howmany(x, y)	(((x)+((y)-1))/(y))
46 #endif
47 
48 #ifndef offsetof
49 #define	offsetof(type, field)	((size_t)(&((type *)0)->field))
50 #endif
51 
52 typedef struct {
53 	uint16_t	start;		/* first register */
54 	uint16_t	end;		/* ending register or zero */
55 } HAL_REGRANGE;
56 
57 typedef struct {
58 	uint32_t	addr;		/* regiser address/offset */
59 	uint32_t	value;		/* value to write */
60 } HAL_REGWRITE;
61 
62 /*
63  * Transmit power scale factor.
64  *
65  * NB: This is not public because we want to discourage the use of
66  *     scaling; folks should use the tx power limit interface.
67  */
68 typedef enum {
69 	HAL_TP_SCALE_MAX	= 0,		/* no scaling (default) */
70 	HAL_TP_SCALE_50		= 1,		/* 50% of max (-3 dBm) */
71 	HAL_TP_SCALE_25		= 2,		/* 25% of max (-6 dBm) */
72 	HAL_TP_SCALE_12		= 3,		/* 12% of max (-9 dBm) */
73 	HAL_TP_SCALE_MIN	= 4,		/* min, but still on */
74 } HAL_TP_SCALE;
75 
76 typedef enum {
77  	HAL_CAP_RADAR		= 0,		/* Radar capability */
78  	HAL_CAP_AR		= 1,		/* AR capability */
79 } HAL_PHYDIAG_CAPS;
80 
81 /*
82  * Enable/disable strong signal fast diversity
83  */
84 #define	HAL_CAP_STRONG_DIV		2
85 
86 /*
87  * Each chip or class of chips registers to offer support.
88  */
89 struct ath_hal_chip {
90 	const char	*name;
91 	const char	*(*probe)(uint16_t vendorid, uint16_t devid);
92 	struct ath_hal	*(*attach)(uint16_t devid, HAL_SOFTC,
93 			    HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata,
94 			    HAL_STATUS *error);
95 };
96 #ifndef AH_CHIP
97 #define	AH_CHIP(_name, _probe, _attach)				\
98 static struct ath_hal_chip _name##_chip = {			\
99 	.name		= #_name,				\
100 	.probe		= _probe,				\
101 	.attach		= _attach				\
102 };								\
103 OS_DATA_SET(ah_chips, _name##_chip)
104 #endif
105 
106 /*
107  * Each RF backend registers to offer support; this is mostly
108  * used by multi-chip 5212 solutions.  Single-chip solutions
109  * have a fixed idea about which RF to use.
110  */
111 struct ath_hal_rf {
112 	const char	*name;
113 	HAL_BOOL	(*probe)(struct ath_hal *ah);
114 	HAL_BOOL	(*attach)(struct ath_hal *ah, HAL_STATUS *ecode);
115 };
116 #ifndef AH_RF
117 #define	AH_RF(_name, _probe, _attach)				\
118 static struct ath_hal_rf _name##_rf = {				\
119 	.name		= __STRING(_name),			\
120 	.probe		= _probe,				\
121 	.attach		= _attach				\
122 };								\
123 OS_DATA_SET(ah_rfs, _name##_rf)
124 #endif
125 
126 struct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode);
127 
128 /*
129  * Maximum number of internal channels.  Entries are per unique
130  * frequency so this might be need to be increased to handle all
131  * usage cases; typically no more than 32 are really needed but
132  * dynamically allocating the data structures is a bit painful
133  * right now.
134  */
135 #ifndef AH_MAXCHAN
136 #define	AH_MAXCHAN	96
137 #endif
138 
139 #define	HAL_NF_CAL_HIST_LEN_FULL	5
140 #define	HAL_NF_CAL_HIST_LEN_SMALL	1
141 #define	HAL_NUM_NF_READINGS		6	/* 3 chains * (ctl + ext) */
142 #define	HAL_NF_LOAD_DELAY		1000
143 
144 /*
145  * PER_CHAN doesn't work for now, as it looks like the device layer
146  * has to pre-populate the per-channel list with nominal values.
147  */
148 //#define	ATH_NF_PER_CHAN		1
149 
150 typedef struct {
151     u_int8_t    curr_index;
152     int8_t      invalidNFcount; /* TO DO: REMOVE THIS! */
153     int16_t     priv_nf[HAL_NUM_NF_READINGS];
154 } HAL_NFCAL_BASE;
155 
156 typedef struct {
157     HAL_NFCAL_BASE base;
158     int16_t     nf_cal_buffer[HAL_NF_CAL_HIST_LEN_FULL][HAL_NUM_NF_READINGS];
159 } HAL_NFCAL_HIST_FULL;
160 
161 typedef struct {
162     HAL_NFCAL_BASE base;
163     int16_t     nf_cal_buffer[HAL_NF_CAL_HIST_LEN_SMALL][HAL_NUM_NF_READINGS];
164 } HAL_NFCAL_HIST_SMALL;
165 
166 #ifdef	ATH_NF_PER_CHAN
167 typedef HAL_NFCAL_HIST_FULL HAL_CHAN_NFCAL_HIST;
168 #define	AH_HOME_CHAN_NFCAL_HIST(ah, ichan) (ichan ? &ichan->nf_cal_hist: NULL)
169 #else
170 typedef HAL_NFCAL_HIST_SMALL HAL_CHAN_NFCAL_HIST;
171 #define	AH_HOME_CHAN_NFCAL_HIST(ah, ichan) (&AH_PRIVATE(ah)->nf_cal_hist)
172 #endif	/* ATH_NF_PER_CHAN */
173 
174 /*
175  * Internal per-channel state.  These are found
176  * using ic_devdata in the ieee80211_channel.
177  */
178 typedef struct {
179 	uint16_t	channel;	/* h/w frequency, NB: may be mapped */
180 	uint8_t		privFlags;
181 #define	CHANNEL_IQVALID		0x01	/* IQ calibration valid */
182 #define	CHANNEL_ANI_INIT	0x02	/* ANI state initialized */
183 #define	CHANNEL_ANI_SETUP	0x04	/* ANI state setup */
184 #define	CHANNEL_MIMO_NF_VALID	0x04	/* Mimo NF values are valid */
185 	uint8_t		calValid;	/* bitmask of cal types */
186 	int8_t		iCoff;
187 	int8_t		qCoff;
188 	int16_t		rawNoiseFloor;
189 	int16_t		noiseFloorAdjust;
190 #ifdef	AH_SUPPORT_AR5416
191 	int16_t		noiseFloorCtl[AH_MAX_CHAINS];
192 	int16_t		noiseFloorExt[AH_MAX_CHAINS];
193 #endif	/* AH_SUPPORT_AR5416 */
194 	uint16_t	mainSpur;	/* cached spur value for this channel */
195 
196 	/*XXX TODO: make these part of privFlags */
197 	uint8_t  paprd_done:1,           /* 1: PAPRD DONE, 0: PAPRD Cal not done */
198 	       paprd_table_write_done:1; /* 1: DONE, 0: Cal data write not done */
199 	int		one_time_cals_done;
200 	HAL_CHAN_NFCAL_HIST nf_cal_hist;
201 } HAL_CHANNEL_INTERNAL;
202 
203 /* channel requires noise floor check */
204 #define	CHANNEL_NFCREQUIRED	IEEE80211_CHAN_PRIV0
205 
206 /* all full-width channels */
207 #define	IEEE80211_CHAN_ALLFULL \
208 	(IEEE80211_CHAN_ALL - (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER))
209 #define	IEEE80211_CHAN_ALLTURBOFULL \
210 	(IEEE80211_CHAN_ALLTURBO - \
211 	 (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER))
212 
213 typedef struct {
214 	uint32_t	halChanSpreadSupport 		: 1,
215 			halSleepAfterBeaconBroken	: 1,
216 			halCompressSupport		: 1,
217 			halBurstSupport			: 1,
218 			halFastFramesSupport		: 1,
219 			halChapTuningSupport		: 1,
220 			halTurboGSupport		: 1,
221 			halTurboPrimeSupport		: 1,
222 			halMicAesCcmSupport		: 1,
223 			halMicCkipSupport		: 1,
224 			halMicTkipSupport		: 1,
225 			halTkipMicTxRxKeySupport	: 1,
226 			halCipherAesCcmSupport		: 1,
227 			halCipherCkipSupport		: 1,
228 			halCipherTkipSupport		: 1,
229 			halPSPollBroken			: 1,
230 			halVEOLSupport			: 1,
231 			halBssIdMaskSupport		: 1,
232 			halMcastKeySrchSupport		: 1,
233 			halTsfAddSupport		: 1,
234 			halChanHalfRate			: 1,
235 			halChanQuarterRate		: 1,
236 			halHTSupport			: 1,
237 			halHTSGI20Support		: 1,
238 			halRfSilentSupport		: 1,
239 			halHwPhyCounterSupport		: 1,
240 			halWowSupport			: 1,
241 			halWowMatchPatternExact		: 1,
242 			halAutoSleepSupport		: 1,
243 			halFastCCSupport		: 1,
244 			halBtCoexSupport		: 1;
245 	uint32_t	halRxStbcSupport		: 1,
246 			halTxStbcSupport		: 1,
247 			halGTTSupport			: 1,
248 			halCSTSupport			: 1,
249 			halRifsRxSupport		: 1,
250 			halRifsTxSupport		: 1,
251 			hal4AddrAggrSupport		: 1,
252 			halExtChanDfsSupport		: 1,
253 			halUseCombinedRadarRssi		: 1,
254 			halForcePpmSupport		: 1,
255 			halEnhancedPmSupport		: 1,
256 			halEnhancedDfsSupport		: 1,
257 			halMbssidAggrSupport		: 1,
258 			halBssidMatchSupport		: 1,
259 			hal4kbSplitTransSupport		: 1,
260 			halHasRxSelfLinkedTail		: 1,
261 			halSupportsFastClock5GHz	: 1,
262 			halHasLongRxDescTsf		: 1,
263 			halHasBBReadWar			: 1,
264 			halSerialiseRegWar		: 1,
265 			halMciSupport			: 1,
266 			halRxTxAbortSupport		: 1,
267 			halPaprdEnabled			: 1,
268 			halHasUapsdSupport		: 1,
269 			halWpsPushButtonSupport		: 1,
270 			halBtCoexApsmWar		: 1,
271 			halGenTimerSupport		: 1,
272 			halLDPCSupport			: 1,
273 			halHwBeaconProcSupport		: 1,
274 			halEnhancedDmaSupport		: 1;
275 	uint32_t	halIsrRacSupport		: 1,
276 			halApmEnable			: 1,
277 			halIntrMitigation		: 1,
278 			hal49GhzSupport			: 1,
279 			halAntDivCombSupport		: 1,
280 			halAntDivCombSupportOrg		: 1,
281 			halRadioRetentionSupport	: 1,
282 			halSpectralScanSupport		: 1;
283 
284 	uint32_t	halWirelessModes;
285 	uint16_t	halTotalQueues;
286 	uint16_t	halKeyCacheSize;
287 	uint16_t	halLow5GhzChan, halHigh5GhzChan;
288 	uint16_t	halLow2GhzChan, halHigh2GhzChan;
289 	int		halTstampPrecision;
290 	int		halRtsAggrLimit;
291 	uint8_t		halTxChainMask;
292 	uint8_t		halRxChainMask;
293 	uint8_t		halNumGpioPins;
294 	uint8_t		halNumAntCfg2GHz;
295 	uint8_t		halNumAntCfg5GHz;
296 	uint32_t	halIntrMask;
297 	uint8_t		halTxStreams;
298 	uint8_t		halRxStreams;
299 	HAL_MFP_OPT_T	halMfpSupport;
300 
301 	/* AR9300 HAL porting capabilities */
302 	int		hal_paprd_enabled;
303 	int		hal_pcie_lcr_offset;
304 	int		hal_pcie_lcr_extsync_en;
305 	int		halNumTxMaps;
306 	int		halTxDescLen;
307 	int		halTxStatusLen;
308 	int		halRxStatusLen;
309 	int		halRxHpFifoDepth;
310 	int		halRxLpFifoDepth;
311 	uint32_t	halRegCap;		/* XXX needed? */
312 	int		halNumMRRetries;
313 	int		hal_ani_poll_interval;
314 	int		hal_channel_switch_time_usec;
315 } HAL_CAPABILITIES;
316 
317 struct regDomain;
318 
319 /*
320  * Definitions for ah_flags in ath_hal_private
321  */
322 #define		AH_USE_EEPROM	0x1
323 #define		AH_IS_HB63	0x2
324 
325 /*
326  * The ``private area'' follows immediately after the ``public area''
327  * in the data structure returned by ath_hal_attach.  Private data are
328  * used by device-independent code such as the regulatory domain support.
329  * In general, code within the HAL should never depend on data in the
330  * public area.  Instead any public data needed internally should be
331  * shadowed here.
332  *
333  * When declaring a device-specific ath_hal data structure this structure
334  * is assumed to at the front; e.g.
335  *
336  *	struct ath_hal_5212 {
337  *		struct ath_hal_private	ah_priv;
338  *		...
339  *	};
340  *
341  * It might be better to manage the method pointers in this structure
342  * using an indirect pointer to a read-only data structure but this would
343  * disallow class-style method overriding.
344  */
345 struct ath_hal_private {
346 	struct ath_hal	h;			/* public area */
347 
348 	/* NB: all methods go first to simplify initialization */
349 	HAL_BOOL	(*ah_getChannelEdges)(struct ath_hal*,
350 				uint16_t channelFlags,
351 				uint16_t *lowChannel, uint16_t *highChannel);
352 	u_int		(*ah_getWirelessModes)(struct ath_hal*);
353 	HAL_BOOL	(*ah_eepromRead)(struct ath_hal *, u_int off,
354 				uint16_t *data);
355 	HAL_BOOL	(*ah_eepromWrite)(struct ath_hal *, u_int off,
356 				uint16_t data);
357 	HAL_BOOL	(*ah_getChipPowerLimits)(struct ath_hal *,
358 				struct ieee80211_channel *);
359 	int16_t		(*ah_getNfAdjust)(struct ath_hal *,
360 				const HAL_CHANNEL_INTERNAL*);
361 	void		(*ah_getNoiseFloor)(struct ath_hal *,
362 				int16_t nfarray[]);
363 
364 	void		*ah_eeprom;		/* opaque EEPROM state */
365 	uint16_t	ah_eeversion;		/* EEPROM version */
366 	void		(*ah_eepromDetach)(struct ath_hal *);
367 	HAL_STATUS	(*ah_eepromGet)(struct ath_hal *, int, void *);
368 	HAL_STATUS	(*ah_eepromSet)(struct ath_hal *, int, int);
369 	uint16_t	(*ah_getSpurChan)(struct ath_hal *, int, HAL_BOOL);
370 	HAL_BOOL	(*ah_eepromDiag)(struct ath_hal *, int request,
371 			    const void *args, uint32_t argsize,
372 			    void **result, uint32_t *resultsize);
373 
374 	/*
375 	 * Device revision information.
376 	 */
377 	uint16_t	ah_devid;		/* PCI device ID */
378 	uint16_t	ah_subvendorid;		/* PCI subvendor ID */
379 	uint32_t	ah_macVersion;		/* MAC version id */
380 	uint16_t	ah_macRev;		/* MAC revision */
381 	uint16_t	ah_phyRev;		/* PHY revision */
382 	uint16_t	ah_analog5GhzRev;	/* 2GHz radio revision */
383 	uint16_t	ah_analog2GhzRev;	/* 5GHz radio revision */
384 	uint32_t	ah_flags;		/* misc flags */
385 	uint8_t		ah_ispcie;		/* PCIE, special treatment */
386 	uint8_t		ah_devType;		/* card type - CB, PCI, PCIe */
387 
388 	HAL_OPMODE	ah_opmode;		/* operating mode from reset */
389 	const struct ieee80211_channel *ah_curchan;/* operating channel */
390 	HAL_CAPABILITIES ah_caps;		/* device capabilities */
391 	uint32_t	ah_diagreg;		/* user-specified AR_DIAG_SW */
392 	int16_t		ah_powerLimit;		/* tx power cap */
393 	uint16_t	ah_maxPowerLevel;	/* calculated max tx power */
394 	u_int		ah_tpScale;		/* tx power scale factor */
395 	uint32_t	ah_11nCompat;		/* 11n compat controls */
396 
397 	/*
398 	 * State for regulatory domain handling.
399 	 */
400 	HAL_REG_DOMAIN	ah_currentRD;		/* EEPROM regulatory domain */
401 	HAL_REG_DOMAIN	ah_currentRDext;	/* EEPROM extended regdomain flags */
402 	HAL_DFS_DOMAIN	ah_dfsDomain;		/* current DFS domain */
403 	HAL_CHANNEL_INTERNAL ah_channels[AH_MAXCHAN]; /* private chan state */
404 	u_int		ah_nchan;		/* valid items in ah_channels */
405 	const struct regDomain *ah_rd2GHz;	/* reg state for 2G band */
406 	const struct regDomain *ah_rd5GHz;	/* reg state for 5G band */
407 
408 	uint8_t    	ah_coverageClass;   	/* coverage class */
409 	/*
410 	 * RF Silent handling; setup according to the EEPROM.
411 	 */
412 	uint16_t	ah_rfsilent;		/* GPIO pin + polarity */
413 	HAL_BOOL	ah_rfkillEnabled;	/* enable/disable RfKill */
414 	/*
415 	 * Diagnostic support for discriminating HIUERR reports.
416 	 */
417 	uint32_t	ah_fatalState[6];	/* AR_ISR+shadow regs */
418 	int		ah_rxornIsFatal;	/* how to treat HAL_INT_RXORN */
419 
420 #ifndef	ATH_NF_PER_CHAN
421 	HAL_NFCAL_HIST_FULL	nf_cal_hist;
422 #endif	/* ! ATH_NF_PER_CHAN */
423 };
424 
425 #define	AH_PRIVATE(_ah)	((struct ath_hal_private *)(_ah))
426 
427 #define	ath_hal_getChannelEdges(_ah, _cf, _lc, _hc) \
428 	AH_PRIVATE(_ah)->ah_getChannelEdges(_ah, _cf, _lc, _hc)
429 #define	ath_hal_getWirelessModes(_ah) \
430 	AH_PRIVATE(_ah)->ah_getWirelessModes(_ah)
431 #define	ath_hal_eepromRead(_ah, _off, _data) \
432 	AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data)
433 #define	ath_hal_eepromWrite(_ah, _off, _data) \
434 	AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data)
435 #define	ath_hal_gpioCfgOutput(_ah, _gpio, _type) \
436 	(_ah)->ah_gpioCfgOutput(_ah, _gpio, _type)
437 #define	ath_hal_gpioCfgInput(_ah, _gpio) \
438 	(_ah)->ah_gpioCfgInput(_ah, _gpio)
439 #define	ath_hal_gpioGet(_ah, _gpio) \
440 	(_ah)->ah_gpioGet(_ah, _gpio)
441 #define	ath_hal_gpioSet(_ah, _gpio, _val) \
442 	(_ah)->ah_gpioSet(_ah, _gpio, _val)
443 #define	ath_hal_gpioSetIntr(_ah, _gpio, _ilevel) \
444 	(_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel)
445 #define	ath_hal_getpowerlimits(_ah, _chan) \
446 	AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chan)
447 #define ath_hal_getNfAdjust(_ah, _c) \
448 	AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c)
449 #define	ath_hal_getNoiseFloor(_ah, _nfArray) \
450 	AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray)
451 #define	ath_hal_configPCIE(_ah, _reset, _poweroff) \
452 	(_ah)->ah_configPCIE(_ah, _reset, _poweroff)
453 #define	ath_hal_disablePCIE(_ah) \
454 	(_ah)->ah_disablePCIE(_ah)
455 #define	ath_hal_setInterrupts(_ah, _mask) \
456 	(_ah)->ah_setInterrupts(_ah, _mask)
457 
458 #define ath_hal_isrfkillenabled(_ah)  \
459     (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, AH_NULL) == HAL_OK)
460 #define ath_hal_enable_rfkill(_ah, _v) \
461     ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _v, AH_NULL)
462 #define ath_hal_hasrfkill_int(_ah)  \
463     (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 3, AH_NULL) == HAL_OK)
464 
465 #define	ath_hal_eepromDetach(_ah) do {				\
466 	if (AH_PRIVATE(_ah)->ah_eepromDetach != AH_NULL)	\
467 		AH_PRIVATE(_ah)->ah_eepromDetach(_ah);		\
468 } while (0)
469 #define	ath_hal_eepromGet(_ah, _param, _val) \
470 	AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val)
471 #define	ath_hal_eepromSet(_ah, _param, _val) \
472 	AH_PRIVATE(_ah)->ah_eepromSet(_ah, _param, _val)
473 #define	ath_hal_eepromGetFlag(_ah, _param) \
474 	(AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, AH_NULL) == HAL_OK)
475 #define ath_hal_getSpurChan(_ah, _ix, _is2G) \
476 	AH_PRIVATE(_ah)->ah_getSpurChan(_ah, _ix, _is2G)
477 #define	ath_hal_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) \
478 	AH_PRIVATE(_ah)->ah_eepromDiag(_ah, _request, _a, _asize,  _r, _rsize)
479 
480 #ifndef _NET_IF_IEEE80211_H_
481 /*
482  * Stuff that would naturally come from _ieee80211.h
483  */
484 #define	IEEE80211_ADDR_LEN		6
485 
486 #define	IEEE80211_WEP_IVLEN			3	/* 24bit */
487 #define	IEEE80211_WEP_KIDLEN			1	/* 1 octet */
488 #define	IEEE80211_WEP_CRCLEN			4	/* CRC-32 */
489 
490 #define	IEEE80211_CRC_LEN			4
491 
492 #define	IEEE80211_MAX_LEN			(2300 + IEEE80211_CRC_LEN + \
493     (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN))
494 #endif /* _NET_IF_IEEE80211_H_ */
495 
496 #define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS	0x00000001
497 
498 #define INIT_AIFS		2
499 #define INIT_CWMIN		15
500 #define INIT_CWMIN_11B		31
501 #define INIT_CWMAX		1023
502 #define INIT_SH_RETRY		10
503 #define INIT_LG_RETRY		10
504 #define INIT_SSH_RETRY		32
505 #define INIT_SLG_RETRY		32
506 
507 typedef struct {
508 	uint32_t	tqi_ver;		/* HAL TXQ verson */
509 	HAL_TX_QUEUE	tqi_type;		/* hw queue type*/
510 	HAL_TX_QUEUE_SUBTYPE tqi_subtype;	/* queue subtype, if applicable */
511 	HAL_TX_QUEUE_FLAGS tqi_qflags;		/* queue flags */
512 	uint32_t	tqi_priority;
513 	uint32_t	tqi_aifs;		/* aifs */
514 	uint32_t	tqi_cwmin;		/* cwMin */
515 	uint32_t	tqi_cwmax;		/* cwMax */
516 	uint16_t	tqi_shretry;		/* frame short retry limit */
517 	uint16_t	tqi_lgretry;		/* frame long retry limit */
518 	uint32_t	tqi_cbrPeriod;
519 	uint32_t	tqi_cbrOverflowLimit;
520 	uint32_t	tqi_burstTime;
521 	uint32_t	tqi_readyTime;
522 	uint32_t	tqi_physCompBuf;
523 	uint32_t	tqi_intFlags;		/* flags for internal use */
524 } HAL_TX_QUEUE_INFO;
525 
526 extern	HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah,
527 		HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo);
528 extern	HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah,
529 		HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi);
530 
531 #define	HAL_SPUR_VAL_MASK		0x3FFF
532 #define	HAL_SPUR_CHAN_WIDTH		87
533 #define	HAL_BIN_WIDTH_BASE_100HZ	3125
534 #define	HAL_BIN_WIDTH_TURBO_100HZ	6250
535 #define	HAL_MAX_BINS_ALLOWED		28
536 
537 #define	IS_CHAN_5GHZ(_c)	((_c)->channel > 4900)
538 #define	IS_CHAN_2GHZ(_c)	(!IS_CHAN_5GHZ(_c))
539 
540 #define	IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990)
541 
542 /*
543  * Deduce if the host cpu has big- or litt-endian byte order.
544  */
545 static __inline__ int
546 isBigEndian(void)
547 {
548 	union {
549 		int32_t i;
550 		char c[4];
551 	} u;
552 	u.i = 1;
553 	return (u.c[0] == 0);
554 }
555 
556 /* unalligned little endian access */
557 #define LE_READ_2(p)							\
558 	((uint16_t)							\
559 	 ((((const uint8_t *)(p))[0]    ) | (((const uint8_t *)(p))[1]<< 8)))
560 #define LE_READ_4(p)							\
561 	((uint32_t)							\
562 	 ((((const uint8_t *)(p))[0]    ) | (((const uint8_t *)(p))[1]<< 8) |\
563 	  (((const uint8_t *)(p))[2]<<16) | (((const uint8_t *)(p))[3]<<24)))
564 
565 /*
566  * Register manipulation macros that expect bit field defines
567  * to follow the convention that an _S suffix is appended for
568  * a shift count, while the field mask has no suffix.
569  */
570 #define	SM(_v, _f)	(((_v) << _f##_S) & (_f))
571 #define	MS(_v, _f)	(((_v) & (_f)) >> _f##_S)
572 #define OS_REG_RMW(_a, _r, _set, _clr)    \
573 	OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) & ~(_clr)) | (_set))
574 #define	OS_REG_RMW_FIELD(_a, _r, _f, _v) \
575 	OS_REG_WRITE(_a, _r, \
576 		(OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f)))
577 #define	OS_REG_SET_BIT(_a, _r, _f) \
578 	OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | (_f))
579 #define	OS_REG_CLR_BIT(_a, _r, _f) \
580 	OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f))
581 #define OS_REG_IS_BIT_SET(_a, _r, _f) \
582 	    ((OS_REG_READ(_a, _r) & (_f)) != 0)
583 #define	OS_REG_RMW_FIELD_ALT(_a, _r, _f, _v) \
584 	    OS_REG_WRITE(_a, _r, \
585 	    (OS_REG_READ(_a, _r) &~(_f<<_f##_S)) | \
586 	    (((_v) << _f##_S) & (_f<<_f##_S)))
587 #define	OS_REG_READ_FIELD(_a, _r, _f) \
588 	    (((OS_REG_READ(_a, _r) & _f) >> _f##_S))
589 #define	OS_REG_READ_FIELD_ALT(_a, _r, _f) \
590 	    ((OS_REG_READ(_a, _r) >> (_f##_S))&(_f))
591 
592 /* Analog register writes may require a delay between each one (eg Merlin?) */
593 #define	OS_A_REG_RMW_FIELD(_a, _r, _f, _v) \
594 	do { OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) &~ (_f)) | \
595 	    (((_v) << _f##_S) & (_f))) ; OS_DELAY(100); } while (0)
596 #define	OS_A_REG_WRITE(_a, _r, _v) \
597 	do { OS_REG_WRITE(_a, _r, _v); OS_DELAY(100); } while (0)
598 
599 /* wait for the register contents to have the specified value */
600 extern	HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg,
601 		uint32_t mask, uint32_t val);
602 extern	HAL_BOOL ath_hal_waitfor(struct ath_hal *, u_int reg,
603 		uint32_t mask, uint32_t val, uint32_t timeout);
604 
605 /* return the first n bits in val reversed */
606 extern	uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n);
607 
608 /* printf interfaces */
609 extern	void ath_hal_printf(struct ath_hal *, const char*, ...)
610 		__printflike(2,3);
611 extern	void ath_hal_vprintf(struct ath_hal *, const char*, __va_list)
612 		__printflike(2, 0);
613 extern	const char* ath_hal_ether_sprintf(const uint8_t *mac);
614 
615 /* allocate and free memory */
616 extern	void *ath_hal_malloc(size_t);
617 extern	void ath_hal_free(void *);
618 
619 /* common debugging interfaces */
620 #ifdef AH_DEBUG
621 #include "ah_debug.h"
622 extern	int ath_hal_debug;	/* Global debug flags */
623 
624 /*
625  * The typecast is purely because some callers will pass in
626  * AH_NULL directly rather than using a NULL ath_hal pointer.
627  */
628 #define	HALDEBUG(_ah, __m, ...) \
629 	do {							\
630 		if ((__m) == HAL_DEBUG_UNMASKABLE ||		\
631 		    ath_hal_debug & (__m) ||			\
632 		    ((_ah) != NULL &&				\
633 		      ((struct ath_hal *) (_ah))->ah_config.ah_debug & (__m))) {	\
634 			DO_HALDEBUG((_ah), (__m), __VA_ARGS__);	\
635 		}						\
636 	} while(0);
637 
638 extern	void DO_HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...)
639 	__printflike(3,4);
640 #else
641 #define HALDEBUG(_ah, __m, ...)
642 #endif /* AH_DEBUG */
643 
644 /*
645  * Register logging definitions shared with ardecode.
646  */
647 #include "ah_decode.h"
648 
649 /*
650  * Common assertion interface.  Note: it is a bad idea to generate
651  * an assertion failure for any recoverable event.  Instead catch
652  * the violation and, if possible, fix it up or recover from it; either
653  * with an error return value or a diagnostic messages.  System software
654  * does not panic unless the situation is hopeless.
655  */
656 #ifdef AH_ASSERT
657 extern	void ath_hal_assert_failed(const char* filename,
658 		int lineno, const char* msg);
659 
660 #define	HALASSERT(_x) do {					\
661 	if (!(_x)) {						\
662 		ath_hal_assert_failed(__FILE__, __LINE__, #_x);	\
663 	}							\
664 } while (0)
665 #else
666 #define	HALASSERT(_x)
667 #endif /* AH_ASSERT */
668 
669 /*
670  * Regulatory domain support.
671  */
672 
673 /*
674  * Return the max allowed antenna gain and apply any regulatory
675  * domain specific changes.
676  */
677 u_int	ath_hal_getantennareduction(struct ath_hal *ah,
678 	    const struct ieee80211_channel *chan, u_int twiceGain);
679 
680 /*
681  * Return the test group for the specific channel based on
682  * the current regulatory setup.
683  */
684 u_int	ath_hal_getctl(struct ath_hal *, const struct ieee80211_channel *);
685 
686 /*
687  * Map a public channel definition to the corresponding
688  * internal data structure.  This implicitly specifies
689  * whether or not the specified channel is ok to use
690  * based on the current regulatory domain constraints.
691  */
692 #ifndef AH_DEBUG
693 static OS_INLINE HAL_CHANNEL_INTERNAL *
694 ath_hal_checkchannel(struct ath_hal *ah, const struct ieee80211_channel *c)
695 {
696 	HAL_CHANNEL_INTERNAL *cc;
697 
698 	HALASSERT(c->ic_devdata < AH_PRIVATE(ah)->ah_nchan);
699 	cc = &AH_PRIVATE(ah)->ah_channels[c->ic_devdata];
700 	HALASSERT(c->ic_freq == cc->channel || IEEE80211_IS_CHAN_GSM(c));
701 	return cc;
702 }
703 #else
704 /* NB: non-inline version that checks state */
705 HAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *,
706 		const struct ieee80211_channel *);
707 #endif /* AH_DEBUG */
708 
709 /*
710  * Return the h/w frequency for a channel.  This may be
711  * different from ic_freq if this is a GSM device that
712  * takes 2.4GHz frequencies and down-converts them.
713  */
714 static OS_INLINE uint16_t
715 ath_hal_gethwchannel(struct ath_hal *ah, const struct ieee80211_channel *c)
716 {
717 	return ath_hal_checkchannel(ah, c)->channel;
718 }
719 
720 /*
721  * Convert between microseconds and core system clocks.
722  */
723 extern	u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs);
724 extern	u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks);
725 
726 /*
727  * Generic get/set capability support.  Each chip overrides
728  * this routine to support chip-specific capabilities.
729  */
730 extern	HAL_STATUS ath_hal_getcapability(struct ath_hal *ah,
731 		HAL_CAPABILITY_TYPE type, uint32_t capability,
732 		uint32_t *result);
733 extern	HAL_BOOL ath_hal_setcapability(struct ath_hal *ah,
734 		HAL_CAPABILITY_TYPE type, uint32_t capability,
735 		uint32_t setting, HAL_STATUS *status);
736 
737 /* The diagnostic codes used to be internally defined here -adrian */
738 #include "ah_diagcodes.h"
739 
740 /*
741  * The AR5416 and later HALs have MAC and baseband hang checking.
742  */
743 typedef struct {
744 	uint32_t hang_reg_offset;
745 	uint32_t hang_val;
746 	uint32_t hang_mask;
747 	uint32_t hang_offset;
748 } hal_hw_hang_check_t;
749 
750 typedef struct {
751 	uint32_t dma_dbg_3;
752 	uint32_t dma_dbg_4;
753 	uint32_t dma_dbg_5;
754 	uint32_t dma_dbg_6;
755 } mac_dbg_regs_t;
756 
757 typedef enum {
758 	dcu_chain_state		= 0x1,
759 	dcu_complete_state	= 0x2,
760 	qcu_state		= 0x4,
761 	qcu_fsp_ok		= 0x8,
762 	qcu_fsp_state		= 0x10,
763 	qcu_stitch_state	= 0x20,
764 	qcu_fetch_state		= 0x40,
765 	qcu_complete_state	= 0x80
766 } hal_mac_hangs_t;
767 
768 typedef struct {
769 	int states;
770 	uint8_t dcu_chain_state;
771 	uint8_t dcu_complete_state;
772 	uint8_t qcu_state;
773 	uint8_t qcu_fsp_ok;
774 	uint8_t qcu_fsp_state;
775 	uint8_t qcu_stitch_state;
776 	uint8_t qcu_fetch_state;
777 	uint8_t qcu_complete_state;
778 } hal_mac_hang_check_t;
779 
780 enum {
781     HAL_BB_HANG_DFS		= 0x0001,
782     HAL_BB_HANG_RIFS		= 0x0002,
783     HAL_BB_HANG_RX_CLEAR	= 0x0004,
784     HAL_BB_HANG_UNKNOWN		= 0x0080,
785 
786     HAL_MAC_HANG_SIG1		= 0x0100,
787     HAL_MAC_HANG_SIG2		= 0x0200,
788     HAL_MAC_HANG_UNKNOWN	= 0x8000,
789 
790     HAL_BB_HANGS = HAL_BB_HANG_DFS
791 		 | HAL_BB_HANG_RIFS
792 		 | HAL_BB_HANG_RX_CLEAR
793 		 | HAL_BB_HANG_UNKNOWN,
794     HAL_MAC_HANGS = HAL_MAC_HANG_SIG1
795 		 | HAL_MAC_HANG_SIG2
796 		 | HAL_MAC_HANG_UNKNOWN,
797 };
798 
799 /* Merge these with above */
800 typedef enum hal_hw_hangs {
801     HAL_DFS_BB_HANG_WAR          = 0x1,
802     HAL_RIFS_BB_HANG_WAR         = 0x2,
803     HAL_RX_STUCK_LOW_BB_HANG_WAR = 0x4,
804     HAL_MAC_HANG_WAR             = 0x8,
805     HAL_PHYRESTART_CLR_WAR       = 0x10,
806     HAL_MAC_HANG_DETECTED        = 0x40000000,
807     HAL_BB_HANG_DETECTED         = 0x80000000
808 } hal_hw_hangs_t;
809 
810 /*
811  * Device revision information.
812  */
813 typedef struct {
814 	uint16_t	ah_devid;		/* PCI device ID */
815 	uint16_t	ah_subvendorid;		/* PCI subvendor ID */
816 	uint32_t	ah_macVersion;		/* MAC version id */
817 	uint16_t	ah_macRev;		/* MAC revision */
818 	uint16_t	ah_phyRev;		/* PHY revision */
819 	uint16_t	ah_analog5GhzRev;	/* 2GHz radio revision */
820 	uint16_t	ah_analog2GhzRev;	/* 5GHz radio revision */
821 } HAL_REVS;
822 
823 /*
824  * Argument payload for HAL_DIAG_SETKEY.
825  */
826 typedef struct {
827 	HAL_KEYVAL	dk_keyval;
828 	uint16_t	dk_keyix;	/* key index */
829 	uint8_t		dk_mac[IEEE80211_ADDR_LEN];
830 	int		dk_xor;		/* XOR key data */
831 } HAL_DIAG_KEYVAL;
832 
833 /*
834  * Argument payload for HAL_DIAG_EEWRITE.
835  */
836 typedef struct {
837 	uint16_t	ee_off;		/* eeprom offset */
838 	uint16_t	ee_data;	/* write data */
839 } HAL_DIAG_EEVAL;
840 
841 
842 typedef struct {
843 	u_int offset;		/* reg offset */
844 	uint32_t val;		/* reg value  */
845 } HAL_DIAG_REGVAL;
846 
847 /*
848  * 11n compatibility tweaks.
849  */
850 #define	HAL_DIAG_11N_SERVICES	0x00000003
851 #define	HAL_DIAG_11N_SERVICES_S	0
852 #define	HAL_DIAG_11N_TXSTOMP	0x0000000c
853 #define	HAL_DIAG_11N_TXSTOMP_S	2
854 
855 typedef struct {
856 	int		maxNoiseImmunityLevel;	/* [0..4] */
857 	int		totalSizeDesired[5];
858 	int		coarseHigh[5];
859 	int		coarseLow[5];
860 	int		firpwr[5];
861 
862 	int		maxSpurImmunityLevel;	/* [0..7] */
863 	int		cycPwrThr1[8];
864 
865 	int		maxFirstepLevel;	/* [0..2] */
866 	int		firstep[3];
867 
868 	uint32_t	ofdmTrigHigh;
869 	uint32_t	ofdmTrigLow;
870 	int32_t		cckTrigHigh;
871 	int32_t		cckTrigLow;
872 	int32_t		rssiThrLow;
873 	int32_t		rssiThrHigh;
874 
875 	int		period;			/* update listen period */
876 } HAL_ANI_PARAMS;
877 
878 extern	HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request,
879 			const void *args, uint32_t argsize,
880 			void **result, uint32_t *resultsize);
881 
882 /*
883  * Setup a h/w rate table for use.
884  */
885 extern	void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt);
886 
887 /*
888  * Common routine for implementing getChanNoise api.
889  */
890 int16_t	ath_hal_getChanNoise(struct ath_hal *, const struct ieee80211_channel *);
891 
892 /*
893  * Initialization support.
894  */
895 typedef struct {
896 	const uint32_t	*data;
897 	int		rows, cols;
898 } HAL_INI_ARRAY;
899 
900 #define	HAL_INI_INIT(_ia, _data, _cols) do {			\
901 	(_ia)->data = (const uint32_t *)(_data);		\
902 	(_ia)->rows = sizeof(_data) / sizeof((_data)[0]);	\
903 	(_ia)->cols = (_cols);					\
904 } while (0)
905 #define	HAL_INI_VAL(_ia, _r, _c) \
906 	((_ia)->data[((_r)*(_ia)->cols) + (_c)])
907 
908 /*
909  * OS_DELAY() does a PIO READ on the PCI bus which allows
910  * other cards' DMA reads to complete in the middle of our reset.
911  */
912 #define DMA_YIELD(x) do {		\
913 	if ((++(x) % 64) == 0)		\
914 		OS_DELAY(1);		\
915 } while (0)
916 
917 #define HAL_INI_WRITE_ARRAY(ah, regArray, col, regWr) do {             	\
918 	int r;								\
919 	for (r = 0; r < N(regArray); r++) {				\
920 		OS_REG_WRITE(ah, (regArray)[r][0], (regArray)[r][col]);	\
921 		DMA_YIELD(regWr);					\
922 	}								\
923 } while (0)
924 
925 #define HAL_INI_WRITE_BANK(ah, regArray, bankData, regWr) do {		\
926 	int r;								\
927 	for (r = 0; r < N(regArray); r++) {				\
928 		OS_REG_WRITE(ah, (regArray)[r][0], (bankData)[r]);	\
929 		DMA_YIELD(regWr);					\
930 	}								\
931 } while (0)
932 
933 extern	int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia,
934 		int col, int regWr);
935 extern	void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia,
936 		int col);
937 extern	int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia,
938 		const uint32_t data[], int regWr);
939 
940 #define	CCK_SIFS_TIME		10
941 #define	CCK_PREAMBLE_BITS	144
942 #define	CCK_PLCP_BITS		48
943 
944 #define	OFDM_SIFS_TIME		16
945 #define	OFDM_PREAMBLE_TIME	20
946 #define	OFDM_PLCP_BITS		22
947 #define	OFDM_SYMBOL_TIME	4
948 
949 #define	OFDM_HALF_SIFS_TIME	32
950 #define	OFDM_HALF_PREAMBLE_TIME	40
951 #define	OFDM_HALF_PLCP_BITS	22
952 #define	OFDM_HALF_SYMBOL_TIME	8
953 
954 #define	OFDM_QUARTER_SIFS_TIME 		64
955 #define	OFDM_QUARTER_PREAMBLE_TIME	80
956 #define	OFDM_QUARTER_PLCP_BITS		22
957 #define	OFDM_QUARTER_SYMBOL_TIME	16
958 
959 #define	TURBO_SIFS_TIME		8
960 #define	TURBO_PREAMBLE_TIME	14
961 #define	TURBO_PLCP_BITS		22
962 #define	TURBO_SYMBOL_TIME	4
963 
964 #define	WLAN_CTRL_FRAME_SIZE	(2+2+6+4)	/* ACK+FCS */
965 
966 /* Generic EEPROM board value functions */
967 extern	HAL_BOOL ath_ee_getLowerUpperIndex(uint8_t target, uint8_t *pList,
968 	uint16_t listSize, uint16_t *indexL, uint16_t *indexR);
969 extern	HAL_BOOL ath_ee_FillVpdTable(uint8_t pwrMin, uint8_t pwrMax,
970 	uint8_t *pPwrList, uint8_t *pVpdList, uint16_t numIntercepts,
971 	uint8_t *pRetVpdList);
972 extern	int16_t ath_ee_interpolate(uint16_t target, uint16_t srcLeft,
973 	uint16_t srcRight, int16_t targetLeft, int16_t targetRight);
974 
975 /* Whether 5ghz fast clock is needed */
976 /*
977  * The chipset (Merlin, AR9300/later) should set the capability flag below;
978  * this flag simply says that the hardware can do it, not that the EEPROM
979  * says it can.
980  *
981  * Merlin 2.0/2.1 chips with an EEPROM version > 16 do 5ghz fast clock
982  *   if the relevant eeprom flag is set.
983  * Merlin 2.0/2.1 chips with an EEPROM version <= 16 do 5ghz fast clock
984  *   by default.
985  */
986 #define	IS_5GHZ_FAST_CLOCK_EN(_ah, _c) \
987 	(IEEE80211_IS_CHAN_5GHZ(_c) && \
988 	 AH_PRIVATE((_ah))->ah_caps.halSupportsFastClock5GHz && \
989 	ath_hal_eepromGetFlag((_ah), AR_EEP_FSTCLK_5G))
990 
991 /*
992  * Fetch the maximum regulatory domain power for the given channel
993  * in 1/2dBm steps.
994  */
995 static inline int
996 ath_hal_get_twice_max_regpower(struct ath_hal_private *ahp,
997     const HAL_CHANNEL_INTERNAL *ichan, const struct ieee80211_channel *chan)
998 {
999 	struct ath_hal *ah = &ahp->h;
1000 
1001 	if (! chan) {
1002 		ath_hal_printf(ah, "%s: called with chan=NULL!\n", __func__);
1003 		return (0);
1004 	}
1005 	return (chan->ic_maxpower);
1006 }
1007 
1008 /*
1009  * Get the maximum antenna gain allowed, in 1/2dBm steps.
1010  */
1011 static inline int
1012 ath_hal_getantennaallowed(struct ath_hal *ah,
1013     const struct ieee80211_channel *chan)
1014 {
1015 
1016 	if (! chan)
1017 		return (0);
1018 
1019 	return (chan->ic_maxantgain);
1020 }
1021 
1022 
1023 #endif /* _ATH_AH_INTERAL_H_ */
1024