1 /* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19 #ifndef _ATH_AH_INTERAL_H_ 20 #define _ATH_AH_INTERAL_H_ 21 /* 22 * Atheros Device Hardware Access Layer (HAL). 23 * 24 * Internal definitions. 25 */ 26 #define AH_NULL 0 27 #define AH_MIN(a,b) ((a)<(b)?(a):(b)) 28 #define AH_MAX(a,b) ((a)>(b)?(a):(b)) 29 30 #include <net80211/_ieee80211.h> 31 32 #ifndef NBBY 33 #define NBBY 8 /* number of bits/byte */ 34 #endif 35 36 #ifndef roundup 37 #define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */ 38 #endif 39 #ifndef howmany 40 #define howmany(x, y) (((x)+((y)-1))/(y)) 41 #endif 42 43 #ifndef offsetof 44 #define offsetof(type, field) ((size_t)(&((type *)0)->field)) 45 #endif 46 47 typedef struct { 48 uint16_t start; /* first register */ 49 uint16_t end; /* ending register or zero */ 50 } HAL_REGRANGE; 51 52 typedef struct { 53 uint32_t addr; /* regiser address/offset */ 54 uint32_t value; /* value to write */ 55 } HAL_REGWRITE; 56 57 /* 58 * Transmit power scale factor. 59 * 60 * NB: This is not public because we want to discourage the use of 61 * scaling; folks should use the tx power limit interface. 62 */ 63 typedef enum { 64 HAL_TP_SCALE_MAX = 0, /* no scaling (default) */ 65 HAL_TP_SCALE_50 = 1, /* 50% of max (-3 dBm) */ 66 HAL_TP_SCALE_25 = 2, /* 25% of max (-6 dBm) */ 67 HAL_TP_SCALE_12 = 3, /* 12% of max (-9 dBm) */ 68 HAL_TP_SCALE_MIN = 4, /* min, but still on */ 69 } HAL_TP_SCALE; 70 71 typedef enum { 72 HAL_CAP_RADAR = 0, /* Radar capability */ 73 HAL_CAP_AR = 1, /* AR capability */ 74 } HAL_PHYDIAG_CAPS; 75 76 /* 77 * Each chip or class of chips registers to offer support. 78 */ 79 struct ath_hal_chip { 80 const char *name; 81 const char *(*probe)(uint16_t vendorid, uint16_t devid); 82 struct ath_hal *(*attach)(uint16_t devid, HAL_SOFTC, 83 HAL_BUS_TAG, HAL_BUS_HANDLE, HAL_STATUS *error); 84 }; 85 #ifndef AH_CHIP 86 #define AH_CHIP(_name, _probe, _attach) \ 87 static struct ath_hal_chip _name##_chip = { \ 88 .name = #_name, \ 89 .probe = _probe, \ 90 .attach = _attach \ 91 }; \ 92 OS_DATA_SET(ah_chips, _name##_chip) 93 #endif 94 95 /* 96 * Each RF backend registers to offer support; this is mostly 97 * used by multi-chip 5212 solutions. Single-chip solutions 98 * have a fixed idea about which RF to use. 99 */ 100 struct ath_hal_rf { 101 const char *name; 102 HAL_BOOL (*probe)(struct ath_hal *ah); 103 HAL_BOOL (*attach)(struct ath_hal *ah, HAL_STATUS *ecode); 104 }; 105 #ifndef AH_RF 106 #define AH_RF(_name, _probe, _attach) \ 107 static struct ath_hal_rf _name##_rf = { \ 108 .name = __STRING(_name), \ 109 .probe = _probe, \ 110 .attach = _attach \ 111 }; \ 112 OS_DATA_SET(ah_rfs, _name##_rf) 113 #endif 114 115 struct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode); 116 117 /* 118 * Maximum number of internal channels. Entries are per unique 119 * frequency so this might be need to be increased to handle all 120 * usage cases; typically no more than 32 are really needed but 121 * dynamically allocating the data structures is a bit painful 122 * right now. 123 */ 124 #ifndef AH_MAXCHAN 125 #define AH_MAXCHAN 96 126 #endif 127 128 /* 129 * Internal per-channel state. These are found 130 * using ic_devdata in the ieee80211_channel. 131 */ 132 typedef struct { 133 uint16_t channel; /* h/w frequency, NB: may be mapped */ 134 uint8_t privFlags; 135 #define CHANNEL_IQVALID 0x01 /* IQ calibration valid */ 136 #define CHANNEL_ANI_INIT 0x02 /* ANI state initialized */ 137 #define CHANNEL_ANI_SETUP 0x04 /* ANI state setup */ 138 uint8_t calValid; /* bitmask of cal types */ 139 int8_t iCoff; 140 int8_t qCoff; 141 int16_t rawNoiseFloor; 142 int16_t noiseFloorAdjust; 143 uint16_t mainSpur; /* cached spur value for this channel */ 144 } HAL_CHANNEL_INTERNAL; 145 146 /* channel requires noise floor check */ 147 #define CHANNEL_NFCREQUIRED IEEE80211_CHAN_PRIV0 148 149 /* all full-width channels */ 150 #define IEEE80211_CHAN_ALLFULL \ 151 (IEEE80211_CHAN_ALL - (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 152 #define IEEE80211_CHAN_ALLTURBOFULL \ 153 (IEEE80211_CHAN_ALLTURBO - \ 154 (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 155 156 typedef struct { 157 uint32_t halChanSpreadSupport : 1, 158 halSleepAfterBeaconBroken : 1, 159 halCompressSupport : 1, 160 halBurstSupport : 1, 161 halFastFramesSupport : 1, 162 halChapTuningSupport : 1, 163 halTurboGSupport : 1, 164 halTurboPrimeSupport : 1, 165 halMicAesCcmSupport : 1, 166 halMicCkipSupport : 1, 167 halMicTkipSupport : 1, 168 halTkipMicTxRxKeySupport : 1, 169 halCipherAesCcmSupport : 1, 170 halCipherCkipSupport : 1, 171 halCipherTkipSupport : 1, 172 halPSPollBroken : 1, 173 halVEOLSupport : 1, 174 halBssIdMaskSupport : 1, 175 halMcastKeySrchSupport : 1, 176 halTsfAddSupport : 1, 177 halChanHalfRate : 1, 178 halChanQuarterRate : 1, 179 halHTSupport : 1, 180 halRfSilentSupport : 1, 181 halHwPhyCounterSupport : 1, 182 halWowSupport : 1, 183 halWowMatchPatternExact : 1, 184 halAutoSleepSupport : 1, 185 halFastCCSupport : 1, 186 halBtCoexSupport : 1; 187 uint32_t halRxStbcSupport : 1, 188 halTxStbcSupport : 1, 189 halGTTSupport : 1, 190 halCSTSupport : 1, 191 halRifsRxSupport : 1, 192 halRifsTxSupport : 1, 193 halExtChanDfsSupport : 1, 194 halForcePpmSupport : 1, 195 halEnhancedPmSupport : 1, 196 halMbssidAggrSupport : 1, 197 halBssidMatchSupport : 1; 198 uint32_t halWirelessModes; 199 uint16_t halTotalQueues; 200 uint16_t halKeyCacheSize; 201 uint16_t halLow5GhzChan, halHigh5GhzChan; 202 uint16_t halLow2GhzChan, halHigh2GhzChan; 203 int halTstampPrecision; 204 int halRtsAggrLimit; 205 uint8_t halTxChainMask; 206 uint8_t halRxChainMask; 207 uint8_t halNumGpioPins; 208 uint8_t halNumAntCfg2GHz; 209 uint8_t halNumAntCfg5GHz; 210 uint32_t halIntrMask; 211 } HAL_CAPABILITIES; 212 213 struct regDomain; 214 215 /* 216 * The ``private area'' follows immediately after the ``public area'' 217 * in the data structure returned by ath_hal_attach. Private data are 218 * used by device-independent code such as the regulatory domain support. 219 * In general, code within the HAL should never depend on data in the 220 * public area. Instead any public data needed internally should be 221 * shadowed here. 222 * 223 * When declaring a device-specific ath_hal data structure this structure 224 * is assumed to at the front; e.g. 225 * 226 * struct ath_hal_5212 { 227 * struct ath_hal_private ah_priv; 228 * ... 229 * }; 230 * 231 * It might be better to manage the method pointers in this structure 232 * using an indirect pointer to a read-only data structure but this would 233 * disallow class-style method overriding. 234 */ 235 struct ath_hal_private { 236 struct ath_hal h; /* public area */ 237 238 /* NB: all methods go first to simplify initialization */ 239 HAL_BOOL (*ah_getChannelEdges)(struct ath_hal*, 240 uint16_t channelFlags, 241 uint16_t *lowChannel, uint16_t *highChannel); 242 u_int (*ah_getWirelessModes)(struct ath_hal*); 243 HAL_BOOL (*ah_eepromRead)(struct ath_hal *, u_int off, 244 uint16_t *data); 245 HAL_BOOL (*ah_eepromWrite)(struct ath_hal *, u_int off, 246 uint16_t data); 247 HAL_BOOL (*ah_getChipPowerLimits)(struct ath_hal *, 248 struct ieee80211_channel *); 249 int16_t (*ah_getNfAdjust)(struct ath_hal *, 250 const HAL_CHANNEL_INTERNAL*); 251 void (*ah_getNoiseFloor)(struct ath_hal *, 252 int16_t nfarray[]); 253 254 void *ah_eeprom; /* opaque EEPROM state */ 255 uint16_t ah_eeversion; /* EEPROM version */ 256 void (*ah_eepromDetach)(struct ath_hal *); 257 HAL_STATUS (*ah_eepromGet)(struct ath_hal *, int, void *); 258 HAL_BOOL (*ah_eepromSet)(struct ath_hal *, int, int); 259 uint16_t (*ah_getSpurChan)(struct ath_hal *, int, HAL_BOOL); 260 HAL_BOOL (*ah_eepromDiag)(struct ath_hal *, int request, 261 const void *args, uint32_t argsize, 262 void **result, uint32_t *resultsize); 263 264 /* 265 * Device revision information. 266 */ 267 uint16_t ah_devid; /* PCI device ID */ 268 uint16_t ah_subvendorid; /* PCI subvendor ID */ 269 uint32_t ah_macVersion; /* MAC version id */ 270 uint16_t ah_macRev; /* MAC revision */ 271 uint16_t ah_phyRev; /* PHY revision */ 272 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 273 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 274 uint8_t ah_ispcie; /* PCIE, special treatment */ 275 276 HAL_OPMODE ah_opmode; /* operating mode from reset */ 277 const struct ieee80211_channel *ah_curchan;/* operating channel */ 278 HAL_CAPABILITIES ah_caps; /* device capabilities */ 279 uint32_t ah_diagreg; /* user-specified AR_DIAG_SW */ 280 int16_t ah_powerLimit; /* tx power cap */ 281 uint16_t ah_maxPowerLevel; /* calculated max tx power */ 282 u_int ah_tpScale; /* tx power scale factor */ 283 uint32_t ah_11nCompat; /* 11n compat controls */ 284 285 /* 286 * State for regulatory domain handling. 287 */ 288 HAL_REG_DOMAIN ah_currentRD; /* EEPROM regulatory domain */ 289 HAL_CHANNEL_INTERNAL ah_channels[AH_MAXCHAN]; /* private chan state */ 290 u_int ah_nchan; /* valid items in ah_channels */ 291 const struct regDomain *ah_rd2GHz; /* reg state for 2G band */ 292 const struct regDomain *ah_rd5GHz; /* reg state for 5G band */ 293 294 uint8_t ah_coverageClass; /* coverage class */ 295 /* 296 * RF Silent handling; setup according to the EEPROM. 297 */ 298 uint16_t ah_rfsilent; /* GPIO pin + polarity */ 299 HAL_BOOL ah_rfkillEnabled; /* enable/disable RfKill */ 300 /* 301 * Diagnostic support for discriminating HIUERR reports. 302 */ 303 uint32_t ah_fatalState[6]; /* AR_ISR+shadow regs */ 304 int ah_rxornIsFatal; /* how to treat HAL_INT_RXORN */ 305 }; 306 307 #define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah)) 308 309 #define ath_hal_getChannelEdges(_ah, _cf, _lc, _hc) \ 310 AH_PRIVATE(_ah)->ah_getChannelEdges(_ah, _cf, _lc, _hc) 311 #define ath_hal_getWirelessModes(_ah) \ 312 AH_PRIVATE(_ah)->ah_getWirelessModes(_ah) 313 #define ath_hal_eepromRead(_ah, _off, _data) \ 314 AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data) 315 #define ath_hal_eepromWrite(_ah, _off, _data) \ 316 AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data) 317 #define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 318 (_ah)->ah_gpioCfgOutput(_ah, _gpio, _type) 319 #define ath_hal_gpioCfgInput(_ah, _gpio) \ 320 (_ah)->ah_gpioCfgInput(_ah, _gpio) 321 #define ath_hal_gpioGet(_ah, _gpio) \ 322 (_ah)->ah_gpioGet(_ah, _gpio) 323 #define ath_hal_gpioSet(_ah, _gpio, _val) \ 324 (_ah)->ah_gpioSet(_ah, _gpio, _val) 325 #define ath_hal_gpioSetIntr(_ah, _gpio, _ilevel) \ 326 (_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel) 327 #define ath_hal_getpowerlimits(_ah, _chan) \ 328 AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chan) 329 #define ath_hal_getNfAdjust(_ah, _c) \ 330 AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c) 331 #define ath_hal_getNoiseFloor(_ah, _nfArray) \ 332 AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray) 333 #define ath_hal_configPCIE(_ah, _reset) \ 334 (_ah)->ah_configPCIE(_ah, _reset) 335 #define ath_hal_disablePCIE(_ah) \ 336 (_ah)->ah_disablePCIE(_ah) 337 #define ath_hal_setInterrupts(_ah, _mask) \ 338 (_ah)->ah_setInterrupts(_ah, _mask) 339 340 #define ath_hal_eepromDetach(_ah) do { \ 341 if (AH_PRIVATE(_ah)->ah_eepromDetach != AH_NULL) \ 342 AH_PRIVATE(_ah)->ah_eepromDetach(_ah); \ 343 } while (0) 344 #define ath_hal_eepromGet(_ah, _param, _val) \ 345 AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val) 346 #define ath_hal_eepromSet(_ah, _param, _val) \ 347 AH_PRIVATE(_ah)->ah_eepromSet(_ah, _param, _val) 348 #define ath_hal_eepromGetFlag(_ah, _param) \ 349 (AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, AH_NULL) == HAL_OK) 350 #define ath_hal_getSpurChan(_ah, _ix, _is2G) \ 351 AH_PRIVATE(_ah)->ah_getSpurChan(_ah, _ix, _is2G) 352 #define ath_hal_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) \ 353 AH_PRIVATE(_ah)->ah_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) 354 355 #ifndef _NET_IF_IEEE80211_H_ 356 /* 357 * Stuff that would naturally come from _ieee80211.h 358 */ 359 #define IEEE80211_ADDR_LEN 6 360 361 #define IEEE80211_WEP_IVLEN 3 /* 24bit */ 362 #define IEEE80211_WEP_KIDLEN 1 /* 1 octet */ 363 #define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */ 364 365 #define IEEE80211_CRC_LEN 4 366 367 #define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \ 368 (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN)) 369 #endif /* _NET_IF_IEEE80211_H_ */ 370 371 #define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 372 373 #define INIT_AIFS 2 374 #define INIT_CWMIN 15 375 #define INIT_CWMIN_11B 31 376 #define INIT_CWMAX 1023 377 #define INIT_SH_RETRY 10 378 #define INIT_LG_RETRY 10 379 #define INIT_SSH_RETRY 32 380 #define INIT_SLG_RETRY 32 381 382 typedef struct { 383 uint32_t tqi_ver; /* HAL TXQ verson */ 384 HAL_TX_QUEUE tqi_type; /* hw queue type*/ 385 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* queue subtype, if applicable */ 386 HAL_TX_QUEUE_FLAGS tqi_qflags; /* queue flags */ 387 uint32_t tqi_priority; 388 uint32_t tqi_aifs; /* aifs */ 389 uint32_t tqi_cwmin; /* cwMin */ 390 uint32_t tqi_cwmax; /* cwMax */ 391 uint16_t tqi_shretry; /* frame short retry limit */ 392 uint16_t tqi_lgretry; /* frame long retry limit */ 393 uint32_t tqi_cbrPeriod; 394 uint32_t tqi_cbrOverflowLimit; 395 uint32_t tqi_burstTime; 396 uint32_t tqi_readyTime; 397 uint32_t tqi_physCompBuf; 398 uint32_t tqi_intFlags; /* flags for internal use */ 399 } HAL_TX_QUEUE_INFO; 400 401 extern HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah, 402 HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo); 403 extern HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah, 404 HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi); 405 406 typedef enum { 407 HAL_ANI_PRESENT, /* is ANI support present */ 408 HAL_ANI_NOISE_IMMUNITY_LEVEL, /* set level */ 409 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION, /* enable/disable */ 410 HAL_ANI_CCK_WEAK_SIGNAL_THR, /* enable/disable */ 411 HAL_ANI_FIRSTEP_LEVEL, /* set level */ 412 HAL_ANI_SPUR_IMMUNITY_LEVEL, /* set level */ 413 HAL_ANI_MODE = 6, /* 0 => manual, 1 => auto (XXX do not change) */ 414 HAL_ANI_PHYERR_RESET, /* reset phy error stats */ 415 } HAL_ANI_CMD; 416 417 #define HAL_SPUR_VAL_MASK 0x3FFF 418 #define HAL_SPUR_CHAN_WIDTH 87 419 #define HAL_BIN_WIDTH_BASE_100HZ 3125 420 #define HAL_BIN_WIDTH_TURBO_100HZ 6250 421 #define HAL_MAX_BINS_ALLOWED 28 422 423 #define IS_CHAN_5GHZ(_c) ((_c)->channel > 4900) 424 #define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c)) 425 426 #define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990) 427 428 /* 429 * Deduce if the host cpu has big- or litt-endian byte order. 430 */ 431 static __inline__ int 432 isBigEndian(void) 433 { 434 union { 435 int32_t i; 436 char c[4]; 437 } u; 438 u.i = 1; 439 return (u.c[0] == 0); 440 } 441 442 /* unalligned little endian access */ 443 #define LE_READ_2(p) \ 444 ((uint16_t) \ 445 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8))) 446 #define LE_READ_4(p) \ 447 ((uint32_t) \ 448 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8) |\ 449 (((const uint8_t *)(p))[2]<<16) | (((const uint8_t *)(p))[3]<<24))) 450 451 /* 452 * Register manipulation macros that expect bit field defines 453 * to follow the convention that an _S suffix is appended for 454 * a shift count, while the field mask has no suffix. 455 */ 456 #define SM(_v, _f) (((_v) << _f##_S) & (_f)) 457 #define MS(_v, _f) (((_v) & (_f)) >> _f##_S) 458 #define OS_REG_RMW_FIELD(_a, _r, _f, _v) \ 459 OS_REG_WRITE(_a, _r, \ 460 (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) 461 #define OS_REG_SET_BIT(_a, _r, _f) \ 462 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | (_f)) 463 #define OS_REG_CLR_BIT(_a, _r, _f) \ 464 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f)) 465 466 /* system-configurable parameters */ 467 extern int ath_hal_dma_beacon_response_time; /* in TU's */ 468 extern int ath_hal_sw_beacon_response_time; /* in TU's */ 469 extern int ath_hal_additional_swba_backoff; /* in TU's */ 470 471 /* wait for the register contents to have the specified value */ 472 extern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg, 473 uint32_t mask, uint32_t val); 474 475 /* return the first n bits in val reversed */ 476 extern uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n); 477 478 /* printf interfaces */ 479 extern void ath_hal_printf(struct ath_hal *, const char*, ...) 480 __printflike(2,3); 481 extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list) 482 __printflike(2, 0); 483 extern const char* ath_hal_ether_sprintf(const uint8_t *mac); 484 485 /* allocate and free memory */ 486 extern void *ath_hal_malloc(size_t); 487 extern void ath_hal_free(void *); 488 489 /* common debugging interfaces */ 490 #ifdef AH_DEBUG 491 #include "ah_debug.h" 492 extern int ath_hal_debug; 493 extern void HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...) 494 __printflike(3,4); 495 #else 496 #define HALDEBUG(_ah, __m, _fmt, ...) 497 #endif /* AH_DEBUG */ 498 499 /* 500 * Register logging definitions shared with ardecode. 501 */ 502 #include "ah_decode.h" 503 504 /* 505 * Common assertion interface. Note: it is a bad idea to generate 506 * an assertion failure for any recoverable event. Instead catch 507 * the violation and, if possible, fix it up or recover from it; either 508 * with an error return value or a diagnostic messages. System software 509 * does not panic unless the situation is hopeless. 510 */ 511 #ifdef AH_ASSERT 512 extern void ath_hal_assert_failed(const char* filename, 513 int lineno, const char* msg); 514 515 #define HALASSERT(_x) do { \ 516 if (!(_x)) { \ 517 ath_hal_assert_failed(__FILE__, __LINE__, #_x); \ 518 } \ 519 } while (0) 520 #else 521 #define HALASSERT(_x) 522 #endif /* AH_ASSERT */ 523 524 /* 525 * Regulatory domain support. 526 */ 527 528 /* 529 * Return the max allowed antenna gain and apply any regulatory 530 * domain specific changes. 531 */ 532 u_int ath_hal_getantennareduction(struct ath_hal *ah, 533 const struct ieee80211_channel *chan, u_int twiceGain); 534 535 /* 536 * Return the test group for the specific channel based on 537 * the current regulatory setup. 538 */ 539 u_int ath_hal_getctl(struct ath_hal *, const struct ieee80211_channel *); 540 541 /* 542 * Map a public channel definition to the corresponding 543 * internal data structure. This implicitly specifies 544 * whether or not the specified channel is ok to use 545 * based on the current regulatory domain constraints. 546 */ 547 #ifndef AH_DEBUG 548 static OS_INLINE HAL_CHANNEL_INTERNAL * 549 ath_hal_checkchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 550 { 551 HAL_CHANNEL_INTERNAL *cc; 552 553 HALASSERT(c->ic_devdata < AH_PRIVATE(ah)->ah_nchan); 554 cc = &AH_PRIVATE(ah)->ah_channels[c->ic_devdata]; 555 HALASSERT(c->ic_freq == cc->channel || IEEE80211_IS_CHAN_GSM(c)); 556 return cc; 557 } 558 #else 559 /* NB: non-inline version that checks state */ 560 HAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *, 561 const struct ieee80211_channel *); 562 #endif /* AH_DEBUG */ 563 564 /* 565 * Return the h/w frequency for a channel. This may be 566 * different from ic_freq if this is a GSM device that 567 * takes 2.4GHz frequencies and down-converts them. 568 */ 569 static OS_INLINE uint16_t 570 ath_hal_gethwchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 571 { 572 return ath_hal_checkchannel(ah, c)->channel; 573 } 574 575 /* 576 * Convert between microseconds and core system clocks. 577 */ 578 extern u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs); 579 extern u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks); 580 581 /* 582 * Generic get/set capability support. Each chip overrides 583 * this routine to support chip-specific capabilities. 584 */ 585 extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah, 586 HAL_CAPABILITY_TYPE type, uint32_t capability, 587 uint32_t *result); 588 extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah, 589 HAL_CAPABILITY_TYPE type, uint32_t capability, 590 uint32_t setting, HAL_STATUS *status); 591 592 /* 593 * Diagnostic interface. This is an open-ended interface that 594 * is opaque to applications. Diagnostic programs use this to 595 * retrieve internal data structures, etc. There is no guarantee 596 * that calling conventions for calls other than HAL_DIAG_REVS 597 * are stable between HAL releases; a diagnostic application must 598 * use the HAL revision information to deal with ABI/API differences. 599 * 600 * NB: do not renumber these, certain codes are publicly used. 601 */ 602 enum { 603 HAL_DIAG_REVS = 0, /* MAC/PHY/Radio revs */ 604 HAL_DIAG_EEPROM = 1, /* EEPROM contents */ 605 HAL_DIAG_EEPROM_EXP_11A = 2, /* EEPROM 5112 power exp for 11a */ 606 HAL_DIAG_EEPROM_EXP_11B = 3, /* EEPROM 5112 power exp for 11b */ 607 HAL_DIAG_EEPROM_EXP_11G = 4, /* EEPROM 5112 power exp for 11g */ 608 HAL_DIAG_ANI_CURRENT = 5, /* ANI current channel state */ 609 HAL_DIAG_ANI_OFDM = 6, /* ANI OFDM timing error stats */ 610 HAL_DIAG_ANI_CCK = 7, /* ANI CCK timing error stats */ 611 HAL_DIAG_ANI_STATS = 8, /* ANI statistics */ 612 HAL_DIAG_RFGAIN = 9, /* RfGain GAIN_VALUES */ 613 HAL_DIAG_RFGAIN_CURSTEP = 10, /* RfGain GAIN_OPTIMIZATION_STEP */ 614 HAL_DIAG_PCDAC = 11, /* PCDAC table */ 615 HAL_DIAG_TXRATES = 12, /* Transmit rate table */ 616 HAL_DIAG_REGS = 13, /* Registers */ 617 HAL_DIAG_ANI_CMD = 14, /* ANI issue command (XXX do not change!) */ 618 HAL_DIAG_SETKEY = 15, /* Set keycache backdoor */ 619 HAL_DIAG_RESETKEY = 16, /* Reset keycache backdoor */ 620 HAL_DIAG_EEREAD = 17, /* Read EEPROM word */ 621 HAL_DIAG_EEWRITE = 18, /* Write EEPROM word */ 622 /* 19-26 removed, do not reuse */ 623 HAL_DIAG_RDWRITE = 27, /* Write regulatory domain */ 624 HAL_DIAG_RDREAD = 28, /* Get regulatory domain */ 625 HAL_DIAG_FATALERR = 29, /* Read cached interrupt state */ 626 HAL_DIAG_11NCOMPAT = 30, /* 11n compatibility tweaks */ 627 HAL_DIAG_ANI_PARAMS = 31, /* ANI noise immunity parameters */ 628 HAL_DIAG_CHECK_HANGS = 32, /* check h/w hangs */ 629 HAL_DIAG_SETREGS = 33, /* write registers */ 630 }; 631 632 enum { 633 HAL_BB_HANG_DFS = 0x0001, 634 HAL_BB_HANG_RIFS = 0x0002, 635 HAL_BB_HANG_RX_CLEAR = 0x0004, 636 HAL_BB_HANG_UNKNOWN = 0x0080, 637 638 HAL_MAC_HANG_SIG1 = 0x0100, 639 HAL_MAC_HANG_SIG2 = 0x0200, 640 HAL_MAC_HANG_UNKNOWN = 0x8000, 641 642 HAL_BB_HANGS = HAL_BB_HANG_DFS 643 | HAL_BB_HANG_RIFS 644 | HAL_BB_HANG_RX_CLEAR 645 | HAL_BB_HANG_UNKNOWN, 646 HAL_MAC_HANGS = HAL_MAC_HANG_SIG1 647 | HAL_MAC_HANG_SIG2 648 | HAL_MAC_HANG_UNKNOWN, 649 }; 650 651 /* 652 * Device revision information. 653 */ 654 typedef struct { 655 uint16_t ah_devid; /* PCI device ID */ 656 uint16_t ah_subvendorid; /* PCI subvendor ID */ 657 uint32_t ah_macVersion; /* MAC version id */ 658 uint16_t ah_macRev; /* MAC revision */ 659 uint16_t ah_phyRev; /* PHY revision */ 660 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 661 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 662 } HAL_REVS; 663 664 /* 665 * Argument payload for HAL_DIAG_SETKEY. 666 */ 667 typedef struct { 668 HAL_KEYVAL dk_keyval; 669 uint16_t dk_keyix; /* key index */ 670 uint8_t dk_mac[IEEE80211_ADDR_LEN]; 671 int dk_xor; /* XOR key data */ 672 } HAL_DIAG_KEYVAL; 673 674 /* 675 * Argument payload for HAL_DIAG_EEWRITE. 676 */ 677 typedef struct { 678 uint16_t ee_off; /* eeprom offset */ 679 uint16_t ee_data; /* write data */ 680 } HAL_DIAG_EEVAL; 681 682 683 typedef struct { 684 u_int offset; /* reg offset */ 685 uint32_t val; /* reg value */ 686 } HAL_DIAG_REGVAL; 687 688 /* 689 * 11n compatibility tweaks. 690 */ 691 #define HAL_DIAG_11N_SERVICES 0x00000003 692 #define HAL_DIAG_11N_SERVICES_S 0 693 #define HAL_DIAG_11N_TXSTOMP 0x0000000c 694 #define HAL_DIAG_11N_TXSTOMP_S 2 695 696 typedef struct { 697 int maxNoiseImmunityLevel; /* [0..4] */ 698 int totalSizeDesired[5]; 699 int coarseHigh[5]; 700 int coarseLow[5]; 701 int firpwr[5]; 702 703 int maxSpurImmunityLevel; /* [0..7] */ 704 int cycPwrThr1[8]; 705 706 int maxFirstepLevel; /* [0..2] */ 707 int firstep[3]; 708 709 uint32_t ofdmTrigHigh; 710 uint32_t ofdmTrigLow; 711 int32_t cckTrigHigh; 712 int32_t cckTrigLow; 713 int32_t rssiThrLow; 714 int32_t rssiThrHigh; 715 716 int period; /* update listen period */ 717 } HAL_ANI_PARAMS; 718 719 extern HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request, 720 const void *args, uint32_t argsize, 721 void **result, uint32_t *resultsize); 722 723 /* 724 * Setup a h/w rate table for use. 725 */ 726 extern void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt); 727 728 /* 729 * Common routine for implementing getChanNoise api. 730 */ 731 int16_t ath_hal_getChanNoise(struct ath_hal *, const struct ieee80211_channel *); 732 733 /* 734 * Initialization support. 735 */ 736 typedef struct { 737 const uint32_t *data; 738 int rows, cols; 739 } HAL_INI_ARRAY; 740 741 #define HAL_INI_INIT(_ia, _data, _cols) do { \ 742 (_ia)->data = (const uint32_t *)(_data); \ 743 (_ia)->rows = sizeof(_data) / sizeof((_data)[0]); \ 744 (_ia)->cols = (_cols); \ 745 } while (0) 746 #define HAL_INI_VAL(_ia, _r, _c) \ 747 ((_ia)->data[((_r)*(_ia)->cols) + (_c)]) 748 749 /* 750 * OS_DELAY() does a PIO READ on the PCI bus which allows 751 * other cards' DMA reads to complete in the middle of our reset. 752 */ 753 #define DMA_YIELD(x) do { \ 754 if ((++(x) % 64) == 0) \ 755 OS_DELAY(1); \ 756 } while (0) 757 758 #define HAL_INI_WRITE_ARRAY(ah, regArray, col, regWr) do { \ 759 int r; \ 760 for (r = 0; r < N(regArray); r++) { \ 761 OS_REG_WRITE(ah, (regArray)[r][0], (regArray)[r][col]); \ 762 DMA_YIELD(regWr); \ 763 } \ 764 } while (0) 765 766 #define HAL_INI_WRITE_BANK(ah, regArray, bankData, regWr) do { \ 767 int r; \ 768 for (r = 0; r < N(regArray); r++) { \ 769 OS_REG_WRITE(ah, (regArray)[r][0], (bankData)[r]); \ 770 DMA_YIELD(regWr); \ 771 } \ 772 } while (0) 773 774 extern int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 775 int col, int regWr); 776 extern void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia, 777 int col); 778 extern int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 779 const uint32_t data[], int regWr); 780 781 #define CCK_SIFS_TIME 10 782 #define CCK_PREAMBLE_BITS 144 783 #define CCK_PLCP_BITS 48 784 785 #define OFDM_SIFS_TIME 16 786 #define OFDM_PREAMBLE_TIME 20 787 #define OFDM_PLCP_BITS 22 788 #define OFDM_SYMBOL_TIME 4 789 790 #define OFDM_HALF_SIFS_TIME 32 791 #define OFDM_HALF_PREAMBLE_TIME 40 792 #define OFDM_HALF_PLCP_BITS 22 793 #define OFDM_HALF_SYMBOL_TIME 8 794 795 #define OFDM_QUARTER_SIFS_TIME 64 796 #define OFDM_QUARTER_PREAMBLE_TIME 80 797 #define OFDM_QUARTER_PLCP_BITS 22 798 #define OFDM_QUARTER_SYMBOL_TIME 16 799 800 #define TURBO_SIFS_TIME 8 801 #define TURBO_PREAMBLE_TIME 14 802 #define TURBO_PLCP_BITS 22 803 #define TURBO_SYMBOL_TIME 4 804 805 #define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */ 806 #endif /* _ATH_AH_INTERAL_H_ */ 807