1 /*- 2 * SPDX-License-Identifier: ISC 3 * 4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 5 * Copyright (c) 2002-2008 Atheros Communications, Inc. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 * 19 * $FreeBSD$ 20 */ 21 #ifndef _ATH_AH_EEPROM_V3_H_ 22 #define _ATH_AH_EEPROM_V3_H_ 23 24 #include "ah_eeprom.h" 25 26 /* EEPROM defines for Version 2 & 3 AR5211 chips */ 27 #define AR_EEPROM_RFSILENT 0x0f /* RF Silent/Clock Run Enable */ 28 #define AR_EEPROM_MAC(i) (0x1d+(i)) /* MAC address word */ 29 #define AR_EEPROM_MAGIC 0x3d /* magic number */ 30 #define AR_EEPROM_PROTECT 0x3f /* EEPROM protect bits */ 31 #define AR_EEPROM_PROTECT_PCIE 0x01 /* EEPROM protect bits for Condor/Swan*/ 32 #define AR_EEPROM_REG_DOMAIN 0xbf /* current regulatory domain */ 33 #define AR_EEPROM_ATHEROS_BASE 0xc0 /* Base of Atheros-specific data */ 34 #define AR_EEPROM_ATHEROS(i) (AR_EEPROM_ATHEROS_BASE+(i)) 35 #define AR_EEPROM_ATHEROS_MAX (0x400-AR_EEPROM_ATHEROS_BASE) 36 #define AR_EEPROM_VERSION AR_EEPROM_ATHEROS(1) 37 38 /* FLASH(EEPROM) Defines for AR531X chips */ 39 #define AR_EEPROM_SIZE_LOWER 0x1b /* size info -- lower */ 40 #define AR_EEPROM_SIZE_UPPER 0x1c /* size info -- upper */ 41 #define AR_EEPROM_SIZE_UPPER_MASK 0xfff0 42 #define AR_EEPROM_SIZE_UPPER_SHIFT 4 43 #define AR_EEPROM_SIZE_ENDLOC_SHIFT 12 44 #define AR_EEPROM_ATHEROS_MAX_LOC 0x400 45 #define AR_EEPROM_ATHEROS_MAX_OFF (AR_EEPROM_ATHEROS_MAX_LOC-AR_EEPROM_ATHEROS_BASE) 46 47 /* regulatory capabilities offsets */ 48 #define AR_EEPROM_REG_CAPABILITIES_OFFSET 0xCA 49 #define AR_EEPROM_REG_CAPABILITIES_OFFSET_PRE4_0 0xCF /* prior to 4.0 */ 50 51 /* regulatory capabilities */ 52 #define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040 53 #define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080 54 #define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100 55 #define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200 56 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400 57 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800 58 59 /* regulatory capabilities prior to eeprom version 4.0 */ 60 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000 61 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000 62 63 /* 64 * AR2413 (includes AR5413) 65 */ 66 #define AR_EEPROM_SERIAL_NUM_OFFSET 0xB0 /* EEPROM serial number */ 67 #define AR_EEPROM_SERIAL_NUM_SIZE 12 /* EEPROM serial number size */ 68 #define AR_EEPROM_CAPABILITIES_OFFSET 0xC9 /* EEPROM Location of capabilities */ 69 70 #define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001 71 #define AR_EEPROM_EEPCAP_AES_DIS 0x0002 72 #define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004 73 #define AR_EEPROM_EEPCAP_BURST_DIS 0x0008 74 #define AR_EEPROM_EEPCAP_MAXQCU 0x01F0 75 #define AR_EEPROM_EEPCAP_MAXQCU_S 4 76 #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200 77 #define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000 78 #define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12 79 80 /* XXX used to index various EEPROM-derived data structures */ 81 enum { 82 headerInfo11A = 0, 83 headerInfo11B = 1, 84 headerInfo11G = 2, 85 }; 86 87 #define GROUPS_OFFSET3_2 0x100 /* groups offset for ver3.2 and earlier */ 88 #define GROUPS_OFFSET3_3 0x150 /* groups offset for ver3.3 */ 89 /* relative offset of GROUPi to GROUPS_OFFSET */ 90 #define GROUP1_OFFSET 0x0 91 #define GROUP2_OFFSET 0x5 92 #define GROUP3_OFFSET 0x37 93 #define GROUP4_OFFSET 0x46 94 #define GROUP5_OFFSET 0x55 95 #define GROUP6_OFFSET 0x65 96 #define GROUP7_OFFSET 0x69 97 #define GROUP8_OFFSET 0x6f 98 99 /* RF silent fields in EEPROM */ 100 #define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c 101 #define AR_EEPROM_RFSILENT_GPIO_SEL_S 2 102 #define AR_EEPROM_RFSILENT_POLARITY 0x0002 103 #define AR_EEPROM_RFSILENT_POLARITY_S 1 104 105 /* Protect Bits RP is read protect, WP is write protect */ 106 #define AR_EEPROM_PROTECT_RP_0_31 0x0001 107 #define AR_EEPROM_PROTECT_WP_0_31 0x0002 108 #define AR_EEPROM_PROTECT_RP_32_63 0x0004 109 #define AR_EEPROM_PROTECT_WP_32_63 0x0008 110 #define AR_EEPROM_PROTECT_RP_64_127 0x0010 111 #define AR_EEPROM_PROTECT_WP_64_127 0x0020 112 #define AR_EEPROM_PROTECT_RP_128_191 0x0040 113 #define AR_EEPROM_PROTECT_WP_128_191 0x0080 114 #define AR_EEPROM_PROTECT_RP_192_207 0x0100 115 #define AR_EEPROM_PROTECT_WP_192_207 0x0200 116 #define AR_EEPROM_PROTECT_RP_208_223 0x0400 117 #define AR_EEPROM_PROTECT_WP_208_223 0x0800 118 #define AR_EEPROM_PROTECT_RP_224_239 0x1000 119 #define AR_EEPROM_PROTECT_WP_224_239 0x2000 120 #define AR_EEPROM_PROTECT_RP_240_255 0x4000 121 #define AR_EEPROM_PROTECT_WP_240_255 0x8000 122 123 #define AR_EEPROM_MODAL_SPURS 5 124 #define AR_SPUR_5413_1 1640 /* Freq 2464 */ 125 #define AR_SPUR_5413_2 1200 /* Freq 2420 */ 126 127 /* 128 * EEPROM fixed point conversion scale factors. 129 * NB: if you change one be sure to keep the other in sync. 130 */ 131 #define EEP_SCALE 100 /* conversion scale to avoid fp arith */ 132 #define EEP_DELTA 10 /* SCALE/10, to avoid arith divide */ 133 134 #define PWR_MIN 0 135 #define PWR_MAX 3150 /* 31.5 * SCALE */ 136 #define PWR_STEP 50 /* 0.5 * SCALE */ 137 /* Keep 2 above defines together */ 138 139 #define NUM_11A_EEPROM_CHANNELS 10 140 #define NUM_2_4_EEPROM_CHANNELS 3 141 #define NUM_PCDAC_VALUES 11 142 #define NUM_TEST_FREQUENCIES 8 143 #define NUM_EDGES 8 144 #define NUM_INTERCEPTS 11 145 #define FREQ_MASK 0x7f 146 #define FREQ_MASK_3_3 0xff /* expanded in version 3.3 */ 147 #define PCDAC_MASK 0x3f 148 #define POWER_MASK 0x3f 149 #define NON_EDGE_FLAG_MASK 0x40 150 #define CHANNEL_POWER_INFO 8 151 #define OBDB_UNSET 0xffff 152 #define CHANNEL_UNUSED 0xff 153 #define SCALE_OC_DELTA(_x) (((_x) * 2) / 10) 154 155 /* Used during pcdac table construction */ 156 #define PCDAC_START 1 157 #define PCDAC_STOP 63 158 #define PCDAC_STEP 1 159 #define PWR_TABLE_SIZE 64 160 #define MAX_RATE_POWER 63 161 162 /* Used during power/rate table construction */ 163 #define NUM_CTLS 16 164 #define NUM_CTLS_3_3 32 /* expanded in version 3.3 */ 165 #define NUM_CTLS_MAX NUM_CTLS_3_3 166 167 typedef struct fullPcdacStruct { 168 uint16_t channelValue; 169 uint16_t pcdacMin; 170 uint16_t pcdacMax; 171 uint16_t numPcdacValues; 172 uint16_t PcdacValues[64]; 173 /* power is 32bit since in dest it is scaled */ 174 int16_t PwrValues[64]; 175 } FULL_PCDAC_STRUCT; 176 177 typedef struct dataPerChannel { 178 uint16_t channelValue; 179 uint16_t pcdacMin; 180 uint16_t pcdacMax; 181 uint16_t numPcdacValues; 182 uint16_t PcdacValues[NUM_PCDAC_VALUES]; 183 /* NB: power is 32bit since in dest it is scaled */ 184 int16_t PwrValues[NUM_PCDAC_VALUES]; 185 } DATA_PER_CHANNEL; 186 187 /* points to the appropriate pcdac structs in the above struct based on mode */ 188 typedef struct pcdacsEeprom { 189 const uint16_t *pChannelList; 190 uint16_t numChannels; 191 const DATA_PER_CHANNEL *pDataPerChannel; 192 } PCDACS_EEPROM; 193 194 typedef struct trgtPowerInfo { 195 uint16_t twicePwr54; 196 uint16_t twicePwr48; 197 uint16_t twicePwr36; 198 uint16_t twicePwr6_24; 199 uint16_t testChannel; 200 } TRGT_POWER_INFO; 201 202 typedef struct trgtPowerAllModes { 203 uint16_t numTargetPwr_11a; 204 TRGT_POWER_INFO trgtPwr_11a[NUM_TEST_FREQUENCIES]; 205 uint16_t numTargetPwr_11g; 206 TRGT_POWER_INFO trgtPwr_11g[3]; 207 uint16_t numTargetPwr_11b; 208 TRGT_POWER_INFO trgtPwr_11b[2]; 209 } TRGT_POWER_ALL_MODES; 210 211 typedef struct cornerCalInfo { 212 uint16_t gSel; 213 uint16_t pd84; 214 uint16_t pd90; 215 uint16_t clip; 216 } CORNER_CAL_INFO; 217 218 /* 219 * EEPROM version 4 definitions 220 */ 221 #define NUM_XPD_PER_CHANNEL 4 222 #define NUM_POINTS_XPD0 4 223 #define NUM_POINTS_XPD3 3 224 #define IDEAL_10dB_INTERCEPT_2G 35 225 #define IDEAL_10dB_INTERCEPT_5G 55 226 227 #define TENX_OFDM_CCK_DELTA_INIT 15 /* power 1.5 dbm */ 228 #define TENX_CH14_FILTER_CCK_DELTA_INIT 15 /* power 1.5 dbm */ 229 #define CCK_OFDM_GAIN_DELTA 15 230 231 #define NUM_TARGET_POWER_LOCATIONS_11B 4 232 #define NUM_TARGET_POWER_LOCATIONS_11G 6 233 234 235 typedef struct { 236 uint16_t xpd_gain; 237 uint16_t numPcdacs; 238 uint16_t pcdac[NUM_POINTS_XPD0]; 239 int16_t pwr_t4[NUM_POINTS_XPD0]; /* or gainF */ 240 } EXPN_DATA_PER_XPD_5112; 241 242 typedef struct { 243 uint16_t channelValue; 244 int16_t maxPower_t4; 245 EXPN_DATA_PER_XPD_5112 pDataPerXPD[NUM_XPD_PER_CHANNEL]; 246 } EXPN_DATA_PER_CHANNEL_5112; 247 248 typedef struct { 249 uint16_t *pChannels; 250 uint16_t numChannels; 251 uint16_t xpdMask; /* mask of permitted xpd_gains */ 252 EXPN_DATA_PER_CHANNEL_5112 *pDataPerChannel; 253 } EEPROM_POWER_EXPN_5112; 254 255 typedef struct { 256 uint16_t channelValue; 257 uint16_t pcd1_xg0; 258 int16_t pwr1_xg0; 259 uint16_t pcd2_delta_xg0; 260 int16_t pwr2_xg0; 261 uint16_t pcd3_delta_xg0; 262 int16_t pwr3_xg0; 263 uint16_t pcd4_delta_xg0; 264 int16_t pwr4_xg0; 265 int16_t maxPower_t4; 266 int16_t pwr1_xg3; /* pcdac = 20 */ 267 int16_t pwr2_xg3; /* pcdac = 35 */ 268 int16_t pwr3_xg3; /* pcdac = 63 */ 269 /* XXX - Should be pwr1_xg2, etc to agree with documentation */ 270 } EEPROM_DATA_PER_CHANNEL_5112; 271 272 typedef struct { 273 uint16_t pChannels[NUM_11A_EEPROM_CHANNELS]; 274 uint16_t numChannels; 275 uint16_t xpdMask; /* mask of permitted xpd_gains */ 276 EEPROM_DATA_PER_CHANNEL_5112 pDataPerChannel[NUM_11A_EEPROM_CHANNELS]; 277 } EEPROM_POWER_5112; 278 279 /* 280 * EEPROM version 5 definitions (Griffin, et. al.). 281 */ 282 #define NUM_2_4_EEPROM_CHANNELS_2413 4 283 #define NUM_11A_EEPROM_CHANNELS_2413 10 284 #define PWR_TABLE_SIZE_2413 128 285 286 /* Used during pdadc construction */ 287 #define MAX_NUM_PDGAINS_PER_CHANNEL 4 288 #define NUM_PDGAINS_PER_CHANNEL 2 289 #define NUM_POINTS_LAST_PDGAIN 5 290 #define NUM_POINTS_OTHER_PDGAINS 4 291 #define XPD_GAIN1_GEN5 3 292 #define XPD_GAIN2_GEN5 1 293 #define MAX_PWR_RANGE_IN_HALF_DB 64 294 #define PD_GAIN_BOUNDARY_STRETCH_IN_HALF_DB 4 295 296 typedef struct { 297 uint16_t pd_gain; 298 uint16_t numVpd; 299 uint16_t Vpd[NUM_POINTS_LAST_PDGAIN]; 300 int16_t pwr_t4[NUM_POINTS_LAST_PDGAIN]; /* or gainF */ 301 } RAW_DATA_PER_PDGAIN_2413; 302 303 typedef struct { 304 uint16_t channelValue; 305 int16_t maxPower_t4; 306 uint16_t numPdGains; /* # Pd Gains per channel */ 307 RAW_DATA_PER_PDGAIN_2413 pDataPerPDGain[MAX_NUM_PDGAINS_PER_CHANNEL]; 308 } RAW_DATA_PER_CHANNEL_2413; 309 310 /* XXX: assumes NUM_11A_EEPROM_CHANNELS_2413 >= NUM_2_4_EEPROM_CHANNELS_2413 ??? */ 311 typedef struct { 312 uint16_t pChannels[NUM_11A_EEPROM_CHANNELS_2413]; 313 uint16_t numChannels; 314 uint16_t xpd_mask; /* mask of permitted xpd_gains */ 315 RAW_DATA_PER_CHANNEL_2413 pDataPerChannel[NUM_11A_EEPROM_CHANNELS_2413]; 316 } RAW_DATA_STRUCT_2413; 317 318 typedef struct { 319 uint16_t channelValue; 320 uint16_t numPdGains; 321 uint16_t Vpd_I[MAX_NUM_PDGAINS_PER_CHANNEL]; 322 int16_t pwr_I[MAX_NUM_PDGAINS_PER_CHANNEL]; 323 uint16_t Vpd_delta[NUM_POINTS_LAST_PDGAIN] 324 [MAX_NUM_PDGAINS_PER_CHANNEL]; 325 int16_t pwr_delta_t2[NUM_POINTS_LAST_PDGAIN] 326 [MAX_NUM_PDGAINS_PER_CHANNEL]; 327 int16_t maxPower_t4; 328 } EEPROM_DATA_PER_CHANNEL_2413; 329 330 typedef struct { 331 uint16_t pChannels[NUM_11A_EEPROM_CHANNELS_2413]; 332 uint16_t numChannels; 333 uint16_t xpd_mask; /* mask of permitted xpd_gains */ 334 EEPROM_DATA_PER_CHANNEL_2413 pDataPerChannel[NUM_11A_EEPROM_CHANNELS_2413]; 335 } EEPROM_DATA_STRUCT_2413; 336 337 /* 338 * Information retrieved from EEPROM. 339 */ 340 typedef struct { 341 uint16_t ee_version; /* Version field */ 342 uint16_t ee_protect; /* EEPROM protect field */ 343 uint16_t ee_regdomain; /* Regulatory domain */ 344 345 /* General Device Parameters */ 346 uint16_t ee_turbo5Disable; 347 uint16_t ee_turbo2Disable; 348 uint16_t ee_rfKill; 349 uint16_t ee_deviceType; 350 uint16_t ee_turbo2WMaxPower5; 351 uint16_t ee_turbo2WMaxPower2; 352 uint16_t ee_xrTargetPower5; 353 uint16_t ee_xrTargetPower2; 354 uint16_t ee_Amode; 355 uint16_t ee_regCap; 356 uint16_t ee_Bmode; 357 uint16_t ee_Gmode; 358 int8_t ee_antennaGainMax[2]; 359 uint16_t ee_xtnd5GSupport; 360 uint8_t ee_cckOfdmPwrDelta; 361 uint8_t ee_exist32kHzCrystal; 362 uint16_t ee_targetPowersStart; 363 uint16_t ee_fixedBias5; 364 uint16_t ee_fixedBias2; 365 uint16_t ee_cckOfdmGainDelta; 366 uint16_t ee_scaledCh14FilterCckDelta; 367 uint16_t ee_eepMap; 368 uint16_t ee_earStart; 369 370 /* 5 GHz / 2.4 GHz CKK / 2.4 GHz OFDM common parameters */ 371 uint16_t ee_switchSettling[3]; 372 uint16_t ee_txrxAtten[3]; 373 uint16_t ee_txEndToXLNAOn[3]; 374 uint16_t ee_thresh62[3]; 375 uint16_t ee_txEndToXPAOff[3]; 376 uint16_t ee_txFrameToXPAOn[3]; 377 int8_t ee_adcDesiredSize[3]; /* 8-bit signed value */ 378 int8_t ee_pgaDesiredSize[3]; /* 8-bit signed value */ 379 int16_t ee_noiseFloorThresh[3]; 380 uint16_t ee_xlnaGain[3]; 381 uint16_t ee_xgain[3]; 382 uint16_t ee_xpd[3]; 383 uint16_t ee_antennaControl[11][3]; 384 uint16_t ee_falseDetectBackoff[3]; 385 uint16_t ee_gainI[3]; 386 uint16_t ee_rxtxMargin[3]; 387 388 /* new parameters added for the AR2413 */ 389 HAL_BOOL ee_disableXr5; 390 HAL_BOOL ee_disableXr2; 391 uint16_t ee_eepMap2PowerCalStart; 392 uint16_t ee_capField; 393 394 uint16_t ee_switchSettlingTurbo[2]; 395 uint16_t ee_txrxAttenTurbo[2]; 396 int8_t ee_adcDesiredSizeTurbo[2]; 397 int8_t ee_pgaDesiredSizeTurbo[2]; 398 uint16_t ee_rxtxMarginTurbo[2]; 399 400 /* 5 GHz parameters */ 401 uint16_t ee_ob1; 402 uint16_t ee_db1; 403 uint16_t ee_ob2; 404 uint16_t ee_db2; 405 uint16_t ee_ob3; 406 uint16_t ee_db3; 407 uint16_t ee_ob4; 408 uint16_t ee_db4; 409 410 /* 2.4 GHz parameters */ 411 uint16_t ee_obFor24; 412 uint16_t ee_dbFor24; 413 uint16_t ee_obFor24g; 414 uint16_t ee_dbFor24g; 415 uint16_t ee_ob2GHz[2]; 416 uint16_t ee_db2GHz[2]; 417 uint16_t ee_numCtls; 418 uint16_t ee_ctl[NUM_CTLS_MAX]; 419 uint16_t ee_iqCalI[2]; 420 uint16_t ee_iqCalQ[2]; 421 uint16_t ee_calPier11g[NUM_2_4_EEPROM_CHANNELS]; 422 uint16_t ee_calPier11b[NUM_2_4_EEPROM_CHANNELS]; 423 424 /* corner calibration information */ 425 CORNER_CAL_INFO ee_cornerCal; 426 427 uint16_t ee_opCap; 428 429 /* 11a info */ 430 uint16_t ee_channels11a[NUM_11A_EEPROM_CHANNELS]; 431 uint16_t ee_numChannels11a; 432 DATA_PER_CHANNEL ee_dataPerChannel11a[NUM_11A_EEPROM_CHANNELS]; 433 434 uint16_t ee_numChannels2_4; 435 uint16_t ee_channels11g[NUM_2_4_EEPROM_CHANNELS]; 436 uint16_t ee_channels11b[NUM_2_4_EEPROM_CHANNELS]; 437 uint16_t ee_spurChans[AR_EEPROM_MODAL_SPURS][2]; 438 439 /* 11g info */ 440 DATA_PER_CHANNEL ee_dataPerChannel11g[NUM_2_4_EEPROM_CHANNELS]; 441 442 /* 11b info */ 443 DATA_PER_CHANNEL ee_dataPerChannel11b[NUM_2_4_EEPROM_CHANNELS]; 444 445 TRGT_POWER_ALL_MODES ee_tpow; 446 447 RD_EDGES_POWER ee_rdEdgesPower[NUM_EDGES*NUM_CTLS_MAX]; 448 449 union { 450 EEPROM_POWER_EXPN_5112 eu_modePowerArray5112[3]; 451 RAW_DATA_STRUCT_2413 eu_rawDataset2413[3]; 452 } ee_u; 453 } HAL_EEPROM; 454 455 /* write-around defines */ 456 #define ee_numTargetPwr_11a ee_tpow.numTargetPwr_11a 457 #define ee_trgtPwr_11a ee_tpow.trgtPwr_11a 458 #define ee_numTargetPwr_11g ee_tpow.numTargetPwr_11g 459 #define ee_trgtPwr_11g ee_tpow.trgtPwr_11g 460 #define ee_numTargetPwr_11b ee_tpow.numTargetPwr_11b 461 #define ee_trgtPwr_11b ee_tpow.trgtPwr_11b 462 #define ee_modePowerArray5112 ee_u.eu_modePowerArray5112 463 #define ee_rawDataset2413 ee_u.eu_rawDataset2413 464 #endif /* _ATH_AH_EEPROM_V3_H_ */ 465