1 /* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19 20 #ifndef _DEV_ATH_DESC_H 21 #define _DEV_ATH_DESC_H 22 23 #include "opt_ah.h" /* NB: required for AH_SUPPORT_AR5416 */ 24 25 /* 26 * For now, define this for the structure definitions. 27 * Because of how the HAL / driver module currently builds, 28 * it's not very feasible to build the module without 29 * this defined. The rest of the code (eg in the driver 30 * body) can work fine with these fields being uninitialised; 31 * they'll be initialised to 0 anyway. 32 */ 33 34 #ifndef AH_SUPPORT_AR5416 35 #define AH_SUPPORT_AR5416 1 36 #endif 37 38 /* 39 * Transmit descriptor status. This structure is filled 40 * in only after the tx descriptor process method finds a 41 * ``done'' descriptor; at which point it returns something 42 * other than HAL_EINPROGRESS. 43 * 44 * Note that ts_antenna may not be valid for all h/w. It 45 * should be used only if non-zero. 46 */ 47 struct ath_tx_status { 48 uint16_t ts_seqnum; /* h/w assigned sequence number */ 49 uint16_t ts_pad1[1]; 50 uint32_t ts_tstamp; /* h/w assigned timestamp */ 51 uint8_t ts_status; /* frame status, 0 => xmit ok */ 52 uint8_t ts_rate; /* h/w transmit rate index */ 53 int8_t ts_rssi; /* tx ack RSSI */ 54 uint8_t ts_shortretry; /* # short retries */ 55 uint8_t ts_longretry; /* # long retries */ 56 uint8_t ts_virtcol; /* virtual collision count */ 57 uint8_t ts_antenna; /* antenna information */ 58 uint8_t ts_finaltsi; /* final transmit series index */ 59 #ifdef AH_SUPPORT_AR5416 60 /* 802.11n status */ 61 uint8_t ts_flags; /* misc flags */ 62 uint8_t ts_queue_id; /* AR9300: TX queue id */ 63 uint8_t ts_desc_id; /* AR9300: TX descriptor id */ 64 uint8_t ts_tid; /* TID */ 65 /* #define ts_rssi ts_rssi_combined */ 66 uint32_t ts_ba_low; /* blockack bitmap low */ 67 uint32_t ts_ba_high; /* blockack bitmap high */ 68 uint32_t ts_evm0; /* evm bytes */ 69 uint32_t ts_evm1; 70 uint32_t ts_evm2; 71 int8_t ts_rssi_ctl[3]; /* tx ack RSSI [ctl, chain 0-2] */ 72 int8_t ts_rssi_ext[3]; /* tx ack RSSI [ext, chain 0-2] */ 73 uint8_t ts_pad[2]; 74 #endif /* AH_SUPPORT_AR5416 */ 75 }; 76 77 /* bits found in ts_status */ 78 #define HAL_TXERR_XRETRY 0x01 /* excessive retries */ 79 #define HAL_TXERR_FILT 0x02 /* blocked by tx filtering */ 80 #define HAL_TXERR_FIFO 0x04 /* fifo underrun */ 81 #define HAL_TXERR_XTXOP 0x08 /* txop exceeded */ 82 #define HAL_TXERR_TIMER_EXPIRED 0x10 /* Tx timer expired */ 83 84 /* bits found in ts_flags */ 85 #define HAL_TX_BA 0x01 /* Block Ack seen */ 86 #define HAL_TX_AGGR 0x02 /* Aggregate */ 87 #define HAL_TX_DESC_CFG_ERR 0x10 /* Error in 20/40 desc config */ 88 #define HAL_TX_DATA_UNDERRUN 0x20 /* Tx buffer underrun */ 89 #define HAL_TX_DELIM_UNDERRUN 0x40 /* Tx delimiter underrun */ 90 #define HAL_TX_FAST_TS 0x80 /* Tx locationing timestamp */ 91 92 /* 93 * Receive descriptor status. This structure is filled 94 * in only after the rx descriptor process method finds a 95 * ``done'' descriptor; at which point it returns something 96 * other than HAL_EINPROGRESS. 97 * 98 * If rx_status is zero, then the frame was received ok; 99 * otherwise the error information is indicated and rs_phyerr 100 * contains a phy error code if HAL_RXERR_PHY is set. In general 101 * the frame contents is undefined when an error occurred thought 102 * for some errors (e.g. a decryption error), it may be meaningful. 103 * 104 * Note that the receive timestamp is expanded using the TSF to 105 * at least 15 bits (regardless of what the h/w provides directly). 106 * Newer hardware supports a full 32-bits; use HAL_CAP_32TSTAMP to 107 * find out if the hardware is capable. 108 * 109 * rx_rssi is in units of dbm above the noise floor. This value 110 * is measured during the preamble and PLCP; i.e. with the initial 111 * 4us of detection. The noise floor is typically a consistent 112 * -96dBm absolute power in a 20MHz channel. 113 */ 114 struct ath_rx_status { 115 uint16_t rs_datalen; /* rx frame length */ 116 uint8_t rs_status; /* rx status, 0 => recv ok */ 117 uint8_t rs_phyerr; /* phy error code */ 118 int8_t rs_rssi; /* rx frame RSSI (combined for 11n) */ 119 uint8_t rs_keyix; /* key cache index */ 120 uint8_t rs_rate; /* h/w receive rate index */ 121 uint8_t rs_more; /* more descriptors follow */ 122 uint32_t rs_tstamp; /* h/w assigned timestamp */ 123 uint32_t rs_antenna; /* antenna information */ 124 #ifdef AH_SUPPORT_AR5416 125 /* 802.11n status */ 126 int8_t rs_rssi_ctl[3]; /* rx frame RSSI [ctl, chain 0-2] */ 127 int8_t rs_rssi_ext[3]; /* rx frame RSSI [ext, chain 0-2] */ 128 uint8_t rs_isaggr; /* is part of the aggregate */ 129 uint8_t rs_moreaggr; /* more frames in aggr to follow */ 130 uint16_t rs_flags; /* misc flags */ 131 uint8_t rs_num_delims; /* number of delims in aggr */ 132 uint8_t rs_spare0; /* padding */ 133 uint8_t rs_ness; /* number of extension spatial streams */ 134 uint8_t rs_hw_upload_data_type; /* hw upload format */ 135 uint16_t rs_spare1; 136 uint32_t rs_evm0; /* evm bytes */ 137 uint32_t rs_evm1; 138 uint32_t rs_evm2; 139 uint32_t rs_evm3; /* needed for ar9300 and later */ 140 uint32_t rs_evm4; /* needed for ar9300 and later */ 141 #endif /* AH_SUPPORT_AR5416 */ 142 }; 143 144 /* bits found in rs_status */ 145 #define HAL_RXERR_CRC 0x01 /* CRC error on frame */ 146 #define HAL_RXERR_PHY 0x02 /* PHY error, rs_phyerr is valid */ 147 #define HAL_RXERR_FIFO 0x04 /* fifo overrun */ 148 #define HAL_RXERR_DECRYPT 0x08 /* non-Michael decrypt error */ 149 #define HAL_RXERR_MIC 0x10 /* Michael MIC decrypt error */ 150 #define HAL_RXERR_INCOMP 0x20 /* Rx Desc processing is incomplete */ 151 #define HAL_RXERR_KEYMISS 0x40 /* Key not found in keycache */ 152 153 /* bits found in rs_flags */ 154 #define HAL_RX_MORE 0x0001 /* more descriptors follow */ 155 #define HAL_RX_MORE_AGGR 0x0002 /* more frames in aggr */ 156 #define HAL_RX_GI 0x0004 /* full gi */ 157 #define HAL_RX_2040 0x0008 /* 40 Mhz */ 158 #define HAL_RX_DELIM_CRC_PRE 0x0010 /* crc error in delimiter pre */ 159 #define HAL_RX_DELIM_CRC_POST 0x0020 /* crc error in delim after */ 160 #define HAL_RX_DECRYPT_BUSY 0x0040 /* decrypt was too slow */ 161 #define HAL_RX_HI_RX_CHAIN 0x0080 /* SM power save: hi Rx chain control */ 162 #define HAL_RX_IS_APSD 0x0100 /* Is ASPD trigger frame */ 163 #define HAL_RX_STBC 0x0200 /* Is an STBC frame */ 164 #define HAL_RX_LOC_INFO 0x0400 /* RX locationing information */ 165 166 #define HAL_RX_HW_UPLOAD_DATA 0x1000 /* This is a hardware data frame */ 167 #define HAL_RX_HW_SOUNDING 0x2000 /* Rx sounding frame (TxBF, positioning) */ 168 #define HAL_RX_UPLOAD_VALID 0x4000 /* This hardware data frame is valid */ 169 170 /* 171 * This is the format of RSSI[2] on the AR9285/AR9485. 172 * It encodes the LNA configuration information. 173 * 174 * For boards with an external diversity antenna switch, 175 * HAL_RX_LNA_EXTCFG encodes which configuration was 176 * used (antenna 1 or antenna 2.) This feeds into the 177 * switch table and ensures that the given antenna was 178 * connected to an LNA. 179 */ 180 #define HAL_RX_LNA_LNACFG 0x80 /* 1 = main LNA config used, 0 = ALT */ 181 #define HAL_RX_LNA_EXTCFG 0x40 /* 0 = external diversity ant1, 1 = ant2 */ 182 #define HAL_RX_LNA_CFG_USED 0x30 /* 2 bits; LNA config used on RX */ 183 #define HAL_RX_LNA_CFG_USED_S 4 184 #define HAL_RX_LNA_CFG_MAIN 0x0c /* 2 bits; "Main" LNA config */ 185 #define HAL_RX_LNA_CFG_ALT 0x02 /* 2 bits; "Alt" LNA config */ 186 187 /* 188 * This is the format of RSSI_EXT[2] on the AR9285/AR9485. 189 * It encodes the switch table configuration and fast diversity 190 * value. 191 */ 192 #define HAL_RX_LNA_FASTDIV 0x40 /* 1 = fast diversity measurement done */ 193 #define HAL_RX_LNA_SWITCH_0 0x30 /* 2 bits; sw_0[1:0] */ 194 #define HAL_RX_LNA_SWITCH_COM 0x0f /* 4 bits, sw_com[3:0] */ 195 196 enum { 197 HAL_PHYERR_UNDERRUN = 0, /* Transmit underrun */ 198 HAL_PHYERR_TIMING = 1, /* Timing error */ 199 HAL_PHYERR_PARITY = 2, /* Illegal parity */ 200 HAL_PHYERR_RATE = 3, /* Illegal rate */ 201 HAL_PHYERR_LENGTH = 4, /* Illegal length */ 202 HAL_PHYERR_RADAR = 5, /* Radar detect */ 203 HAL_PHYERR_SERVICE = 6, /* Illegal service */ 204 HAL_PHYERR_TOR = 7, /* Transmit override receive */ 205 /* NB: these are specific to the 5212 and later */ 206 HAL_PHYERR_OFDM_TIMING = 17, /* */ 207 HAL_PHYERR_OFDM_SIGNAL_PARITY = 18, /* */ 208 HAL_PHYERR_OFDM_RATE_ILLEGAL = 19, /* */ 209 HAL_PHYERR_OFDM_LENGTH_ILLEGAL = 20, /* */ 210 HAL_PHYERR_OFDM_POWER_DROP = 21, /* */ 211 HAL_PHYERR_OFDM_SERVICE = 22, /* */ 212 HAL_PHYERR_OFDM_RESTART = 23, /* */ 213 HAL_PHYERR_FALSE_RADAR_EXT = 24, /* */ 214 HAL_PHYERR_CCK_TIMING = 25, /* */ 215 HAL_PHYERR_CCK_HEADER_CRC = 26, /* */ 216 HAL_PHYERR_CCK_RATE_ILLEGAL = 27, /* */ 217 HAL_PHYERR_CCK_SERVICE = 30, /* */ 218 HAL_PHYERR_CCK_RESTART = 31, /* */ 219 HAL_PHYERR_CCK_LENGTH_ILLEGAL = 32, /* */ 220 HAL_PHYERR_CCK_POWER_DROP = 33, /* */ 221 /* AR5416 and later */ 222 HAL_PHYERR_HT_CRC_ERROR = 34, /* */ 223 HAL_PHYERR_HT_LENGTH_ILLEGAL = 35, /* */ 224 HAL_PHYERR_HT_RATE_ILLEGAL = 36, /* */ 225 226 HAL_PHYERR_SPECTRAL = 38, 227 }; 228 229 /* value found in rs_keyix to mark invalid entries */ 230 #define HAL_RXKEYIX_INVALID ((uint8_t) -1) 231 /* value used to specify no encryption key for xmit */ 232 #define HAL_TXKEYIX_INVALID ((u_int) -1) 233 234 /* XXX rs_antenna definitions */ 235 236 /* 237 * Definitions for the software frame/packet descriptors used by 238 * the Atheros HAL. This definition obscures hardware-specific 239 * details from the driver. Drivers are expected to fillin the 240 * portions of a descriptor that are not opaque then use HAL calls 241 * to complete the work. Status for completed frames is returned 242 * in a device-independent format. 243 */ 244 #ifdef AH_SUPPORT_AR5416 245 #define HAL_DESC_HW_SIZE 20 246 #else 247 #define HAL_DESC_HW_SIZE 4 248 #endif /* AH_SUPPORT_AR5416 */ 249 250 struct ath_desc { 251 /* 252 * The following definitions are passed directly 253 * the hardware and managed by the HAL. Drivers 254 * should not touch those elements marked opaque. 255 */ 256 uint32_t ds_link; /* phys address of next descriptor */ 257 uint32_t ds_data; /* phys address of data buffer */ 258 uint32_t ds_ctl0; /* opaque DMA control 0 */ 259 uint32_t ds_ctl1; /* opaque DMA control 1 */ 260 uint32_t ds_hw[HAL_DESC_HW_SIZE]; /* opaque h/w region */ 261 }; 262 263 struct ath_desc_txedma { 264 uint32_t ds_info; 265 uint32_t ds_link; 266 uint32_t ds_hw[21]; /* includes buf/len */ 267 }; 268 269 struct ath_desc_status { 270 union { 271 struct ath_tx_status tx;/* xmit status */ 272 struct ath_rx_status rx;/* recv status */ 273 } ds_us; 274 }; 275 276 #define ds_txstat ds_us.tx 277 #define ds_rxstat ds_us.rx 278 279 /* flags passed to tx descriptor setup methods */ 280 /* This is a uint16_t field in ath_buf, just be warned! */ 281 #define HAL_TXDESC_CLRDMASK 0x0001 /* clear destination filter mask */ 282 #define HAL_TXDESC_NOACK 0x0002 /* don't wait for ACK */ 283 #define HAL_TXDESC_RTSENA 0x0004 /* enable RTS */ 284 #define HAL_TXDESC_CTSENA 0x0008 /* enable CTS */ 285 #define HAL_TXDESC_INTREQ 0x0010 /* enable per-descriptor interrupt */ 286 #define HAL_TXDESC_VEOL 0x0020 /* mark virtual EOL */ 287 /* NB: this only affects frame, not any RTS/CTS */ 288 #define HAL_TXDESC_DURENA 0x0040 /* enable h/w write of duration field */ 289 #define HAL_TXDESC_EXT_ONLY 0x0080 /* send on ext channel only (11n) */ 290 #define HAL_TXDESC_EXT_AND_CTL 0x0100 /* send on ext + ctl channels (11n) */ 291 #define HAL_TXDESC_VMF 0x0200 /* virtual more frag */ 292 #define HAL_TXDESC_LOWRXCHAIN 0x0400 /* switch to low RX chain */ 293 #define HAL_TXDESC_LDPC 0x1000 /* Set LDPC TX for all rates */ 294 #define HAL_TXDESC_HWTS 0x2000 /* Request Azimuth Timestamp in TX payload */ 295 #define HAL_TXDESC_POS 0x4000 /* Request ToD/ToA locationing */ 296 297 /* flags passed to rx descriptor setup methods */ 298 #define HAL_RXDESC_INTREQ 0x0020 /* enable per-descriptor interrupt */ 299 #endif /* _DEV_ATH_DESC_H */ 300