1 /* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19 20 #ifndef _DEV_ATH_DESC_H 21 #define _DEV_ATH_DESC_H 22 23 #include "opt_ah.h" /* NB: required for AH_SUPPORT_AR5416 */ 24 25 /* 26 * For now, define this for the structure definitions. 27 * Because of how the HAL / driver module currently builds, 28 * it's not very feasible to build the module without 29 * this defined. The rest of the code (eg in the driver 30 * body) can work fine with these fields being uninitialised; 31 * they'll be initialised to 0 anyway. 32 */ 33 34 #ifndef AH_SUPPORT_AR5416 35 #define AH_SUPPORT_AR5416 1 36 #endif 37 38 /* 39 * Transmit descriptor status. This structure is filled 40 * in only after the tx descriptor process method finds a 41 * ``done'' descriptor; at which point it returns something 42 * other than HAL_EINPROGRESS. 43 * 44 * Note that ts_antenna may not be valid for all h/w. It 45 * should be used only if non-zero. 46 */ 47 struct ath_tx_status { 48 uint16_t ts_seqnum; /* h/w assigned sequence number */ 49 uint16_t ts_tstamp; /* h/w assigned timestamp */ 50 uint8_t ts_status; /* frame status, 0 => xmit ok */ 51 uint8_t ts_rate; /* h/w transmit rate index */ 52 int8_t ts_rssi; /* tx ack RSSI */ 53 uint8_t ts_shortretry; /* # short retries */ 54 uint8_t ts_longretry; /* # long retries */ 55 uint8_t ts_virtcol; /* virtual collision count */ 56 uint8_t ts_antenna; /* antenna information */ 57 uint8_t ts_finaltsi; /* final transmit series index */ 58 #ifdef AH_SUPPORT_AR5416 59 /* 802.11n status */ 60 uint8_t ts_flags; /* misc flags */ 61 int8_t ts_rssi_ctl[3]; /* tx ack RSSI [ctl, chain 0-2] */ 62 int8_t ts_rssi_ext[3]; /* tx ack RSSI [ext, chain 0-2] */ 63 /* #define ts_rssi ts_rssi_combined */ 64 uint32_t ts_ba_low; /* blockack bitmap low */ 65 uint32_t ts_ba_high; /* blockack bitmap high */ 66 uint8_t ts_tid; /* TID */ 67 uint32_t ts_evm0; /* evm bytes */ 68 uint32_t ts_evm1; 69 uint32_t ts_evm2; 70 #endif /* AH_SUPPORT_AR5416 */ 71 }; 72 73 /* bits found in ts_status */ 74 #define HAL_TXERR_XRETRY 0x01 /* excessive retries */ 75 #define HAL_TXERR_FILT 0x02 /* blocked by tx filtering */ 76 #define HAL_TXERR_FIFO 0x04 /* fifo underrun */ 77 #define HAL_TXERR_XTXOP 0x08 /* txop exceeded */ 78 #define HAL_TXERR_TIMER_EXPIRED 0x10 /* Tx timer expired */ 79 80 /* bits found in ts_flags */ 81 #define HAL_TX_BA 0x01 /* Block Ack seen */ 82 #define HAL_TX_AGGR 0x02 /* Aggregate */ 83 #define HAL_TX_DESC_CFG_ERR 0x10 /* Error in 20/40 desc config */ 84 #define HAL_TX_DATA_UNDERRUN 0x20 /* Tx buffer underrun */ 85 #define HAL_TX_DELIM_UNDERRUN 0x40 /* Tx delimiter underrun */ 86 87 /* 88 * Receive descriptor status. This structure is filled 89 * in only after the rx descriptor process method finds a 90 * ``done'' descriptor; at which point it returns something 91 * other than HAL_EINPROGRESS. 92 * 93 * If rx_status is zero, then the frame was received ok; 94 * otherwise the error information is indicated and rs_phyerr 95 * contains a phy error code if HAL_RXERR_PHY is set. In general 96 * the frame contents is undefined when an error occurred thought 97 * for some errors (e.g. a decryption error), it may be meaningful. 98 * 99 * Note that the receive timestamp is expanded using the TSF to 100 * at least 15 bits (regardless of what the h/w provides directly). 101 * Newer hardware supports a full 32-bits; use HAL_CAP_32TSTAMP to 102 * find out if the hardware is capable. 103 * 104 * rx_rssi is in units of dbm above the noise floor. This value 105 * is measured during the preamble and PLCP; i.e. with the initial 106 * 4us of detection. The noise floor is typically a consistent 107 * -96dBm absolute power in a 20MHz channel. 108 */ 109 struct ath_rx_status { 110 uint16_t rs_datalen; /* rx frame length */ 111 uint8_t rs_status; /* rx status, 0 => recv ok */ 112 uint8_t rs_phyerr; /* phy error code */ 113 int8_t rs_rssi; /* rx frame RSSI (combined for 11n) */ 114 uint8_t rs_keyix; /* key cache index */ 115 uint8_t rs_rate; /* h/w receive rate index */ 116 uint8_t rs_more; /* more descriptors follow */ 117 uint32_t rs_tstamp; /* h/w assigned timestamp */ 118 uint32_t rs_antenna; /* antenna information */ 119 #ifdef AH_SUPPORT_AR5416 120 /* 802.11n status */ 121 int8_t rs_rssi_ctl[3]; /* rx frame RSSI [ctl, chain 0-2] */ 122 int8_t rs_rssi_ext[3]; /* rx frame RSSI [ext, chain 0-2] */ 123 uint8_t rs_isaggr; /* is part of the aggregate */ 124 uint8_t rs_moreaggr; /* more frames in aggr to follow */ 125 uint8_t rs_num_delims; /* number of delims in aggr */ 126 uint8_t rs_flags; /* misc flags */ 127 uint32_t rs_evm0; /* evm bytes */ 128 uint32_t rs_evm1; 129 uint32_t rs_evm2; 130 uint32_t rs_evm3; /* needed for ar9300 and later */ 131 uint32_t rs_evm4; /* needed for ar9300 and later */ 132 #endif /* AH_SUPPORT_AR5416 */ 133 }; 134 135 /* bits found in rs_status */ 136 #define HAL_RXERR_CRC 0x01 /* CRC error on frame */ 137 #define HAL_RXERR_PHY 0x02 /* PHY error, rs_phyerr is valid */ 138 #define HAL_RXERR_FIFO 0x04 /* fifo overrun */ 139 #define HAL_RXERR_DECRYPT 0x08 /* non-Michael decrypt error */ 140 #define HAL_RXERR_MIC 0x10 /* Michael MIC decrypt error */ 141 142 /* bits found in rs_flags */ 143 #define HAL_RX_MORE 0x01 /* more descriptors follow */ 144 #define HAL_RX_MORE_AGGR 0x02 /* more frames in aggr */ 145 #define HAL_RX_GI 0x04 /* full gi */ 146 #define HAL_RX_2040 0x08 /* 40 Mhz */ 147 #define HAL_RX_DELIM_CRC_PRE 0x10 /* crc error in delimiter pre */ 148 #define HAL_RX_DELIM_CRC_POST 0x20 /* crc error in delim after */ 149 #define HAL_RX_DECRYPT_BUSY 0x40 /* decrypt was too slow */ 150 #define HAL_RX_HI_RX_CHAIN 0x80 /* SM power save: hi Rx chain control */ 151 152 enum { 153 HAL_PHYERR_UNDERRUN = 0, /* Transmit underrun */ 154 HAL_PHYERR_TIMING = 1, /* Timing error */ 155 HAL_PHYERR_PARITY = 2, /* Illegal parity */ 156 HAL_PHYERR_RATE = 3, /* Illegal rate */ 157 HAL_PHYERR_LENGTH = 4, /* Illegal length */ 158 HAL_PHYERR_RADAR = 5, /* Radar detect */ 159 HAL_PHYERR_SERVICE = 6, /* Illegal service */ 160 HAL_PHYERR_TOR = 7, /* Transmit override receive */ 161 /* NB: these are specific to the 5212 and later */ 162 HAL_PHYERR_OFDM_TIMING = 17, /* */ 163 HAL_PHYERR_OFDM_SIGNAL_PARITY = 18, /* */ 164 HAL_PHYERR_OFDM_RATE_ILLEGAL = 19, /* */ 165 HAL_PHYERR_OFDM_LENGTH_ILLEGAL = 20, /* */ 166 HAL_PHYERR_OFDM_POWER_DROP = 21, /* */ 167 HAL_PHYERR_OFDM_SERVICE = 22, /* */ 168 HAL_PHYERR_OFDM_RESTART = 23, /* */ 169 HAL_PHYERR_FALSE_RADAR_EXT = 24, /* */ 170 HAL_PHYERR_CCK_TIMING = 25, /* */ 171 HAL_PHYERR_CCK_HEADER_CRC = 26, /* */ 172 HAL_PHYERR_CCK_RATE_ILLEGAL = 27, /* */ 173 HAL_PHYERR_CCK_SERVICE = 30, /* */ 174 HAL_PHYERR_CCK_RESTART = 31, /* */ 175 HAL_PHYERR_CCK_LENGTH_ILLEGAL = 32, /* */ 176 HAL_PHYERR_CCK_POWER_DROP = 33, /* */ 177 /* AR5416 and later */ 178 HAL_PHYERR_HT_CRC_ERROR = 34, /* */ 179 HAL_PHYERR_HT_LENGTH_ILLEGAL = 35, /* */ 180 HAL_PHYERR_HT_RATE_ILLEGAL = 36, /* */ 181 }; 182 183 /* value found in rs_keyix to mark invalid entries */ 184 #define HAL_RXKEYIX_INVALID ((uint8_t) -1) 185 /* value used to specify no encryption key for xmit */ 186 #define HAL_TXKEYIX_INVALID ((u_int) -1) 187 188 /* XXX rs_antenna definitions */ 189 190 /* 191 * Definitions for the software frame/packet descriptors used by 192 * the Atheros HAL. This definition obscures hardware-specific 193 * details from the driver. Drivers are expected to fillin the 194 * portions of a descriptor that are not opaque then use HAL calls 195 * to complete the work. Status for completed frames is returned 196 * in a device-independent format. 197 */ 198 #ifdef AH_SUPPORT_AR5416 199 #define HAL_DESC_HW_SIZE 20 200 #else 201 #define HAL_DESC_HW_SIZE 4 202 #endif /* AH_SUPPORT_AR5416 */ 203 204 struct ath_desc { 205 /* 206 * The following definitions are passed directly 207 * the hardware and managed by the HAL. Drivers 208 * should not touch those elements marked opaque. 209 */ 210 uint32_t ds_link; /* phys address of next descriptor */ 211 uint32_t ds_data; /* phys address of data buffer */ 212 uint32_t ds_ctl0; /* opaque DMA control 0 */ 213 uint32_t ds_ctl1; /* opaque DMA control 1 */ 214 uint32_t ds_hw[HAL_DESC_HW_SIZE]; /* opaque h/w region */ 215 }; 216 217 struct ath_desc_status { 218 union { 219 struct ath_tx_status tx;/* xmit status */ 220 struct ath_rx_status rx;/* recv status */ 221 } ds_us; 222 }; 223 224 #define ds_txstat ds_us.tx 225 #define ds_rxstat ds_us.rx 226 227 /* flags passed to tx descriptor setup methods */ 228 #define HAL_TXDESC_CLRDMASK 0x0001 /* clear destination filter mask */ 229 #define HAL_TXDESC_NOACK 0x0002 /* don't wait for ACK */ 230 #define HAL_TXDESC_RTSENA 0x0004 /* enable RTS */ 231 #define HAL_TXDESC_CTSENA 0x0008 /* enable CTS */ 232 #define HAL_TXDESC_INTREQ 0x0010 /* enable per-descriptor interrupt */ 233 #define HAL_TXDESC_VEOL 0x0020 /* mark virtual EOL */ 234 /* NB: this only affects frame, not any RTS/CTS */ 235 #define HAL_TXDESC_DURENA 0x0040 /* enable h/w write of duration field */ 236 #define HAL_TXDESC_EXT_ONLY 0x0080 /* send on ext channel only (11n) */ 237 #define HAL_TXDESC_EXT_AND_CTL 0x0100 /* send on ext + ctl channels (11n) */ 238 #define HAL_TXDESC_VMF 0x0200 /* virtual more frag */ 239 240 /* flags passed to rx descriptor setup methods */ 241 #define HAL_RXDESC_INTREQ 0x0020 /* enable per-descriptor interrupt */ 242 #endif /* _DEV_ATH_DESC_H */ 243