1 /*- 2 * SPDX-License-Identifier: ISC 3 * 4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 5 * Copyright (c) 2002-2008 Atheros Communications, Inc. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 #ifndef _ATH_AH_DECODE_H_ 20 #define _ATH_AH_DECODE_H_ 21 /* 22 * Register tracing support. 23 * 24 * Setting hw.ath.hal.alq=1 enables tracing of all register reads and 25 * writes to the file /tmp/ath_hal.log. The file format is a simple 26 * fixed-size array of records. When done logging set hw.ath.hal.alq=0 27 * and then decode the file with the arcode program (that is part of the 28 * HAL). If you start+stop tracing the data will be appended to an 29 * existing file. 30 */ 31 struct athregrec { 32 uint32_t threadid; 33 uint32_t op : 8, 34 reg : 24; 35 uint32_t val; 36 }; 37 38 enum { 39 OP_READ = 0, /* register read */ 40 OP_WRITE = 1, /* register write */ 41 OP_DEVICE = 2, /* device identification */ 42 OP_MARK = 3, /* application marker */ 43 }; 44 45 enum { 46 AH_MARK_RESET, /* ar*Reset entry, bChannelChange */ 47 AH_MARK_RESET_LINE, /* ar*_reset.c, line %d */ 48 AH_MARK_RESET_DONE, /* ar*Reset exit, error code */ 49 AH_MARK_CHIPRESET, /* ar*ChipReset, channel num */ 50 AH_MARK_PERCAL, /* ar*PerCalibration, channel num */ 51 AH_MARK_SETCHANNEL, /* ar*SetChannel, channel num */ 52 AH_MARK_ANI_RESET, /* ar*AniReset, opmode */ 53 AH_MARK_ANI_POLL, /* ar*AniReset, listen time */ 54 AH_MARK_ANI_CONTROL, /* ar*AniReset, cmd */ 55 AH_MARK_RX_CTL, /* RX DMA control */ 56 AH_MARK_CHIP_POWER, /* chip power control, mode */ 57 AH_MARK_CHIP_POWER_DONE, /* chip power control done, status */ 58 }; 59 60 enum { 61 AH_MARK_RX_CTL_PCU_START, 62 AH_MARK_RX_CTL_PCU_STOP, 63 AH_MARK_RX_CTL_DMA_START, 64 AH_MARK_RX_CTL_DMA_STOP, 65 AH_MARK_RX_CTL_DMA_STOP_ERR, 66 AH_MARK_RX_CTL_DMA_STOP_OK, 67 }; 68 69 #endif /* _ATH_AH_DECODE_H_ */ 70