1 /*- 2 * SPDX-License-Identifier: ISC 3 * 4 * Copyright (c) 2014 Qualcomm Atheros, Inc. 5 * All Rights Reserved. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 * 19 * $FreeBSD$ 20 */ 21 #ifndef __ATH_HAL_BTCOEX_H__ 22 #define __ATH_HAL_BTCOEX_H__ 23 24 /* 25 * General BT coexistence definitions. 26 */ 27 typedef enum { 28 HAL_BT_MODULE_CSR_BC4 = 0, /* CSR BlueCore v4 */ 29 HAL_BT_MODULE_JANUS = 1, /* Kite + Valkyrie combo */ 30 HAL_BT_MODULE_HELIUS = 2, /* Kiwi + Valkyrie combo */ 31 HAL_MAX_BT_MODULES 32 } HAL_BT_MODULE; 33 34 typedef struct { 35 HAL_BT_MODULE bt_module; 36 u_int8_t bt_coex_config; 37 u_int8_t bt_gpio_bt_active; 38 u_int8_t bt_gpio_bt_priority; 39 u_int8_t bt_gpio_wlan_active; 40 u_int8_t bt_active_polarity; 41 HAL_BOOL bt_single_ant; 42 u_int8_t bt_isolation; 43 } HAL_BT_COEX_INFO; 44 45 typedef enum { 46 HAL_BT_COEX_MODE_LEGACY = 0, /* legacy rx_clear mode */ 47 HAL_BT_COEX_MODE_UNSLOTTED = 1, /* untimed/unslotted mode */ 48 HAL_BT_COEX_MODE_SLOTTED = 2, /* slotted mode */ 49 HAL_BT_COEX_MODE_DISALBED = 3, /* coexistence disabled */ 50 } HAL_BT_COEX_MODE; 51 52 typedef enum { 53 HAL_BT_COEX_CFG_NONE, /* No bt coex enabled */ 54 HAL_BT_COEX_CFG_2WIRE_2CH, /* 2-wire with 2 chains */ 55 HAL_BT_COEX_CFG_2WIRE_CH1, /* 2-wire with ch1 */ 56 HAL_BT_COEX_CFG_2WIRE_CH0, /* 2-wire with ch0 */ 57 HAL_BT_COEX_CFG_3WIRE, /* 3-wire */ 58 HAL_BT_COEX_CFG_MCI /* MCI */ 59 } HAL_BT_COEX_CFG; 60 61 typedef enum { 62 HAL_BT_COEX_SET_ACK_PWR = 0, /* Change ACK power setting */ 63 HAL_BT_COEX_LOWER_TX_PWR, /* Change transmit power */ 64 HAL_BT_COEX_ANTENNA_DIVERSITY, /* Enable RX diversity for Kite */ 65 HAL_BT_COEX_MCI_MAX_TX_PWR, /* Set max tx power for concurrent tx */ 66 HAL_BT_COEX_MCI_FTP_STOMP_RX, /* Use a different weight for stomp low */ 67 } HAL_BT_COEX_SET_PARAMETER; 68 69 /* 70 * MCI specific coexistence definitions. 71 */ 72 73 #define HAL_BT_COEX_FLAG_LOW_ACK_PWR 0x00000001 74 #define HAL_BT_COEX_FLAG_LOWER_TX_PWR 0x00000002 75 /* Check Rx Diversity is allowed */ 76 #define HAL_BT_COEX_FLAG_ANT_DIV_ALLOW 0x00000004 77 /* Check Diversity is on or off */ 78 #define HAL_BT_COEX_FLAG_ANT_DIV_ENABLE 0x00000008 79 80 #define HAL_BT_COEX_ANTDIV_CONTROL1_ENABLE 0x0b 81 /* main: LNA1, alt: LNA2 */ 82 #define HAL_BT_COEX_ANTDIV_CONTROL2_ENABLE 0x09 83 #define HAL_BT_COEX_ANTDIV_CONTROL1_FIXED_A 0x04 84 #define HAL_BT_COEX_ANTDIV_CONTROL2_FIXED_A 0x09 85 #define HAL_BT_COEX_ANTDIV_CONTROL1_FIXED_B 0x02 86 #define HAL_BT_COEX_ANTDIV_CONTROL2_FIXED_B 0x06 87 88 #define HAL_BT_COEX_ISOLATION_FOR_NO_COEX 30 89 90 #define HAL_BT_COEX_ANT_DIV_SWITCH_COM 0x66666666 91 92 #define HAL_BT_COEX_HELIUS_CHAINMASK 0x02 93 94 #define HAL_BT_COEX_LOW_ACK_POWER 0x0 95 #define HAL_BT_COEX_HIGH_ACK_POWER 0x3f3f3f 96 97 typedef enum { 98 HAL_BT_COEX_NO_STOMP = 0, 99 HAL_BT_COEX_STOMP_ALL, 100 HAL_BT_COEX_STOMP_LOW, 101 HAL_BT_COEX_STOMP_NONE, 102 HAL_BT_COEX_STOMP_ALL_FORCE, 103 HAL_BT_COEX_STOMP_LOW_FORCE, 104 HAL_BT_COEX_STOMP_AUDIO, 105 } HAL_BT_COEX_STOMP_TYPE; 106 107 typedef struct { 108 /* extend rx_clear after tx/rx to protect the burst (in usec). */ 109 u_int8_t bt_time_extend; 110 111 /* 112 * extend rx_clear as long as txsm is 113 * transmitting or waiting for ack. 114 */ 115 HAL_BOOL bt_txstate_extend; 116 117 /* 118 * extend rx_clear so that when tx_frame 119 * is asserted, rx_clear will drop. 120 */ 121 HAL_BOOL bt_txframe_extend; 122 123 /* 124 * coexistence mode 125 */ 126 HAL_BT_COEX_MODE bt_mode; 127 128 /* 129 * treat BT high priority traffic as 130 * a quiet collision 131 */ 132 HAL_BOOL bt_quiet_collision; 133 134 /* 135 * invert rx_clear as WLAN_ACTIVE 136 */ 137 HAL_BOOL bt_rxclear_polarity; 138 139 /* 140 * slotted mode only. indicate the time in usec 141 * from the rising edge of BT_ACTIVE to the time 142 * BT_PRIORITY can be sampled to indicate priority. 143 */ 144 u_int8_t bt_priority_time; 145 146 /* 147 * slotted mode only. indicate the time in usec 148 * from the rising edge of BT_ACTIVE to the time 149 * BT_PRIORITY can be sampled to indicate tx/rx and 150 * BT_FREQ is sampled. 151 */ 152 u_int8_t bt_first_slot_time; 153 154 /* 155 * slotted mode only. rx_clear and bt_ant decision 156 * will be held the entire time that BT_ACTIVE is asserted, 157 * otherwise the decision is made before every slot boundary. 158 */ 159 HAL_BOOL bt_hold_rxclear; 160 } HAL_BT_COEX_CONFIG; 161 162 #define HAL_BT_COEX_FLAG_LOW_ACK_PWR 0x00000001 163 #define HAL_BT_COEX_FLAG_LOWER_TX_PWR 0x00000002 164 #define HAL_BT_COEX_FLAG_ANT_DIV_ALLOW 0x00000004 /* Check Rx Diversity is allowed */ 165 #define HAL_BT_COEX_FLAG_ANT_DIV_ENABLE 0x00000008 /* Check Diversity is on or off */ 166 #define HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR 0x00000010 167 #define HAL_BT_COEX_FLAG_MCI_FTP_STOMP_RX 0x00000020 168 169 #define HAL_MCI_FLAG_DISABLE_TIMESTAMP 0x00000001 /* Disable time stamp */ 170 171 typedef enum mci_message_header { 172 MCI_LNA_CTRL = 0x10, /* len = 0 */ 173 MCI_CONT_NACK = 0x20, /* len = 0 */ 174 MCI_CONT_INFO = 0x30, /* len = 4 */ 175 MCI_CONT_RST = 0x40, /* len = 0 */ 176 MCI_SCHD_INFO = 0x50, /* len = 16 */ 177 MCI_CPU_INT = 0x60, /* len = 4 */ 178 MCI_SYS_WAKING = 0x70, /* len = 0 */ 179 MCI_GPM = 0x80, /* len = 16 */ 180 MCI_LNA_INFO = 0x90, /* len = 1 */ 181 MCI_LNA_STATE = 0x94, 182 MCI_LNA_TAKE = 0x98, 183 MCI_LNA_TRANS = 0x9c, 184 MCI_SYS_SLEEPING = 0xa0, /* len = 0 */ 185 MCI_REQ_WAKE = 0xc0, /* len = 0 */ 186 MCI_DEBUG_16 = 0xfe, /* len = 2 */ 187 MCI_REMOTE_RESET = 0xff /* len = 16 */ 188 } MCI_MESSAGE_HEADER; 189 190 /* Default remote BT device MCI COEX version */ 191 #define MCI_GPM_COEX_MAJOR_VERSION_DEFAULT 3 192 #define MCI_GPM_COEX_MINOR_VERSION_DEFAULT 0 193 /* Local WLAN MCI COEX version */ 194 #define MCI_GPM_COEX_MAJOR_VERSION_WLAN 3 195 #define MCI_GPM_COEX_MINOR_VERSION_WLAN 0 196 197 typedef enum mci_gpm_subtype { 198 MCI_GPM_BT_CAL_REQ = 0, 199 MCI_GPM_BT_CAL_GRANT = 1, 200 MCI_GPM_BT_CAL_DONE = 2, 201 MCI_GPM_WLAN_CAL_REQ = 3, 202 MCI_GPM_WLAN_CAL_GRANT = 4, 203 MCI_GPM_WLAN_CAL_DONE = 5, 204 MCI_GPM_COEX_AGENT = 0x0C, 205 MCI_GPM_RSVD_PATTERN = 0xFE, 206 MCI_GPM_RSVD_PATTERN32 = 0xFEFEFEFE, 207 MCI_GPM_BT_DEBUG = 0xFF 208 } MCI_GPM_SUBTYPE_T; 209 210 typedef enum mci_gpm_coex_opcode { 211 MCI_GPM_COEX_VERSION_QUERY = 0, 212 MCI_GPM_COEX_VERSION_RESPONSE = 1, 213 MCI_GPM_COEX_STATUS_QUERY = 2, 214 MCI_GPM_COEX_HALT_BT_GPM = 3, 215 MCI_GPM_COEX_WLAN_CHANNELS = 4, 216 MCI_GPM_COEX_BT_PROFILE_INFO = 5, 217 MCI_GPM_COEX_BT_STATUS_UPDATE = 6, 218 MCI_GPM_COEX_BT_UPDATE_FLAGS = 7 219 } MCI_GPM_COEX_OPCODE_T; 220 221 typedef enum mci_gpm_coex_query_type { 222 /* WLAN information */ 223 MCI_GPM_COEX_QUERY_WLAN_ALL_INFO = 0x01, 224 /* BT information */ 225 MCI_GPM_COEX_QUERY_BT_ALL_INFO = 0x01, 226 MCI_GPM_COEX_QUERY_BT_TOPOLOGY = 0x02, 227 MCI_GPM_COEX_QUERY_BT_DEBUG = 0x04 228 } MCI_GPM_COEX_QUERY_TYPE_T; 229 230 typedef enum mci_gpm_coex_halt_bt_gpm { 231 MCI_GPM_COEX_BT_GPM_UNHALT = 0, 232 MCI_GPM_COEX_BT_GPM_HALT = 1 233 } MCI_GPM_COEX_HALT_BT_GPM_T; 234 235 typedef enum mci_gpm_coex_profile_type { 236 MCI_GPM_COEX_PROFILE_UNKNOWN = 0, 237 MCI_GPM_COEX_PROFILE_RFCOMM = 1, 238 MCI_GPM_COEX_PROFILE_A2DP = 2, 239 MCI_GPM_COEX_PROFILE_HID = 3, 240 MCI_GPM_COEX_PROFILE_BNEP = 4, 241 MCI_GPM_COEX_PROFILE_VOICE = 5, 242 MCI_GPM_COEX_PROFILE_MAX 243 } MCI_GPM_COEX_PROFILE_TYPE_T; 244 245 typedef enum mci_gpm_coex_profile_state { 246 MCI_GPM_COEX_PROFILE_STATE_END = 0, 247 MCI_GPM_COEX_PROFILE_STATE_START = 1 248 } MCI_GPM_COEX_PROFILE_STATE_T; 249 250 typedef enum mci_gpm_coex_profile_role { 251 MCI_GPM_COEX_PROFILE_SLAVE = 0, 252 MCI_GPM_COEX_PROFILE_MASTER = 1 253 } MCI_GPM_COEX_PROFILE_ROLE_T; 254 255 typedef enum mci_gpm_coex_bt_status_type { 256 MCI_GPM_COEX_BT_NONLINK_STATUS = 0, 257 MCI_GPM_COEX_BT_LINK_STATUS = 1 258 } MCI_GPM_COEX_BT_STATUS_TYPE_T; 259 260 typedef enum mci_gpm_coex_bt_status_state { 261 MCI_GPM_COEX_BT_NORMAL_STATUS = 0, 262 MCI_GPM_COEX_BT_CRITICAL_STATUS = 1 263 } MCI_GPM_COEX_BT_STATUS_STATE_T; 264 265 #define MCI_GPM_INVALID_PROFILE_HANDLE 0xff 266 267 typedef enum mci_gpm_coex_bt_updata_flags_op { 268 MCI_GPM_COEX_BT_FLAGS_READ = 0x00, 269 MCI_GPM_COEX_BT_FLAGS_SET = 0x01, 270 MCI_GPM_COEX_BT_FLAGS_CLEAR = 0x02 271 } MCI_GPM_COEX_BT_FLAGS_OP_T; 272 273 /* MCI GPM/Coex opcode/type definitions */ 274 enum { 275 MCI_GPM_COEX_W_GPM_PAYLOAD = 1, 276 MCI_GPM_COEX_B_GPM_TYPE = 4, 277 MCI_GPM_COEX_B_GPM_OPCODE = 5, 278 /* MCI_GPM_WLAN_CAL_REQ, MCI_GPM_WLAN_CAL_DONE */ 279 MCI_GPM_WLAN_CAL_W_SEQUENCE = 2, 280 /* MCI_GPM_COEX_VERSION_QUERY */ 281 /* MCI_GPM_COEX_VERSION_RESPONSE */ 282 MCI_GPM_COEX_B_MAJOR_VERSION = 6, 283 MCI_GPM_COEX_B_MINOR_VERSION = 7, 284 /* MCI_GPM_COEX_STATUS_QUERY */ 285 MCI_GPM_COEX_B_BT_BITMAP = 6, 286 MCI_GPM_COEX_B_WLAN_BITMAP = 7, 287 /* MCI_GPM_COEX_HALT_BT_GPM */ 288 MCI_GPM_COEX_B_HALT_STATE = 6, 289 /* MCI_GPM_COEX_WLAN_CHANNELS */ 290 MCI_GPM_COEX_B_CHANNEL_MAP = 6, 291 /* MCI_GPM_COEX_BT_PROFILE_INFO */ 292 MCI_GPM_COEX_B_PROFILE_TYPE = 6, 293 MCI_GPM_COEX_B_PROFILE_LINKID = 7, 294 MCI_GPM_COEX_B_PROFILE_STATE = 8, 295 MCI_GPM_COEX_B_PROFILE_ROLE = 9, 296 MCI_GPM_COEX_B_PROFILE_RATE = 10, 297 MCI_GPM_COEX_B_PROFILE_VOTYPE = 11, 298 MCI_GPM_COEX_H_PROFILE_T = 12, 299 MCI_GPM_COEX_B_PROFILE_W = 14, 300 MCI_GPM_COEX_B_PROFILE_A = 15, 301 /* MCI_GPM_COEX_BT_STATUS_UPDATE */ 302 MCI_GPM_COEX_B_STATUS_TYPE = 6, 303 MCI_GPM_COEX_B_STATUS_LINKID = 7, 304 MCI_GPM_COEX_B_STATUS_STATE = 8, 305 /* MCI_GPM_COEX_BT_UPDATE_FLAGS */ 306 MCI_GPM_COEX_B_BT_FLAGS_OP = 10, 307 MCI_GPM_COEX_W_BT_FLAGS = 6 308 }; 309 310 #define MCI_GPM_RECYCLE(_p_gpm) \ 311 { \ 312 *(((u_int32_t *)(_p_gpm)) + MCI_GPM_COEX_W_GPM_PAYLOAD) = MCI_GPM_RSVD_PATTERN32; \ 313 } 314 #define MCI_GPM_TYPE(_p_gpm) \ 315 (*(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) & 0xff) 316 #define MCI_GPM_OPCODE(_p_gpm) \ 317 (*(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_OPCODE) & 0xff) 318 319 #define MCI_GPM_SET_CAL_TYPE(_p_gpm, _cal_type) \ 320 { \ 321 *(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) = (_cal_type) & 0xff; \ 322 } 323 #define MCI_GPM_SET_TYPE_OPCODE(_p_gpm, _type, _opcode) \ 324 { \ 325 *(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) = (_type) & 0xff; \ 326 *(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_OPCODE) = (_opcode) & 0xff; \ 327 } 328 #define MCI_GPM_IS_CAL_TYPE(_type) ((_type) <= MCI_GPM_WLAN_CAL_DONE) 329 330 #define MCI_NUM_BT_CHANNELS 79 331 332 #define MCI_GPM_SET_CHANNEL_BIT(_p_gpm, _bt_chan) \ 333 { \ 334 if (_bt_chan < MCI_NUM_BT_CHANNELS) { \ 335 *(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_CHANNEL_MAP + \ 336 (_bt_chan / 8)) |= 1 << (_bt_chan & 7); \ 337 } \ 338 } 339 340 #define MCI_GPM_CLR_CHANNEL_BIT(_p_gpm, _bt_chan) \ 341 { \ 342 if (_bt_chan < MCI_NUM_BT_CHANNELS) { \ 343 *(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_CHANNEL_MAP + \ 344 (_bt_chan / 8)) &= ~(1 << (_bt_chan & 7)); \ 345 } \ 346 } 347 348 #define HAL_MCI_INTERRUPT_SW_MSG_DONE 0x00000001 349 #define HAL_MCI_INTERRUPT_CPU_INT_MSG 0x00000002 350 #define HAL_MCI_INTERRUPT_RX_CHKSUM_FAIL 0x00000004 351 #define HAL_MCI_INTERRUPT_RX_INVALID_HDR 0x00000008 352 #define HAL_MCI_INTERRUPT_RX_HW_MSG_FAIL 0x00000010 353 #define HAL_MCI_INTERRUPT_RX_SW_MSG_FAIL 0x00000020 354 #define HAL_MCI_INTERRUPT_TX_HW_MSG_FAIL 0x00000080 355 #define HAL_MCI_INTERRUPT_TX_SW_MSG_FAIL 0x00000100 356 #define HAL_MCI_INTERRUPT_RX_MSG 0x00000200 357 #define HAL_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE 0x00000400 358 #define HAL_MCI_INTERRUPT_CONT_INFO_TIMEOUT 0x80000000 359 #define HAL_MCI_INTERRUPT_MSG_FAIL_MASK ( HAL_MCI_INTERRUPT_RX_HW_MSG_FAIL | \ 360 HAL_MCI_INTERRUPT_RX_SW_MSG_FAIL | \ 361 HAL_MCI_INTERRUPT_TX_HW_MSG_FAIL | \ 362 HAL_MCI_INTERRUPT_TX_SW_MSG_FAIL ) 363 364 #define HAL_MCI_INTERRUPT_RX_MSG_REMOTE_RESET 0x00000001 365 #define HAL_MCI_INTERRUPT_RX_MSG_LNA_CONTROL 0x00000002 366 #define HAL_MCI_INTERRUPT_RX_MSG_CONT_NACK 0x00000004 367 #define HAL_MCI_INTERRUPT_RX_MSG_CONT_INFO 0x00000008 368 #define HAL_MCI_INTERRUPT_RX_MSG_CONT_RST 0x00000010 369 #define HAL_MCI_INTERRUPT_RX_MSG_SCHD_INFO 0x00000020 370 #define HAL_MCI_INTERRUPT_RX_MSG_CPU_INT 0x00000040 371 #define HAL_MCI_INTERRUPT_RX_MSG_GPM 0x00000100 372 #define HAL_MCI_INTERRUPT_RX_MSG_LNA_INFO 0x00000200 373 #define HAL_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING 0x00000400 374 #define HAL_MCI_INTERRUPT_RX_MSG_SYS_WAKING 0x00000800 375 #define HAL_MCI_INTERRUPT_RX_MSG_REQ_WAKE 0x00001000 376 #define HAL_MCI_INTERRUPT_RX_MSG_MONITOR (HAL_MCI_INTERRUPT_RX_MSG_LNA_CONTROL | \ 377 HAL_MCI_INTERRUPT_RX_MSG_LNA_INFO | \ 378 HAL_MCI_INTERRUPT_RX_MSG_CONT_NACK | \ 379 HAL_MCI_INTERRUPT_RX_MSG_CONT_INFO | \ 380 HAL_MCI_INTERRUPT_RX_MSG_CONT_RST) 381 382 typedef enum mci_bt_state { 383 MCI_BT_SLEEP, 384 MCI_BT_AWAKE, 385 MCI_BT_CAL_START, 386 MCI_BT_CAL 387 } MCI_BT_STATE_T; 388 389 /* Type of state query */ 390 typedef enum mci_state_type { 391 HAL_MCI_STATE_ENABLE, 392 HAL_MCI_STATE_INIT_GPM_OFFSET, 393 HAL_MCI_STATE_NEXT_GPM_OFFSET, 394 HAL_MCI_STATE_LAST_GPM_OFFSET, 395 HAL_MCI_STATE_BT, 396 HAL_MCI_STATE_SET_BT_SLEEP, 397 HAL_MCI_STATE_SET_BT_AWAKE, 398 HAL_MCI_STATE_SET_BT_CAL_START, 399 HAL_MCI_STATE_SET_BT_CAL, 400 HAL_MCI_STATE_LAST_SCHD_MSG_OFFSET, 401 HAL_MCI_STATE_REMOTE_SLEEP, 402 HAL_MCI_STATE_CONT_RSSI_POWER, 403 HAL_MCI_STATE_CONT_PRIORITY, 404 HAL_MCI_STATE_CONT_TXRX, 405 HAL_MCI_STATE_RESET_REQ_WAKE, 406 HAL_MCI_STATE_SEND_WLAN_COEX_VERSION, 407 HAL_MCI_STATE_SET_BT_COEX_VERSION, 408 HAL_MCI_STATE_SEND_WLAN_CHANNELS, 409 HAL_MCI_STATE_SEND_VERSION_QUERY, 410 HAL_MCI_STATE_SEND_STATUS_QUERY, 411 HAL_MCI_STATE_NEED_FLUSH_BT_INFO, 412 HAL_MCI_STATE_SET_CONCUR_TX_PRI, 413 HAL_MCI_STATE_RECOVER_RX, 414 HAL_MCI_STATE_NEED_FTP_STOMP, 415 HAL_MCI_STATE_NEED_TUNING, 416 HAL_MCI_STATE_SHARED_CHAIN_CONCUR_TX, 417 HAL_MCI_STATE_DEBUG, 418 HAL_MCI_STATE_MAX 419 } HAL_MCI_STATE_TYPE; 420 421 #define HAL_MCI_STATE_DEBUG_REQ_BT_DEBUG 1 422 423 #define HAL_MCI_BT_MCI_FLAGS_UPDATE_CORR 0x00000002 424 #define HAL_MCI_BT_MCI_FLAGS_UPDATE_HDR 0x00000004 425 #define HAL_MCI_BT_MCI_FLAGS_UPDATE_PLD 0x00000008 426 #define HAL_MCI_BT_MCI_FLAGS_LNA_CTRL 0x00000010 427 #define HAL_MCI_BT_MCI_FLAGS_DEBUG 0x00000020 428 #define HAL_MCI_BT_MCI_FLAGS_SCHED_MSG 0x00000040 429 #define HAL_MCI_BT_MCI_FLAGS_CONT_MSG 0x00000080 430 #define HAL_MCI_BT_MCI_FLAGS_COEX_GPM 0x00000100 431 #define HAL_MCI_BT_MCI_FLAGS_CPU_INT_MSG 0x00000200 432 #define HAL_MCI_BT_MCI_FLAGS_MCI_MODE 0x00000400 433 #define HAL_MCI_BT_MCI_FLAGS_EGRET_MODE 0x00000800 434 #define HAL_MCI_BT_MCI_FLAGS_JUPITER_MODE 0x00001000 435 #define HAL_MCI_BT_MCI_FLAGS_OTHER 0x00010000 436 437 #define HAL_MCI_DEFAULT_BT_MCI_FLAGS 0x00011dde 438 /* 439 HAL_MCI_BT_MCI_FLAGS_UPDATE_CORR = 1 440 HAL_MCI_BT_MCI_FLAGS_UPDATE_HDR = 1 441 HAL_MCI_BT_MCI_FLAGS_UPDATE_PLD = 1 442 HAL_MCI_BT_MCI_FLAGS_LNA_CTRL = 1 443 HAL_MCI_BT_MCI_FLAGS_DEBUG = 0 444 HAL_MCI_BT_MCI_FLAGS_SCHED_MSG = 1 445 HAL_MCI_BT_MCI_FLAGS_CONT_MSG = 1 446 HAL_MCI_BT_MCI_FLAGS_COEX_GPM = 1 447 HAL_MCI_BT_MCI_FLAGS_CPU_INT_MSG = 0 448 HAL_MCI_BT_MCI_FLAGS_MCI_MODE = 1 449 HAL_MCI_BT_MCI_FLAGS_EGRET_MODE = 1 450 HAL_MCI_BT_MCI_FLAGS_JUPITER_MODE = 1 451 HAL_MCI_BT_MCI_FLAGS_OTHER = 1 452 */ 453 454 #define HAL_MCI_TOGGLE_BT_MCI_FLAGS \ 455 ( HAL_MCI_BT_MCI_FLAGS_UPDATE_CORR | \ 456 HAL_MCI_BT_MCI_FLAGS_UPDATE_HDR | \ 457 HAL_MCI_BT_MCI_FLAGS_UPDATE_PLD | \ 458 HAL_MCI_BT_MCI_FLAGS_MCI_MODE ) 459 460 #define HAL_MCI_2G_FLAGS_CLEAR_MASK 0x00000000 461 #define HAL_MCI_2G_FLAGS_SET_MASK HAL_MCI_TOGGLE_BT_MCI_FLAGS 462 #define HAL_MCI_2G_FLAGS HAL_MCI_DEFAULT_BT_MCI_FLAGS 463 464 #define HAL_MCI_5G_FLAGS_CLEAR_MASK HAL_MCI_TOGGLE_BT_MCI_FLAGS 465 #define HAL_MCI_5G_FLAGS_SET_MASK 0x00000000 466 #define HAL_MCI_5G_FLAGS (HAL_MCI_DEFAULT_BT_MCI_FLAGS & \ 467 ~HAL_MCI_TOGGLE_BT_MCI_FLAGS) 468 469 #define HAL_MCI_GPM_NOMORE 0 470 #define HAL_MCI_GPM_MORE 1 471 #define HAL_MCI_GPM_INVALID 0xffffffff 472 473 #define ATH_AIC_MAX_BT_CHANNEL 79 474 475 /* 476 * Default value for Jupiter is 0x00002201 477 * Default value for Aphrodite is 0x00002282 478 */ 479 #define ATH_MCI_CONFIG_CONCUR_TX 0x00000003 480 #define ATH_MCI_CONFIG_MCI_OBS_MCI 0x00000004 481 #define ATH_MCI_CONFIG_MCI_OBS_TXRX 0x00000008 482 #define ATH_MCI_CONFIG_MCI_OBS_BT 0x00000010 483 #define ATH_MCI_CONFIG_DISABLE_MCI_CAL 0x00000020 484 #define ATH_MCI_CONFIG_DISABLE_OSLA 0x00000040 485 #define ATH_MCI_CONFIG_DISABLE_FTP_STOMP 0x00000080 486 #define ATH_MCI_CONFIG_AGGR_THRESH 0x00000700 487 #define ATH_MCI_CONFIG_AGGR_THRESH_S 8 488 #define ATH_MCI_CONFIG_DISABLE_AGGR_THRESH 0x00000800 489 #define ATH_MCI_CONFIG_CLK_DIV 0x00003000 490 #define ATH_MCI_CONFIG_CLK_DIV_S 12 491 #define ATH_MCI_CONFIG_DISABLE_TUNING 0x00004000 492 #define ATH_MCI_CONFIG_DISABLE_AIC 0x00008000 493 #define ATH_MCI_CONFIG_AIC_CAL_NUM_CHAN 0x007f0000 494 #define ATH_MCI_CONFIG_AIC_CAL_NUM_CHAN_S 16 495 #define ATH_MCI_CONFIG_NO_QUIET_ACK 0x00800000 496 #define ATH_MCI_CONFIG_NO_QUIET_ACK_S 23 497 #define ATH_MCI_CONFIG_ANT_ARCH 0x07000000 498 #define ATH_MCI_CONFIG_ANT_ARCH_S 24 499 #define ATH_MCI_CONFIG_FORCE_QUIET_ACK 0x08000000 500 #define ATH_MCI_CONFIG_FORCE_QUIET_ACK_S 27 501 #define ATH_MCI_CONFIG_FORCE_2CHAIN_ACK 0x10000000 502 #define ATH_MCI_CONFIG_MCI_STAT_DBG 0x20000000 503 #define ATH_MCI_CONFIG_MCI_WEIGHT_DBG 0x40000000 504 #define ATH_MCI_CONFIG_DISABLE_MCI 0x80000000 505 506 #define ATH_MCI_CONFIG_MCI_OBS_MASK ( ATH_MCI_CONFIG_MCI_OBS_MCI | \ 507 ATH_MCI_CONFIG_MCI_OBS_TXRX | \ 508 ATH_MCI_CONFIG_MCI_OBS_BT ) 509 #define ATH_MCI_CONFIG_MCI_OBS_GPIO 0x0000002F 510 511 #define ATH_MCI_ANT_ARCH_1_ANT_PA_LNA_NON_SHARED 0x00 512 #define ATH_MCI_ANT_ARCH_1_ANT_PA_LNA_SHARED 0x01 513 #define ATH_MCI_ANT_ARCH_2_ANT_PA_LNA_NON_SHARED 0x02 514 #define ATH_MCI_ANT_ARCH_2_ANT_PA_LNA_SHARED 0x03 515 #define ATH_MCI_ANT_ARCH_3_ANT 0x04 516 517 #define MCI_ANT_ARCH_PA_LNA_SHARED(c) \ 518 ((MS(c, ATH_MCI_CONFIG_ANT_ARCH) == ATH_MCI_ANT_ARCH_1_ANT_PA_LNA_SHARED) || \ 519 (MS(c, ATH_MCI_CONFIG_ANT_ARCH) == ATH_MCI_ANT_ARCH_2_ANT_PA_LNA_SHARED)) 520 521 #define ATH_MCI_CONCUR_TX_SHARED_CHN 0x01 522 #define ATH_MCI_CONCUR_TX_UNSHARED_CHN 0x02 523 #define ATH_MCI_CONCUR_TX_DEBUG 0x03 524 525 #endif 526