1 /* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19 20 #ifndef _ATH_AH_H_ 21 #define _ATH_AH_H_ 22 /* 23 * Atheros Hardware Access Layer 24 * 25 * Clients of the HAL call ath_hal_attach to obtain a reference to an ath_hal 26 * structure for use with the device. Hardware-related operations that 27 * follow must call back into the HAL through interface, supplying the 28 * reference as the first parameter. 29 */ 30 31 #include "ah_osdep.h" 32 33 /* 34 * The maximum number of TX/RX chains supported. 35 * This is intended to be used by various statistics gathering operations 36 * (NF, RSSI, EVM). 37 */ 38 #define AH_MAX_CHAINS 3 39 #define AH_MIMO_MAX_EVM_PILOTS 6 40 41 /* 42 * __ahdecl is analogous to _cdecl; it defines the calling 43 * convention used within the HAL. For most systems this 44 * can just default to be empty and the compiler will (should) 45 * use _cdecl. For systems where _cdecl is not compatible this 46 * must be defined. See linux/ah_osdep.h for an example. 47 */ 48 #ifndef __ahdecl 49 #define __ahdecl 50 #endif 51 52 /* 53 * Status codes that may be returned by the HAL. Note that 54 * interfaces that return a status code set it only when an 55 * error occurs--i.e. you cannot check it for success. 56 */ 57 typedef enum { 58 HAL_OK = 0, /* No error */ 59 HAL_ENXIO = 1, /* No hardware present */ 60 HAL_ENOMEM = 2, /* Memory allocation failed */ 61 HAL_EIO = 3, /* Hardware didn't respond as expected */ 62 HAL_EEMAGIC = 4, /* EEPROM magic number invalid */ 63 HAL_EEVERSION = 5, /* EEPROM version invalid */ 64 HAL_EELOCKED = 6, /* EEPROM unreadable */ 65 HAL_EEBADSUM = 7, /* EEPROM checksum invalid */ 66 HAL_EEREAD = 8, /* EEPROM read problem */ 67 HAL_EEBADMAC = 9, /* EEPROM mac address invalid */ 68 HAL_EESIZE = 10, /* EEPROM size not supported */ 69 HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */ 70 HAL_EINVAL = 12, /* Invalid parameter to function */ 71 HAL_ENOTSUPP = 13, /* Hardware revision not supported */ 72 HAL_ESELFTEST = 14, /* Hardware self-test failed */ 73 HAL_EINPROGRESS = 15, /* Operation incomplete */ 74 HAL_EEBADREG = 16, /* EEPROM invalid regulatory contents */ 75 HAL_EEBADCC = 17, /* EEPROM invalid country code */ 76 HAL_INV_PMODE = 18, /* Couldn't bring out of sleep state */ 77 } HAL_STATUS; 78 79 typedef enum { 80 AH_FALSE = 0, /* NB: lots of code assumes false is zero */ 81 AH_TRUE = 1, 82 } HAL_BOOL; 83 84 typedef enum { 85 HAL_CAP_REG_DMN = 0, /* current regulatory domain */ 86 HAL_CAP_CIPHER = 1, /* hardware supports cipher */ 87 HAL_CAP_TKIP_MIC = 2, /* handle TKIP MIC in hardware */ 88 HAL_CAP_TKIP_SPLIT = 3, /* hardware TKIP uses split keys */ 89 HAL_CAP_PHYCOUNTERS = 4, /* hardware PHY error counters */ 90 HAL_CAP_DIVERSITY = 5, /* hardware supports fast diversity */ 91 HAL_CAP_KEYCACHE_SIZE = 6, /* number of entries in key cache */ 92 HAL_CAP_NUM_TXQUEUES = 7, /* number of hardware xmit queues */ 93 HAL_CAP_VEOL = 9, /* hardware supports virtual EOL */ 94 HAL_CAP_PSPOLL = 10, /* hardware has working PS-Poll support */ 95 HAL_CAP_DIAG = 11, /* hardware diagnostic support */ 96 HAL_CAP_COMPRESSION = 12, /* hardware supports compression */ 97 HAL_CAP_BURST = 13, /* hardware supports packet bursting */ 98 HAL_CAP_FASTFRAME = 14, /* hardware supoprts fast frames */ 99 HAL_CAP_TXPOW = 15, /* global tx power limit */ 100 HAL_CAP_TPC = 16, /* per-packet tx power control */ 101 HAL_CAP_PHYDIAG = 17, /* hardware phy error diagnostic */ 102 HAL_CAP_BSSIDMASK = 18, /* hardware supports bssid mask */ 103 HAL_CAP_MCAST_KEYSRCH = 19, /* hardware has multicast key search */ 104 HAL_CAP_TSF_ADJUST = 20, /* hardware has beacon tsf adjust */ 105 /* 21 was HAL_CAP_XR */ 106 HAL_CAP_WME_TKIPMIC = 22, /* hardware can support TKIP MIC when WMM is turned on */ 107 /* 23 was HAL_CAP_CHAN_HALFRATE */ 108 /* 24 was HAL_CAP_CHAN_QUARTERRATE */ 109 HAL_CAP_RFSILENT = 25, /* hardware has rfsilent support */ 110 HAL_CAP_TPC_ACK = 26, /* ack txpower with per-packet tpc */ 111 HAL_CAP_TPC_CTS = 27, /* cts txpower with per-packet tpc */ 112 HAL_CAP_11D = 28, /* 11d beacon support for changing cc */ 113 HAL_CAP_PCIE_PS = 29, 114 HAL_CAP_HT = 30, /* hardware can support HT */ 115 HAL_CAP_GTXTO = 31, /* hardware supports global tx timeout */ 116 HAL_CAP_FAST_CC = 32, /* hardware supports fast channel change */ 117 HAL_CAP_TX_CHAINMASK = 33, /* mask of TX chains supported */ 118 HAL_CAP_RX_CHAINMASK = 34, /* mask of RX chains supported */ 119 HAL_CAP_NUM_GPIO_PINS = 36, /* number of GPIO pins */ 120 121 HAL_CAP_CST = 38, /* hardware supports carrier sense timeout */ 122 HAL_CAP_RIFS_RX = 39, 123 HAL_CAP_RIFS_TX = 40, 124 HAL_CAP_FORCE_PPM = 41, 125 HAL_CAP_RTS_AGGR_LIMIT = 42, /* aggregation limit with RTS */ 126 HAL_CAP_4ADDR_AGGR = 43, /* hardware is capable of 4addr aggregation */ 127 HAL_CAP_DFS_DMN = 44, /* current DFS domain */ 128 HAL_CAP_EXT_CHAN_DFS = 45, /* DFS support for extension channel */ 129 HAL_CAP_COMBINED_RADAR_RSSI = 46, /* Is combined RSSI for radar accurate */ 130 131 HAL_CAP_AUTO_SLEEP = 48, /* hardware can go to network sleep 132 automatically after waking up to receive TIM */ 133 HAL_CAP_MBSSID_AGGR_SUPPORT = 49, /* Support for mBSSID Aggregation */ 134 HAL_CAP_SPLIT_4KB_TRANS = 50, /* hardware supports descriptors straddling a 4k page boundary */ 135 HAL_CAP_REG_FLAG = 51, /* Regulatory domain flags */ 136 HAL_CAP_BB_RIFS_HANG = 52, 137 HAL_CAP_RIFS_RX_ENABLED = 53, 138 HAL_CAP_BB_DFS_HANG = 54, 139 140 HAL_CAP_RX_STBC = 58, 141 HAL_CAP_TX_STBC = 59, 142 143 HAL_CAP_BT_COEX = 60, /* hardware is capable of bluetooth coexistence */ 144 HAL_CAP_DYNAMIC_SMPS = 61, /* Dynamic MIMO Power Save hardware support */ 145 146 HAL_CAP_DS = 67, /* 2 stream */ 147 HAL_CAP_BB_RX_CLEAR_STUCK_HANG = 68, 148 HAL_CAP_MAC_HANG = 69, /* can MAC hang */ 149 HAL_CAP_MFP = 70, /* Management Frame Protection in hardware */ 150 151 HAL_CAP_TS = 72, /* 3 stream */ 152 153 HAL_CAP_ENHANCED_DMA_SUPPORT = 75, /* DMA FIFO support */ 154 HAL_CAP_NUM_TXMAPS = 76, /* Number of buffers in a transmit descriptor */ 155 HAL_CAP_TXDESCLEN = 77, /* Length of transmit descriptor */ 156 HAL_CAP_TXSTATUSLEN = 78, /* Length of transmit status descriptor */ 157 HAL_CAP_RXSTATUSLEN = 79, /* Length of transmit status descriptor */ 158 HAL_CAP_RXFIFODEPTH = 80, /* Receive hardware FIFO depth */ 159 HAL_CAP_RXBUFSIZE = 81, /* Receive Buffer Length */ 160 HAL_CAP_NUM_MR_RETRIES = 82, /* limit on multirate retries */ 161 HAL_CAP_OL_PWRCTRL = 84, /* Open loop TX power control */ 162 HAL_CAP_SPECTRAL_SCAN = 90, /* Hardware supports spectral scan */ 163 164 HAL_CAP_BB_PANIC_WATCHDOG = 92, 165 166 HAL_CAP_HT20_SGI = 96, /* hardware supports HT20 short GI */ 167 168 HAL_CAP_LDPC = 99, 169 170 HAL_CAP_RXTSTAMP_PREC = 100, /* rx desc tstamp precision (bits) */ 171 172 HAL_CAP_ANT_DIV_COMB = 105, /* Enable antenna diversity/combining */ 173 HAL_CAP_PHYRESTART_CLR_WAR = 106, /* in some cases, clear phy restart to fix bb hang */ 174 HAL_CAP_ENTERPRISE_MODE = 107, /* Enterprise mode features */ 175 HAL_CAP_LDPCWAR = 108, 176 HAL_CAP_CHANNEL_SWITCH_TIME_USEC = 109, /* Channel change time, usec */ 177 HAL_CAP_ENABLE_APM = 110, /* APM enabled */ 178 HAL_CAP_PCIE_LCR_EXTSYNC_EN = 111, 179 HAL_CAP_PCIE_LCR_OFFSET = 112, 180 181 HAL_CAP_ENHANCED_DFS_SUPPORT = 117, /* hardware supports enhanced DFS */ 182 HAL_CAP_MCI = 118, 183 HAL_CAP_SMARTANTENNA = 119, 184 HAL_CAP_TRAFFIC_FAST_RECOVER = 120, 185 HAL_CAP_TX_DIVERSITY = 121, 186 HAL_CAP_CRDC = 122, 187 188 /* The following are private to the FreeBSD HAL (224 onward) */ 189 190 HAL_CAP_INTMIT = 229, /* interference mitigation */ 191 HAL_CAP_RXORN_FATAL = 230, /* HAL_INT_RXORN treated as fatal */ 192 HAL_CAP_BB_HANG = 235, /* can baseband hang */ 193 HAL_CAP_INTRMASK = 237, /* bitmask of supported interrupts */ 194 HAL_CAP_BSSIDMATCH = 238, /* hardware has disable bssid match */ 195 HAL_CAP_STREAMS = 239, /* how many 802.11n spatial streams are available */ 196 HAL_CAP_RXDESC_SELFLINK = 242, /* support a self-linked tail RX descriptor */ 197 HAL_CAP_BB_READ_WAR = 244, /* baseband read WAR */ 198 HAL_CAP_SERIALISE_WAR = 245, /* serialise register access on PCI */ 199 HAL_CAP_ENFORCE_TXOP = 246, /* Enforce TXOP if supported */ 200 HAL_CAP_RX_LNA_MIXING = 247, /* RX hardware uses LNA mixing */ 201 HAL_CAP_DO_MYBEACON = 248, /* Supports HAL_RX_FILTER_MYBEACON */ 202 HAL_CAP_TOA_LOCATIONING = 249, /* time of flight / arrival locationing */ 203 HAL_CAP_TXTSTAMP_PREC = 250, /* tx desc tstamp precision (bits) */ 204 } HAL_CAPABILITY_TYPE; 205 206 /* 207 * "States" for setting the LED. These correspond to 208 * the possible 802.11 operational states and there may 209 * be a many-to-one mapping between these states and the 210 * actual hardware state for the LED's (i.e. the hardware 211 * may have fewer states). 212 */ 213 typedef enum { 214 HAL_LED_INIT = 0, 215 HAL_LED_SCAN = 1, 216 HAL_LED_AUTH = 2, 217 HAL_LED_ASSOC = 3, 218 HAL_LED_RUN = 4 219 } HAL_LED_STATE; 220 221 /* 222 * Transmit queue types/numbers. These are used to tag 223 * each transmit queue in the hardware and to identify a set 224 * of transmit queues for operations such as start/stop dma. 225 */ 226 typedef enum { 227 HAL_TX_QUEUE_INACTIVE = 0, /* queue is inactive/unused */ 228 HAL_TX_QUEUE_DATA = 1, /* data xmit q's */ 229 HAL_TX_QUEUE_BEACON = 2, /* beacon xmit q */ 230 HAL_TX_QUEUE_CAB = 3, /* "crap after beacon" xmit q */ 231 HAL_TX_QUEUE_UAPSD = 4, /* u-apsd power save xmit q */ 232 HAL_TX_QUEUE_PSPOLL = 5, /* power save poll xmit q */ 233 HAL_TX_QUEUE_CFEND = 6, 234 HAL_TX_QUEUE_PAPRD = 7, 235 } HAL_TX_QUEUE; 236 237 #define HAL_NUM_TX_QUEUES 10 /* max possible # of queues */ 238 239 /* 240 * Receive queue types. These are used to tag 241 * each transmit queue in the hardware and to identify a set 242 * of transmit queues for operations such as start/stop dma. 243 */ 244 typedef enum { 245 HAL_RX_QUEUE_HP = 0, /* high priority recv queue */ 246 HAL_RX_QUEUE_LP = 1, /* low priority recv queue */ 247 } HAL_RX_QUEUE; 248 249 #define HAL_NUM_RX_QUEUES 2 /* max possible # of queues */ 250 251 #define HAL_TXFIFO_DEPTH 8 /* transmit fifo depth */ 252 253 /* 254 * Transmit queue subtype. These map directly to 255 * WME Access Categories (except for UPSD). Refer 256 * to Table 5 of the WME spec. 257 */ 258 typedef enum { 259 HAL_WME_AC_BK = 0, /* background access category */ 260 HAL_WME_AC_BE = 1, /* best effort access category*/ 261 HAL_WME_AC_VI = 2, /* video access category */ 262 HAL_WME_AC_VO = 3, /* voice access category */ 263 HAL_WME_UPSD = 4, /* uplink power save */ 264 } HAL_TX_QUEUE_SUBTYPE; 265 266 /* 267 * Transmit queue flags that control various 268 * operational parameters. 269 */ 270 typedef enum { 271 /* 272 * Per queue interrupt enables. When set the associated 273 * interrupt may be delivered for packets sent through 274 * the queue. Without these enabled no interrupts will 275 * be delivered for transmits through the queue. 276 */ 277 HAL_TXQ_TXOKINT_ENABLE = 0x0001, /* enable TXOK interrupt */ 278 HAL_TXQ_TXERRINT_ENABLE = 0x0001, /* enable TXERR interrupt */ 279 HAL_TXQ_TXDESCINT_ENABLE = 0x0002, /* enable TXDESC interrupt */ 280 HAL_TXQ_TXEOLINT_ENABLE = 0x0004, /* enable TXEOL interrupt */ 281 HAL_TXQ_TXURNINT_ENABLE = 0x0008, /* enable TXURN interrupt */ 282 /* 283 * Enable hardware compression for packets sent through 284 * the queue. The compression buffer must be setup and 285 * packets must have a key entry marked in the tx descriptor. 286 */ 287 HAL_TXQ_COMPRESSION_ENABLE = 0x0010, /* enable h/w compression */ 288 /* 289 * Disable queue when veol is hit or ready time expires. 290 * By default the queue is disabled only on reaching the 291 * physical end of queue (i.e. a null link ptr in the 292 * descriptor chain). 293 */ 294 HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE = 0x0020, 295 /* 296 * Schedule frames on delivery of a DBA (DMA Beacon Alert) 297 * event. Frames will be transmitted only when this timer 298 * fires, e.g to transmit a beacon in ap or adhoc modes. 299 */ 300 HAL_TXQ_DBA_GATED = 0x0040, /* schedule based on DBA */ 301 /* 302 * Each transmit queue has a counter that is incremented 303 * each time the queue is enabled and decremented when 304 * the list of frames to transmit is traversed (or when 305 * the ready time for the queue expires). This counter 306 * must be non-zero for frames to be scheduled for 307 * transmission. The following controls disable bumping 308 * this counter under certain conditions. Typically this 309 * is used to gate frames based on the contents of another 310 * queue (e.g. CAB traffic may only follow a beacon frame). 311 * These are meaningful only when frames are scheduled 312 * with a non-ASAP policy (e.g. DBA-gated). 313 */ 314 HAL_TXQ_CBR_DIS_QEMPTY = 0x0080, /* disable on this q empty */ 315 HAL_TXQ_CBR_DIS_BEMPTY = 0x0100, /* disable on beacon q empty */ 316 317 /* 318 * Fragment burst backoff policy. Normally the no backoff 319 * is done after a successful transmission, the next fragment 320 * is sent at SIFS. If this flag is set backoff is done 321 * after each fragment, regardless whether it was ack'd or 322 * not, after the backoff count reaches zero a normal channel 323 * access procedure is done before the next transmit (i.e. 324 * wait AIFS instead of SIFS). 325 */ 326 HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE = 0x00800000, 327 /* 328 * Disable post-tx backoff following each frame. 329 */ 330 HAL_TXQ_BACKOFF_DISABLE = 0x00010000, /* disable post backoff */ 331 /* 332 * DCU arbiter lockout control. This controls how 333 * lower priority tx queues are handled with respect to 334 * to a specific queue when multiple queues have frames 335 * to send. No lockout means lower priority queues arbitrate 336 * concurrently with this queue. Intra-frame lockout 337 * means lower priority queues are locked out until the 338 * current frame transmits (e.g. including backoffs and bursting). 339 * Global lockout means nothing lower can arbitrary so 340 * long as there is traffic activity on this queue (frames, 341 * backoff, etc). 342 */ 343 HAL_TXQ_ARB_LOCKOUT_INTRA = 0x00020000, /* intra-frame lockout */ 344 HAL_TXQ_ARB_LOCKOUT_GLOBAL = 0x00040000, /* full lockout s */ 345 346 HAL_TXQ_IGNORE_VIRTCOL = 0x00080000, /* ignore virt collisions */ 347 HAL_TXQ_SEQNUM_INC_DIS = 0x00100000, /* disable seqnum increment */ 348 } HAL_TX_QUEUE_FLAGS; 349 350 typedef struct { 351 uint32_t tqi_ver; /* hal TXQ version */ 352 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* subtype if applicable */ 353 HAL_TX_QUEUE_FLAGS tqi_qflags; /* flags (see above) */ 354 uint32_t tqi_priority; /* (not used) */ 355 uint32_t tqi_aifs; /* aifs */ 356 uint32_t tqi_cwmin; /* cwMin */ 357 uint32_t tqi_cwmax; /* cwMax */ 358 uint16_t tqi_shretry; /* rts retry limit */ 359 uint16_t tqi_lgretry; /* long retry limit (not used)*/ 360 uint32_t tqi_cbrPeriod; /* CBR period (us) */ 361 uint32_t tqi_cbrOverflowLimit; /* threshold for CBROVF int */ 362 uint32_t tqi_burstTime; /* max burst duration (us) */ 363 uint32_t tqi_readyTime; /* frame schedule time (us) */ 364 uint32_t tqi_compBuf; /* comp buffer phys addr */ 365 } HAL_TXQ_INFO; 366 367 #define HAL_TQI_NONVAL 0xffff 368 369 /* token to use for aifs, cwmin, cwmax */ 370 #define HAL_TXQ_USEDEFAULT ((uint32_t) -1) 371 372 /* compression definitions */ 373 #define HAL_COMP_BUF_MAX_SIZE 9216 /* 9K */ 374 #define HAL_COMP_BUF_ALIGN_SIZE 512 375 376 /* 377 * Transmit packet types. This belongs in ah_desc.h, but 378 * is here so we can give a proper type to various parameters 379 * (and not require everyone include the file). 380 * 381 * NB: These values are intentionally assigned for 382 * direct use when setting up h/w descriptors. 383 */ 384 typedef enum { 385 HAL_PKT_TYPE_NORMAL = 0, 386 HAL_PKT_TYPE_ATIM = 1, 387 HAL_PKT_TYPE_PSPOLL = 2, 388 HAL_PKT_TYPE_BEACON = 3, 389 HAL_PKT_TYPE_PROBE_RESP = 4, 390 HAL_PKT_TYPE_CHIRP = 5, 391 HAL_PKT_TYPE_GRP_POLL = 6, 392 HAL_PKT_TYPE_AMPDU = 7, 393 } HAL_PKT_TYPE; 394 395 /* Rx Filter Frame Types */ 396 typedef enum { 397 /* 398 * These bits correspond to AR_RX_FILTER for all chips. 399 * Not all bits are supported by all chips. 400 */ 401 HAL_RX_FILTER_UCAST = 0x00000001, /* Allow unicast frames */ 402 HAL_RX_FILTER_MCAST = 0x00000002, /* Allow multicast frames */ 403 HAL_RX_FILTER_BCAST = 0x00000004, /* Allow broadcast frames */ 404 HAL_RX_FILTER_CONTROL = 0x00000008, /* Allow control frames */ 405 HAL_RX_FILTER_BEACON = 0x00000010, /* Allow beacon frames */ 406 HAL_RX_FILTER_PROM = 0x00000020, /* Promiscuous mode */ 407 HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */ 408 HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */ 409 HAL_RX_FILTER_MYBEACON = 0x00000200, /* Filter beacons other than mine */ 410 HAL_RX_FILTER_COMPBAR = 0x00000400, /* Allow compressed BAR */ 411 HAL_RX_FILTER_COMP_BA = 0x00000800, /* Allow compressed blockack */ 412 HAL_RX_FILTER_PHYRADAR = 0x00002000, /* Allow phy radar errors */ 413 HAL_RX_FILTER_PSPOLL = 0x00004000, /* Allow PS-POLL frames */ 414 HAL_RX_FILTER_MCAST_BCAST_ALL = 0x00008000, 415 /* Allow all mcast/bcast frames */ 416 417 /* 418 * Magic RX filter flags that aren't targeting hardware bits 419 * but instead the HAL sets individual bits - eg PHYERR will result 420 * in OFDM/CCK timing error frames being received. 421 */ 422 HAL_RX_FILTER_BSSID = 0x40000000, /* Disable BSSID match */ 423 } HAL_RX_FILTER; 424 425 typedef enum { 426 HAL_PM_AWAKE = 0, 427 HAL_PM_FULL_SLEEP = 1, 428 HAL_PM_NETWORK_SLEEP = 2, 429 HAL_PM_UNDEFINED = 3 430 } HAL_POWER_MODE; 431 432 /* 433 * Enterprise mode flags 434 */ 435 #define AH_ENT_DUAL_BAND_DISABLE 0x00000001 436 #define AH_ENT_CHAIN2_DISABLE 0x00000002 437 #define AH_ENT_5MHZ_DISABLE 0x00000004 438 #define AH_ENT_10MHZ_DISABLE 0x00000008 439 #define AH_ENT_49GHZ_DISABLE 0x00000010 440 #define AH_ENT_LOOPBACK_DISABLE 0x00000020 441 #define AH_ENT_TPC_PERF_DISABLE 0x00000040 442 #define AH_ENT_MIN_PKT_SIZE_DISABLE 0x00000080 443 #define AH_ENT_SPECTRAL_PRECISION 0x00000300 444 #define AH_ENT_SPECTRAL_PRECISION_S 8 445 #define AH_ENT_RTSCTS_DELIM_WAR 0x00010000 446 447 #define AH_FIRST_DESC_NDELIMS 60 448 449 /* 450 * NOTE WELL: 451 * These are mapped to take advantage of the common locations for many of 452 * the bits on all of the currently supported MAC chips. This is to make 453 * the ISR as efficient as possible, while still abstracting HW differences. 454 * When new hardware breaks this commonality this enumerated type, as well 455 * as the HAL functions using it, must be modified. All values are directly 456 * mapped unless commented otherwise. 457 */ 458 typedef enum { 459 HAL_INT_RX = 0x00000001, /* Non-common mapping */ 460 HAL_INT_RXDESC = 0x00000002, /* Legacy mapping */ 461 HAL_INT_RXERR = 0x00000004, 462 HAL_INT_RXHP = 0x00000001, /* EDMA */ 463 HAL_INT_RXLP = 0x00000002, /* EDMA */ 464 HAL_INT_RXNOFRM = 0x00000008, 465 HAL_INT_RXEOL = 0x00000010, 466 HAL_INT_RXORN = 0x00000020, 467 HAL_INT_TX = 0x00000040, /* Non-common mapping */ 468 HAL_INT_TXDESC = 0x00000080, 469 HAL_INT_TIM_TIMER= 0x00000100, 470 HAL_INT_MCI = 0x00000200, 471 HAL_INT_BBPANIC = 0x00000400, 472 HAL_INT_TXURN = 0x00000800, 473 HAL_INT_MIB = 0x00001000, 474 HAL_INT_RXPHY = 0x00004000, 475 HAL_INT_RXKCM = 0x00008000, 476 HAL_INT_SWBA = 0x00010000, 477 HAL_INT_BRSSI = 0x00020000, 478 HAL_INT_BMISS = 0x00040000, 479 HAL_INT_BNR = 0x00100000, 480 HAL_INT_TIM = 0x00200000, /* Non-common mapping */ 481 HAL_INT_DTIM = 0x00400000, /* Non-common mapping */ 482 HAL_INT_DTIMSYNC= 0x00800000, /* Non-common mapping */ 483 HAL_INT_GPIO = 0x01000000, 484 HAL_INT_CABEND = 0x02000000, /* Non-common mapping */ 485 HAL_INT_TSFOOR = 0x04000000, /* Non-common mapping */ 486 HAL_INT_TBTT = 0x08000000, /* Non-common mapping */ 487 /* Atheros ref driver has a generic timer interrupt now..*/ 488 HAL_INT_GENTIMER = 0x08000000, /* Non-common mapping */ 489 HAL_INT_CST = 0x10000000, /* Non-common mapping */ 490 HAL_INT_GTT = 0x20000000, /* Non-common mapping */ 491 HAL_INT_FATAL = 0x40000000, /* Non-common mapping */ 492 #define HAL_INT_GLOBAL 0x80000000 /* Set/clear IER */ 493 HAL_INT_BMISC = HAL_INT_TIM 494 | HAL_INT_DTIM 495 | HAL_INT_DTIMSYNC 496 | HAL_INT_CABEND 497 | HAL_INT_TBTT, 498 499 /* Interrupt bits that map directly to ISR/IMR bits */ 500 HAL_INT_COMMON = HAL_INT_RXNOFRM 501 | HAL_INT_RXDESC 502 | HAL_INT_RXEOL 503 | HAL_INT_RXORN 504 | HAL_INT_TXDESC 505 | HAL_INT_TXURN 506 | HAL_INT_MIB 507 | HAL_INT_RXPHY 508 | HAL_INT_RXKCM 509 | HAL_INT_SWBA 510 | HAL_INT_BMISS 511 | HAL_INT_BRSSI 512 | HAL_INT_BNR 513 | HAL_INT_GPIO, 514 } HAL_INT; 515 516 /* 517 * MSI vector assignments 518 */ 519 typedef enum { 520 HAL_MSIVEC_MISC = 0, 521 HAL_MSIVEC_TX = 1, 522 HAL_MSIVEC_RXLP = 2, 523 HAL_MSIVEC_RXHP = 3, 524 } HAL_MSIVEC; 525 526 typedef enum { 527 HAL_INT_LINE = 0, 528 HAL_INT_MSI = 1, 529 } HAL_INT_TYPE; 530 531 /* For interrupt mitigation registers */ 532 typedef enum { 533 HAL_INT_RX_FIRSTPKT=0, 534 HAL_INT_RX_LASTPKT, 535 HAL_INT_TX_FIRSTPKT, 536 HAL_INT_TX_LASTPKT, 537 HAL_INT_THRESHOLD 538 } HAL_INT_MITIGATION; 539 540 /* XXX this is duplicate information! */ 541 typedef struct { 542 u_int32_t cyclecnt_diff; /* delta cycle count */ 543 u_int32_t rxclr_cnt; /* rx clear count */ 544 u_int32_t extrxclr_cnt; /* ext chan rx clear count */ 545 u_int32_t txframecnt_diff; /* delta tx frame count */ 546 u_int32_t rxframecnt_diff; /* delta rx frame count */ 547 u_int32_t listen_time; /* listen time in msec - time for which ch is free */ 548 u_int32_t ofdmphyerr_cnt; /* OFDM err count since last reset */ 549 u_int32_t cckphyerr_cnt; /* CCK err count since last reset */ 550 u_int32_t ofdmphyerrcnt_diff; /* delta OFDM Phy Error Count */ 551 HAL_BOOL valid; /* if the stats are valid*/ 552 } HAL_ANISTATS; 553 554 typedef struct { 555 u_int8_t txctl_offset; 556 u_int8_t txctl_numwords; 557 u_int8_t txstatus_offset; 558 u_int8_t txstatus_numwords; 559 560 u_int8_t rxctl_offset; 561 u_int8_t rxctl_numwords; 562 u_int8_t rxstatus_offset; 563 u_int8_t rxstatus_numwords; 564 565 u_int8_t macRevision; 566 } HAL_DESC_INFO; 567 568 typedef enum { 569 HAL_GPIO_OUTPUT_MUX_AS_OUTPUT = 0, 570 HAL_GPIO_OUTPUT_MUX_PCIE_ATTENTION_LED = 1, 571 HAL_GPIO_OUTPUT_MUX_PCIE_POWER_LED = 2, 572 HAL_GPIO_OUTPUT_MUX_MAC_NETWORK_LED = 3, 573 HAL_GPIO_OUTPUT_MUX_MAC_POWER_LED = 4, 574 HAL_GPIO_OUTPUT_MUX_AS_WLAN_ACTIVE = 5, 575 HAL_GPIO_OUTPUT_MUX_AS_TX_FRAME = 6, 576 577 HAL_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA, 578 HAL_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK, 579 HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA, 580 HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK, 581 HAL_GPIO_OUTPUT_MUX_AS_WL_IN_TX, 582 HAL_GPIO_OUTPUT_MUX_AS_WL_IN_RX, 583 HAL_GPIO_OUTPUT_MUX_AS_BT_IN_TX, 584 HAL_GPIO_OUTPUT_MUX_AS_BT_IN_RX, 585 HAL_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE, 586 HAL_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA, 587 HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL0, 588 HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL1, 589 HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL2, 590 HAL_GPIO_OUTPUT_MUX_NUM_ENTRIES 591 } HAL_GPIO_MUX_TYPE; 592 593 typedef enum { 594 HAL_GPIO_INTR_LOW = 0, 595 HAL_GPIO_INTR_HIGH = 1, 596 HAL_GPIO_INTR_DISABLE = 2 597 } HAL_GPIO_INTR_TYPE; 598 599 typedef struct halCounters { 600 u_int32_t tx_frame_count; 601 u_int32_t rx_frame_count; 602 u_int32_t rx_clear_count; 603 u_int32_t cycle_count; 604 u_int8_t is_rx_active; // true (1) or false (0) 605 u_int8_t is_tx_active; // true (1) or false (0) 606 } HAL_COUNTERS; 607 608 typedef enum { 609 HAL_RFGAIN_INACTIVE = 0, 610 HAL_RFGAIN_READ_REQUESTED = 1, 611 HAL_RFGAIN_NEED_CHANGE = 2 612 } HAL_RFGAIN; 613 614 typedef uint16_t HAL_CTRY_CODE; /* country code */ 615 typedef uint16_t HAL_REG_DOMAIN; /* regulatory domain code */ 616 617 #define HAL_ANTENNA_MIN_MODE 0 618 #define HAL_ANTENNA_FIXED_A 1 619 #define HAL_ANTENNA_FIXED_B 2 620 #define HAL_ANTENNA_MAX_MODE 3 621 622 typedef struct { 623 uint32_t ackrcv_bad; 624 uint32_t rts_bad; 625 uint32_t rts_good; 626 uint32_t fcs_bad; 627 uint32_t beacons; 628 } HAL_MIB_STATS; 629 630 /* 631 * These bits represent what's in ah_currentRDext. 632 */ 633 typedef enum { 634 REG_EXT_FCC_MIDBAND = 0, 635 REG_EXT_JAPAN_MIDBAND = 1, 636 REG_EXT_FCC_DFS_HT40 = 2, 637 REG_EXT_JAPAN_NONDFS_HT40 = 3, 638 REG_EXT_JAPAN_DFS_HT40 = 4 639 } REG_EXT_BITMAP; 640 641 enum { 642 HAL_MODE_11A = 0x001, /* 11a channels */ 643 HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */ 644 HAL_MODE_11B = 0x004, /* 11b channels */ 645 HAL_MODE_PUREG = 0x008, /* 11g channels (OFDM only) */ 646 #ifdef notdef 647 HAL_MODE_11G = 0x010, /* 11g channels (OFDM/CCK) */ 648 #else 649 HAL_MODE_11G = 0x008, /* XXX historical */ 650 #endif 651 HAL_MODE_108G = 0x020, /* 11g+Turbo channels */ 652 HAL_MODE_108A = 0x040, /* 11a+Turbo channels */ 653 HAL_MODE_11A_HALF_RATE = 0x200, /* 11a half width channels */ 654 HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11a quarter width channels */ 655 HAL_MODE_11G_HALF_RATE = 0x800, /* 11g half width channels */ 656 HAL_MODE_11G_QUARTER_RATE = 0x1000, /* 11g quarter width channels */ 657 HAL_MODE_11NG_HT20 = 0x008000, 658 HAL_MODE_11NA_HT20 = 0x010000, 659 HAL_MODE_11NG_HT40PLUS = 0x020000, 660 HAL_MODE_11NG_HT40MINUS = 0x040000, 661 HAL_MODE_11NA_HT40PLUS = 0x080000, 662 HAL_MODE_11NA_HT40MINUS = 0x100000, 663 HAL_MODE_ALL = 0xffffff 664 }; 665 666 typedef struct { 667 int rateCount; /* NB: for proper padding */ 668 uint8_t rateCodeToIndex[256]; /* back mapping */ 669 struct { 670 uint8_t valid; /* valid for rate control use */ 671 uint8_t phy; /* CCK/OFDM/XR */ 672 uint32_t rateKbps; /* transfer rate in kbs */ 673 uint8_t rateCode; /* rate for h/w descriptors */ 674 uint8_t shortPreamble; /* mask for enabling short 675 * preamble in CCK rate code */ 676 uint8_t dot11Rate; /* value for supported rates 677 * info element of MLME */ 678 uint8_t controlRate; /* index of next lower basic 679 * rate; used for dur. calcs */ 680 uint16_t lpAckDuration; /* long preamble ACK duration */ 681 uint16_t spAckDuration; /* short preamble ACK duration*/ 682 } info[64]; 683 } HAL_RATE_TABLE; 684 685 typedef struct { 686 u_int rs_count; /* number of valid entries */ 687 uint8_t rs_rates[64]; /* rates */ 688 } HAL_RATE_SET; 689 690 /* 691 * 802.11n specific structures and enums 692 */ 693 typedef enum { 694 HAL_CHAINTYPE_TX = 1, /* Tx chain type */ 695 HAL_CHAINTYPE_RX = 2, /* RX chain type */ 696 } HAL_CHAIN_TYPE; 697 698 typedef struct { 699 u_int Tries; 700 u_int Rate; /* hardware rate code */ 701 u_int RateIndex; /* rate series table index */ 702 u_int PktDuration; 703 u_int ChSel; 704 u_int RateFlags; 705 #define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */ 706 #define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */ 707 #define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */ 708 #define HAL_RATESERIES_STBC 0x0008 /* use STBC for series */ 709 u_int tx_power_cap; /* in 1/2 dBm units XXX TODO */ 710 } HAL_11N_RATE_SERIES; 711 712 typedef enum { 713 HAL_HT_MACMODE_20 = 0, /* 20 MHz operation */ 714 HAL_HT_MACMODE_2040 = 1, /* 20/40 MHz operation */ 715 } HAL_HT_MACMODE; 716 717 typedef enum { 718 HAL_HT_PHYMODE_20 = 0, /* 20 MHz operation */ 719 HAL_HT_PHYMODE_2040 = 1, /* 20/40 MHz operation */ 720 } HAL_HT_PHYMODE; 721 722 typedef enum { 723 HAL_HT_EXTPROTSPACING_20 = 0, /* 20 MHz spacing */ 724 HAL_HT_EXTPROTSPACING_25 = 1, /* 25 MHz spacing */ 725 } HAL_HT_EXTPROTSPACING; 726 727 728 typedef enum { 729 HAL_RX_CLEAR_CTL_LOW = 0x1, /* force control channel to appear busy */ 730 HAL_RX_CLEAR_EXT_LOW = 0x2, /* force extension channel to appear busy */ 731 } HAL_HT_RXCLEAR; 732 733 typedef enum { 734 HAL_FREQ_BAND_5GHZ = 0, 735 HAL_FREQ_BAND_2GHZ = 1, 736 } HAL_FREQ_BAND; 737 738 /* 739 * Antenna switch control. By default antenna selection 740 * enables multiple (2) antenna use. To force use of the 741 * A or B antenna only specify a fixed setting. Fixing 742 * the antenna will also disable any diversity support. 743 */ 744 typedef enum { 745 HAL_ANT_VARIABLE = 0, /* variable by programming */ 746 HAL_ANT_FIXED_A = 1, /* fixed antenna A */ 747 HAL_ANT_FIXED_B = 2, /* fixed antenna B */ 748 } HAL_ANT_SETTING; 749 750 typedef enum { 751 HAL_M_STA = 1, /* infrastructure station */ 752 HAL_M_IBSS = 0, /* IBSS (adhoc) station */ 753 HAL_M_HOSTAP = 6, /* Software Access Point */ 754 HAL_M_MONITOR = 8 /* Monitor mode */ 755 } HAL_OPMODE; 756 757 typedef enum { 758 HAL_RESET_NORMAL = 0, /* Do normal reset */ 759 HAL_RESET_BBPANIC = 1, /* Reset because of BB panic */ 760 HAL_RESET_FORCE_COLD = 2, /* Force full reset */ 761 } HAL_RESET_TYPE; 762 763 typedef struct { 764 uint8_t kv_type; /* one of HAL_CIPHER */ 765 uint8_t kv_apsd; /* Mask for APSD enabled ACs */ 766 uint16_t kv_len; /* length in bits */ 767 uint8_t kv_val[16]; /* enough for 128-bit keys */ 768 uint8_t kv_mic[8]; /* TKIP MIC key */ 769 uint8_t kv_txmic[8]; /* TKIP TX MIC key (optional) */ 770 } HAL_KEYVAL; 771 772 /* 773 * This is the TX descriptor field which marks the key padding requirement. 774 * The naming is unfortunately unclear. 775 */ 776 #define AH_KEYTYPE_MASK 0x0F 777 typedef enum { 778 HAL_KEY_TYPE_CLEAR, 779 HAL_KEY_TYPE_WEP, 780 HAL_KEY_TYPE_AES, 781 HAL_KEY_TYPE_TKIP, 782 } HAL_KEY_TYPE; 783 784 typedef enum { 785 HAL_CIPHER_WEP = 0, 786 HAL_CIPHER_AES_OCB = 1, 787 HAL_CIPHER_AES_CCM = 2, 788 HAL_CIPHER_CKIP = 3, 789 HAL_CIPHER_TKIP = 4, 790 HAL_CIPHER_CLR = 5, /* no encryption */ 791 792 HAL_CIPHER_MIC = 127 /* TKIP-MIC, not a cipher */ 793 } HAL_CIPHER; 794 795 enum { 796 HAL_SLOT_TIME_6 = 6, /* NB: for turbo mode */ 797 HAL_SLOT_TIME_9 = 9, 798 HAL_SLOT_TIME_20 = 20, 799 }; 800 801 /* 802 * Per-station beacon timer state. Note that the specified 803 * beacon interval (given in TU's) can also include flags 804 * to force a TSF reset and to enable the beacon xmit logic. 805 * If bs_cfpmaxduration is non-zero the hardware is setup to 806 * coexist with a PCF-capable AP. 807 */ 808 typedef struct { 809 uint32_t bs_nexttbtt; /* next beacon in TU */ 810 uint32_t bs_nextdtim; /* next DTIM in TU */ 811 uint32_t bs_intval; /* beacon interval+flags */ 812 /* 813 * HAL_BEACON_PERIOD, HAL_BEACON_ENA and HAL_BEACON_RESET_TSF 814 * are all 1:1 correspondances with the pre-11n chip AR_BEACON 815 * register. 816 */ 817 #define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */ 818 #define HAL_BEACON_PERIOD_TU8 0x0007ffff /* beacon interval, tu/8 */ 819 #define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */ 820 #define HAL_BEACON_RESET_TSF 0x01000000 /* clear TSF */ 821 #define HAL_TSFOOR_THRESHOLD 0x00004240 /* TSF OOR thresh (16k uS) */ 822 uint32_t bs_dtimperiod; 823 uint16_t bs_cfpperiod; /* CFP period in TU */ 824 uint16_t bs_cfpmaxduration; /* max CFP duration in TU */ 825 uint32_t bs_cfpnext; /* next CFP in TU */ 826 uint16_t bs_timoffset; /* byte offset to TIM bitmap */ 827 uint16_t bs_bmissthreshold; /* beacon miss threshold */ 828 uint32_t bs_sleepduration; /* max sleep duration */ 829 uint32_t bs_tsfoor_threshold; /* TSF out of range threshold */ 830 } HAL_BEACON_STATE; 831 832 /* 833 * Like HAL_BEACON_STATE but for non-station mode setup. 834 * NB: see above flag definitions for bt_intval. 835 */ 836 typedef struct { 837 uint32_t bt_intval; /* beacon interval+flags */ 838 uint32_t bt_nexttbtt; /* next beacon in TU */ 839 uint32_t bt_nextatim; /* next ATIM in TU */ 840 uint32_t bt_nextdba; /* next DBA in 1/8th TU */ 841 uint32_t bt_nextswba; /* next SWBA in 1/8th TU */ 842 uint32_t bt_flags; /* timer enables */ 843 #define HAL_BEACON_TBTT_EN 0x00000001 844 #define HAL_BEACON_DBA_EN 0x00000002 845 #define HAL_BEACON_SWBA_EN 0x00000004 846 } HAL_BEACON_TIMERS; 847 848 /* 849 * Per-node statistics maintained by the driver for use in 850 * optimizing signal quality and other operational aspects. 851 */ 852 typedef struct { 853 uint32_t ns_avgbrssi; /* average beacon rssi */ 854 uint32_t ns_avgrssi; /* average data rssi */ 855 uint32_t ns_avgtxrssi; /* average tx rssi */ 856 } HAL_NODE_STATS; 857 858 #define HAL_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */ 859 860 /* 861 * This is the ANI state and MIB stats. 862 * 863 * It's used by the HAL modules to keep state /and/ by the debug ioctl 864 * to fetch ANI information. 865 */ 866 typedef struct { 867 uint32_t ast_ani_niup; /* ANI increased noise immunity */ 868 uint32_t ast_ani_nidown; /* ANI decreased noise immunity */ 869 uint32_t ast_ani_spurup; /* ANI increased spur immunity */ 870 uint32_t ast_ani_spurdown;/* ANI descreased spur immunity */ 871 uint32_t ast_ani_ofdmon; /* ANI OFDM weak signal detect on */ 872 uint32_t ast_ani_ofdmoff;/* ANI OFDM weak signal detect off */ 873 uint32_t ast_ani_cckhigh;/* ANI CCK weak signal threshold high */ 874 uint32_t ast_ani_ccklow; /* ANI CCK weak signal threshold low */ 875 uint32_t ast_ani_stepup; /* ANI increased first step level */ 876 uint32_t ast_ani_stepdown;/* ANI decreased first step level */ 877 uint32_t ast_ani_ofdmerrs;/* ANI cumulative ofdm phy err count */ 878 uint32_t ast_ani_cckerrs;/* ANI cumulative cck phy err count */ 879 uint32_t ast_ani_reset; /* ANI parameters zero'd for non-STA */ 880 uint32_t ast_ani_lzero; /* ANI listen time forced to zero */ 881 uint32_t ast_ani_lneg; /* ANI listen time calculated < 0 */ 882 HAL_MIB_STATS ast_mibstats; /* MIB counter stats */ 883 HAL_NODE_STATS ast_nodestats; /* Latest rssi stats from driver */ 884 } HAL_ANI_STATS; 885 886 typedef struct { 887 uint8_t noiseImmunityLevel; 888 uint8_t spurImmunityLevel; 889 uint8_t firstepLevel; 890 uint8_t ofdmWeakSigDetectOff; 891 uint8_t cckWeakSigThreshold; 892 uint32_t listenTime; 893 894 /* NB: intentionally ordered so data exported to user space is first */ 895 uint32_t txFrameCount; /* Last txFrameCount */ 896 uint32_t rxFrameCount; /* Last rx Frame count */ 897 uint32_t cycleCount; /* Last cycleCount 898 (to detect wrap-around) */ 899 uint32_t ofdmPhyErrCount;/* OFDM err count since last reset */ 900 uint32_t cckPhyErrCount; /* CCK err count since last reset */ 901 } HAL_ANI_STATE; 902 903 struct ath_desc; 904 struct ath_tx_status; 905 struct ath_rx_status; 906 struct ieee80211_channel; 907 908 /* 909 * This is a channel survey sample entry. 910 * 911 * The AR5212 ANI routines fill these samples. The ANI code then uses it 912 * when calculating listen time; it is also exported via a diagnostic 913 * API. 914 */ 915 typedef struct { 916 uint32_t seq_num; 917 uint32_t tx_busy; 918 uint32_t rx_busy; 919 uint32_t chan_busy; 920 uint32_t ext_chan_busy; 921 uint32_t cycle_count; 922 /* XXX TODO */ 923 uint32_t ofdm_phyerr_count; 924 uint32_t cck_phyerr_count; 925 } HAL_SURVEY_SAMPLE; 926 927 /* 928 * This provides 3.2 seconds of sample space given an 929 * ANI time of 1/10th of a second. This may not be enough! 930 */ 931 #define CHANNEL_SURVEY_SAMPLE_COUNT 32 932 933 typedef struct { 934 HAL_SURVEY_SAMPLE samples[CHANNEL_SURVEY_SAMPLE_COUNT]; 935 uint32_t cur_sample; /* current sample in sequence */ 936 uint32_t cur_seq; /* current sequence number */ 937 } HAL_CHANNEL_SURVEY; 938 939 /* 940 * ANI commands. 941 * 942 * These are used both internally and externally via the diagnostic 943 * API. 944 * 945 * Note that this is NOT the ANI commands being used via the INTMIT 946 * capability - that has a different mapping for some reason. 947 */ 948 typedef enum { 949 HAL_ANI_PRESENT = 0, /* is ANI support present */ 950 HAL_ANI_NOISE_IMMUNITY_LEVEL = 1, /* set level */ 951 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION = 2, /* enable/disable */ 952 HAL_ANI_CCK_WEAK_SIGNAL_THR = 3, /* enable/disable */ 953 HAL_ANI_FIRSTEP_LEVEL = 4, /* set level */ 954 HAL_ANI_SPUR_IMMUNITY_LEVEL = 5, /* set level */ 955 HAL_ANI_MODE = 6, /* 0 => manual, 1 => auto (XXX do not change) */ 956 HAL_ANI_PHYERR_RESET = 7, /* reset phy error stats */ 957 HAL_ANI_MRC_CCK = 8, 958 } HAL_ANI_CMD; 959 960 #define HAL_ANI_ALL 0xffffffff 961 962 /* 963 * This is the layout of the ANI INTMIT capability. 964 * 965 * Notice that the command values differ to HAL_ANI_CMD. 966 */ 967 typedef enum { 968 HAL_CAP_INTMIT_PRESENT = 0, 969 HAL_CAP_INTMIT_ENABLE = 1, 970 HAL_CAP_INTMIT_NOISE_IMMUNITY_LEVEL = 2, 971 HAL_CAP_INTMIT_OFDM_WEAK_SIGNAL_LEVEL = 3, 972 HAL_CAP_INTMIT_CCK_WEAK_SIGNAL_THR = 4, 973 HAL_CAP_INTMIT_FIRSTEP_LEVEL = 5, 974 HAL_CAP_INTMIT_SPUR_IMMUNITY_LEVEL = 6 975 } HAL_CAP_INTMIT_CMD; 976 977 typedef struct { 978 int32_t pe_firpwr; /* FIR pwr out threshold */ 979 int32_t pe_rrssi; /* Radar rssi thresh */ 980 int32_t pe_height; /* Pulse height thresh */ 981 int32_t pe_prssi; /* Pulse rssi thresh */ 982 int32_t pe_inband; /* Inband thresh */ 983 984 /* The following params are only for AR5413 and later */ 985 u_int32_t pe_relpwr; /* Relative power threshold in 0.5dB steps */ 986 u_int32_t pe_relstep; /* Pulse Relative step threshold in 0.5dB steps */ 987 u_int32_t pe_maxlen; /* Max length of radar sign in 0.8us units */ 988 int32_t pe_usefir128; /* Use the average in-band power measured over 128 cycles */ 989 int32_t pe_blockradar; /* 990 * Enable to block radar check if pkt detect is done via OFDM 991 * weak signal detect or pkt is detected immediately after tx 992 * to rx transition 993 */ 994 int32_t pe_enmaxrssi; /* 995 * Enable to use the max rssi instead of the last rssi during 996 * fine gain changes for radar detection 997 */ 998 int32_t pe_extchannel; /* Enable DFS on ext channel */ 999 int32_t pe_enabled; /* Whether radar detection is enabled */ 1000 int32_t pe_enrelpwr; 1001 int32_t pe_en_relstep_check; 1002 } HAL_PHYERR_PARAM; 1003 1004 #define HAL_PHYERR_PARAM_NOVAL 65535 1005 1006 typedef struct { 1007 u_int16_t ss_fft_period; /* Skip interval for FFT reports */ 1008 u_int16_t ss_period; /* Spectral scan period */ 1009 u_int16_t ss_count; /* # of reports to return from ss_active */ 1010 u_int16_t ss_short_report;/* Set to report ony 1 set of FFT results */ 1011 u_int8_t radar_bin_thresh_sel; /* strong signal radar FFT threshold configuration */ 1012 u_int16_t ss_spectral_pri; /* are we doing a noise power cal ? */ 1013 int8_t ss_nf_cal[AH_MAX_CHAINS*2]; /* nf calibrated values for ctl+ext from eeprom */ 1014 int8_t ss_nf_pwr[AH_MAX_CHAINS*2]; /* nf pwr values for ctl+ext from eeprom */ 1015 int32_t ss_nf_temp_data; /* temperature data taken during nf scan */ 1016 int ss_enabled; 1017 int ss_active; 1018 } HAL_SPECTRAL_PARAM; 1019 #define HAL_SPECTRAL_PARAM_NOVAL 0xFFFF 1020 #define HAL_SPECTRAL_PARAM_ENABLE 0x8000 /* Enable/Disable if applicable */ 1021 1022 /* 1023 * DFS operating mode flags. 1024 */ 1025 typedef enum { 1026 HAL_DFS_UNINIT_DOMAIN = 0, /* Uninitialized dfs domain */ 1027 HAL_DFS_FCC_DOMAIN = 1, /* FCC3 dfs domain */ 1028 HAL_DFS_ETSI_DOMAIN = 2, /* ETSI dfs domain */ 1029 HAL_DFS_MKK4_DOMAIN = 3, /* Japan dfs domain */ 1030 } HAL_DFS_DOMAIN; 1031 1032 1033 /* 1034 * MFP decryption options for initializing the MAC. 1035 */ 1036 typedef enum { 1037 HAL_MFP_QOSDATA = 0, /* Decrypt MFP frames like QoS data frames. All chips before Merlin. */ 1038 HAL_MFP_PASSTHRU, /* Don't decrypt MFP frames at all. Passthrough */ 1039 HAL_MFP_HW_CRYPTO /* hardware decryption enabled. Merlin can do it. */ 1040 } HAL_MFP_OPT_T; 1041 1042 /* LNA config supported */ 1043 typedef enum { 1044 HAL_ANT_DIV_COMB_LNA1_MINUS_LNA2 = 0, 1045 HAL_ANT_DIV_COMB_LNA2 = 1, 1046 HAL_ANT_DIV_COMB_LNA1 = 2, 1047 HAL_ANT_DIV_COMB_LNA1_PLUS_LNA2 = 3, 1048 } HAL_ANT_DIV_COMB_LNA_CONF; 1049 1050 typedef struct { 1051 u_int8_t main_lna_conf; 1052 u_int8_t alt_lna_conf; 1053 u_int8_t fast_div_bias; 1054 u_int8_t main_gaintb; 1055 u_int8_t alt_gaintb; 1056 u_int8_t antdiv_configgroup; 1057 int8_t lna1_lna2_delta; 1058 } HAL_ANT_COMB_CONFIG; 1059 1060 #define DEFAULT_ANTDIV_CONFIG_GROUP 0x00 1061 #define HAL_ANTDIV_CONFIG_GROUP_1 0x01 1062 #define HAL_ANTDIV_CONFIG_GROUP_2 0x02 1063 #define HAL_ANTDIV_CONFIG_GROUP_3 0x03 1064 1065 /* 1066 * Flag for setting QUIET period 1067 */ 1068 typedef enum { 1069 HAL_QUIET_DISABLE = 0x0, 1070 HAL_QUIET_ENABLE = 0x1, 1071 HAL_QUIET_ADD_CURRENT_TSF = 0x2, /* add current TSF to next_start offset */ 1072 HAL_QUIET_ADD_SWBA_RESP_TIME = 0x4, /* add beacon response time to next_start offset */ 1073 } HAL_QUIET_FLAG; 1074 1075 #define HAL_DFS_EVENT_PRICH 0x0000001 1076 #define HAL_DFS_EVENT_EXTCH 0x0000002 1077 #define HAL_DFS_EVENT_EXTEARLY 0x0000004 1078 #define HAL_DFS_EVENT_ISDC 0x0000008 1079 1080 struct hal_dfs_event { 1081 uint64_t re_full_ts; /* 64-bit full timestamp from interrupt time */ 1082 uint32_t re_ts; /* Original 15 bit recv timestamp */ 1083 uint8_t re_rssi; /* rssi of radar event */ 1084 uint8_t re_dur; /* duration of radar pulse */ 1085 uint32_t re_flags; /* Flags (see above) */ 1086 }; 1087 typedef struct hal_dfs_event HAL_DFS_EVENT; 1088 1089 /* 1090 * Generic Timer domain 1091 */ 1092 typedef enum { 1093 HAL_GEN_TIMER_TSF = 0, 1094 HAL_GEN_TIMER_TSF2, 1095 HAL_GEN_TIMER_TSF_ANY 1096 } HAL_GEN_TIMER_DOMAIN; 1097 1098 /* 1099 * BT Co-existence definitions 1100 */ 1101 #include "ath_hal/ah_btcoex.h" 1102 1103 struct hal_bb_panic_info { 1104 u_int32_t status; 1105 u_int32_t tsf; 1106 u_int32_t phy_panic_wd_ctl1; 1107 u_int32_t phy_panic_wd_ctl2; 1108 u_int32_t phy_gen_ctrl; 1109 u_int32_t rxc_pcnt; 1110 u_int32_t rxf_pcnt; 1111 u_int32_t txf_pcnt; 1112 u_int32_t cycles; 1113 u_int32_t wd; 1114 u_int32_t det; 1115 u_int32_t rdar; 1116 u_int32_t r_odfm; 1117 u_int32_t r_cck; 1118 u_int32_t t_odfm; 1119 u_int32_t t_cck; 1120 u_int32_t agc; 1121 u_int32_t src; 1122 }; 1123 1124 /* Serialize Register Access Mode */ 1125 typedef enum { 1126 SER_REG_MODE_OFF = 0, 1127 SER_REG_MODE_ON = 1, 1128 SER_REG_MODE_AUTO = 2, 1129 } SER_REG_MODE; 1130 1131 typedef struct 1132 { 1133 int ah_debug; /* only used if AH_DEBUG is defined */ 1134 int ah_ar5416_biasadj; /* enable AR2133 radio specific bias fiddling */ 1135 1136 /* NB: these are deprecated; they exist for now for compatibility */ 1137 int ah_dma_beacon_response_time;/* in TU's */ 1138 int ah_sw_beacon_response_time; /* in TU's */ 1139 int ah_additional_swba_backoff; /* in TU's */ 1140 int ah_force_full_reset; /* force full chip reset rather then warm reset */ 1141 int ah_serialise_reg_war; /* force serialisation of register IO */ 1142 1143 /* XXX these don't belong here, they're just for the ar9300 HAL port effort */ 1144 int ath_hal_desc_tpc; /* Per-packet TPC */ 1145 int ath_hal_sta_update_tx_pwr_enable; /* GreenTX */ 1146 int ath_hal_sta_update_tx_pwr_enable_S1; /* GreenTX */ 1147 int ath_hal_sta_update_tx_pwr_enable_S2; /* GreenTX */ 1148 int ath_hal_sta_update_tx_pwr_enable_S3; /* GreenTX */ 1149 1150 /* I'm not sure what the default values for these should be */ 1151 int ath_hal_pll_pwr_save; 1152 int ath_hal_pcie_power_save_enable; 1153 int ath_hal_intr_mitigation_rx; 1154 int ath_hal_intr_mitigation_tx; 1155 1156 int ath_hal_pcie_clock_req; 1157 #define AR_PCIE_PLL_PWRSAVE_CONTROL (1<<0) 1158 #define AR_PCIE_PLL_PWRSAVE_ON_D3 (1<<1) 1159 #define AR_PCIE_PLL_PWRSAVE_ON_D0 (1<<2) 1160 1161 int ath_hal_pcie_waen; 1162 int ath_hal_pcie_ser_des_write; 1163 1164 /* these are important for correct AR9300 behaviour */ 1165 int ath_hal_ht_enable; /* needs to be enabled for AR9300 HT */ 1166 int ath_hal_diversity_control; 1167 int ath_hal_antenna_switch_swap; 1168 int ath_hal_ext_lna_ctl_gpio; 1169 int ath_hal_spur_mode; 1170 int ath_hal_6mb_ack; /* should set this to 1 for 11a/11na? */ 1171 int ath_hal_enable_msi; /* enable MSI interrupts (needed?) */ 1172 int ath_hal_beacon_filter_interval; /* ok to be 0 for now? */ 1173 1174 /* For now, set this to 0 - net80211 needs to know about hardware MFP support */ 1175 int ath_hal_mfp_support; 1176 1177 int ath_hal_enable_ani; /* should set this.. */ 1178 int ath_hal_cwm_ignore_ext_cca; 1179 int ath_hal_show_bb_panic; 1180 int ath_hal_ant_ctrl_comm2g_switch_enable; 1181 int ath_hal_ext_atten_margin_cfg; 1182 int ath_hal_min_gainidx; 1183 int ath_hal_war70c; 1184 uint32_t ath_hal_mci_config; 1185 } HAL_OPS_CONFIG; 1186 1187 /* 1188 * Hardware Access Layer (HAL) API. 1189 * 1190 * Clients of the HAL call ath_hal_attach to obtain a reference to an 1191 * ath_hal structure for use with the device. Hardware-related operations 1192 * that follow must call back into the HAL through interface, supplying 1193 * the reference as the first parameter. Note that before using the 1194 * reference returned by ath_hal_attach the caller should verify the 1195 * ABI version number. 1196 */ 1197 struct ath_hal { 1198 uint32_t ah_magic; /* consistency check magic number */ 1199 uint16_t ah_devid; /* PCI device ID */ 1200 uint16_t ah_subvendorid; /* PCI subvendor ID */ 1201 HAL_SOFTC ah_sc; /* back pointer to driver/os state */ 1202 HAL_BUS_TAG ah_st; /* params for register r+w */ 1203 HAL_BUS_HANDLE ah_sh; 1204 HAL_CTRY_CODE ah_countryCode; 1205 1206 uint32_t ah_macVersion; /* MAC version id */ 1207 uint16_t ah_macRev; /* MAC revision */ 1208 uint16_t ah_phyRev; /* PHY revision */ 1209 /* NB: when only one radio is present the rev is in 5Ghz */ 1210 uint16_t ah_analog5GhzRev;/* 5GHz radio revision */ 1211 uint16_t ah_analog2GhzRev;/* 2GHz radio revision */ 1212 1213 uint16_t *ah_eepromdata; /* eeprom buffer, if needed */ 1214 1215 uint32_t ah_intrstate[8]; /* last int state */ 1216 uint32_t ah_syncstate; /* last sync intr state */ 1217 1218 /* Current powerstate from HAL calls */ 1219 HAL_POWER_MODE ah_powerMode; 1220 1221 HAL_OPS_CONFIG ah_config; 1222 const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *, 1223 u_int mode); 1224 void __ahdecl(*ah_detach)(struct ath_hal*); 1225 1226 /* Reset functions */ 1227 HAL_BOOL __ahdecl(*ah_reset)(struct ath_hal *, HAL_OPMODE, 1228 struct ieee80211_channel *, 1229 HAL_BOOL bChannelChange, 1230 HAL_RESET_TYPE resetType, 1231 HAL_STATUS *status); 1232 HAL_BOOL __ahdecl(*ah_phyDisable)(struct ath_hal *); 1233 HAL_BOOL __ahdecl(*ah_disable)(struct ath_hal *); 1234 void __ahdecl(*ah_configPCIE)(struct ath_hal *, HAL_BOOL restore, 1235 HAL_BOOL power_off); 1236 void __ahdecl(*ah_disablePCIE)(struct ath_hal *); 1237 void __ahdecl(*ah_setPCUConfig)(struct ath_hal *); 1238 HAL_BOOL __ahdecl(*ah_perCalibration)(struct ath_hal*, 1239 struct ieee80211_channel *, HAL_BOOL *); 1240 HAL_BOOL __ahdecl(*ah_perCalibrationN)(struct ath_hal *, 1241 struct ieee80211_channel *, u_int chainMask, 1242 HAL_BOOL longCal, HAL_BOOL *isCalDone); 1243 HAL_BOOL __ahdecl(*ah_resetCalValid)(struct ath_hal *, 1244 const struct ieee80211_channel *); 1245 HAL_BOOL __ahdecl(*ah_setTxPower)(struct ath_hal *, 1246 const struct ieee80211_channel *, uint16_t *); 1247 HAL_BOOL __ahdecl(*ah_setTxPowerLimit)(struct ath_hal *, uint32_t); 1248 HAL_BOOL __ahdecl(*ah_setBoardValues)(struct ath_hal *, 1249 const struct ieee80211_channel *); 1250 1251 /* Transmit functions */ 1252 HAL_BOOL __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*, 1253 HAL_BOOL incTrigLevel); 1254 int __ahdecl(*ah_setupTxQueue)(struct ath_hal *, HAL_TX_QUEUE, 1255 const HAL_TXQ_INFO *qInfo); 1256 HAL_BOOL __ahdecl(*ah_setTxQueueProps)(struct ath_hal *, int q, 1257 const HAL_TXQ_INFO *qInfo); 1258 HAL_BOOL __ahdecl(*ah_getTxQueueProps)(struct ath_hal *, int q, 1259 HAL_TXQ_INFO *qInfo); 1260 HAL_BOOL __ahdecl(*ah_releaseTxQueue)(struct ath_hal *ah, u_int q); 1261 HAL_BOOL __ahdecl(*ah_resetTxQueue)(struct ath_hal *ah, u_int q); 1262 uint32_t __ahdecl(*ah_getTxDP)(struct ath_hal*, u_int); 1263 HAL_BOOL __ahdecl(*ah_setTxDP)(struct ath_hal*, u_int, uint32_t txdp); 1264 uint32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, u_int q); 1265 HAL_BOOL __ahdecl(*ah_startTxDma)(struct ath_hal*, u_int); 1266 HAL_BOOL __ahdecl(*ah_stopTxDma)(struct ath_hal*, u_int); 1267 HAL_BOOL __ahdecl(*ah_setupTxDesc)(struct ath_hal *, struct ath_desc *, 1268 u_int pktLen, u_int hdrLen, 1269 HAL_PKT_TYPE type, u_int txPower, 1270 u_int txRate0, u_int txTries0, 1271 u_int keyIx, u_int antMode, u_int flags, 1272 u_int rtsctsRate, u_int rtsctsDuration, 1273 u_int compicvLen, u_int compivLen, 1274 u_int comp); 1275 HAL_BOOL __ahdecl(*ah_setupXTxDesc)(struct ath_hal *, struct ath_desc*, 1276 u_int txRate1, u_int txTries1, 1277 u_int txRate2, u_int txTries2, 1278 u_int txRate3, u_int txTries3); 1279 HAL_BOOL __ahdecl(*ah_fillTxDesc)(struct ath_hal *, struct ath_desc *, 1280 HAL_DMA_ADDR *bufAddrList, uint32_t *segLenList, 1281 u_int descId, u_int qcuId, HAL_BOOL firstSeg, 1282 HAL_BOOL lastSeg, const struct ath_desc *); 1283 HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *, 1284 struct ath_desc *, struct ath_tx_status *); 1285 void __ahdecl(*ah_getTxIntrQueue)(struct ath_hal *, uint32_t *); 1286 void __ahdecl(*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc*); 1287 HAL_BOOL __ahdecl(*ah_getTxCompletionRates)(struct ath_hal *, 1288 const struct ath_desc *ds, int *rates, int *tries); 1289 void __ahdecl(*ah_setTxDescLink)(struct ath_hal *ah, void *ds, 1290 uint32_t link); 1291 void __ahdecl(*ah_getTxDescLink)(struct ath_hal *ah, void *ds, 1292 uint32_t *link); 1293 void __ahdecl(*ah_getTxDescLinkPtr)(struct ath_hal *ah, void *ds, 1294 uint32_t **linkptr); 1295 void __ahdecl(*ah_setupTxStatusRing)(struct ath_hal *, 1296 void *ts_start, uint32_t ts_paddr_start, 1297 uint16_t size); 1298 void __ahdecl(*ah_getTxRawTxDesc)(struct ath_hal *, u_int32_t *); 1299 1300 /* Receive Functions */ 1301 uint32_t __ahdecl(*ah_getRxDP)(struct ath_hal*, HAL_RX_QUEUE); 1302 void __ahdecl(*ah_setRxDP)(struct ath_hal*, uint32_t rxdp, HAL_RX_QUEUE); 1303 void __ahdecl(*ah_enableReceive)(struct ath_hal*); 1304 HAL_BOOL __ahdecl(*ah_stopDmaReceive)(struct ath_hal*); 1305 void __ahdecl(*ah_startPcuReceive)(struct ath_hal*); 1306 void __ahdecl(*ah_stopPcuReceive)(struct ath_hal*); 1307 void __ahdecl(*ah_setMulticastFilter)(struct ath_hal*, 1308 uint32_t filter0, uint32_t filter1); 1309 HAL_BOOL __ahdecl(*ah_setMulticastFilterIndex)(struct ath_hal*, 1310 uint32_t index); 1311 HAL_BOOL __ahdecl(*ah_clrMulticastFilterIndex)(struct ath_hal*, 1312 uint32_t index); 1313 uint32_t __ahdecl(*ah_getRxFilter)(struct ath_hal*); 1314 void __ahdecl(*ah_setRxFilter)(struct ath_hal*, uint32_t); 1315 HAL_BOOL __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_desc *, 1316 uint32_t size, u_int flags); 1317 HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *, 1318 struct ath_desc *, uint32_t phyAddr, 1319 struct ath_desc *next, uint64_t tsf, 1320 struct ath_rx_status *); 1321 void __ahdecl(*ah_rxMonitor)(struct ath_hal *, 1322 const HAL_NODE_STATS *, 1323 const struct ieee80211_channel *); 1324 void __ahdecl(*ah_aniPoll)(struct ath_hal *, 1325 const struct ieee80211_channel *); 1326 void __ahdecl(*ah_procMibEvent)(struct ath_hal *, 1327 const HAL_NODE_STATS *); 1328 1329 /* Misc Functions */ 1330 HAL_STATUS __ahdecl(*ah_getCapability)(struct ath_hal *, 1331 HAL_CAPABILITY_TYPE, uint32_t capability, 1332 uint32_t *result); 1333 HAL_BOOL __ahdecl(*ah_setCapability)(struct ath_hal *, 1334 HAL_CAPABILITY_TYPE, uint32_t capability, 1335 uint32_t setting, HAL_STATUS *); 1336 HAL_BOOL __ahdecl(*ah_getDiagState)(struct ath_hal *, int request, 1337 const void *args, uint32_t argsize, 1338 void **result, uint32_t *resultsize); 1339 void __ahdecl(*ah_getMacAddress)(struct ath_hal *, uint8_t *); 1340 HAL_BOOL __ahdecl(*ah_setMacAddress)(struct ath_hal *, const uint8_t*); 1341 void __ahdecl(*ah_getBssIdMask)(struct ath_hal *, uint8_t *); 1342 HAL_BOOL __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const uint8_t*); 1343 HAL_BOOL __ahdecl(*ah_setRegulatoryDomain)(struct ath_hal*, 1344 uint16_t, HAL_STATUS *); 1345 void __ahdecl(*ah_setLedState)(struct ath_hal*, HAL_LED_STATE); 1346 void __ahdecl(*ah_writeAssocid)(struct ath_hal*, 1347 const uint8_t *bssid, uint16_t assocId); 1348 HAL_BOOL __ahdecl(*ah_gpioCfgOutput)(struct ath_hal *, 1349 uint32_t gpio, HAL_GPIO_MUX_TYPE); 1350 HAL_BOOL __ahdecl(*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio); 1351 uint32_t __ahdecl(*ah_gpioGet)(struct ath_hal *, uint32_t gpio); 1352 HAL_BOOL __ahdecl(*ah_gpioSet)(struct ath_hal *, 1353 uint32_t gpio, uint32_t val); 1354 void __ahdecl(*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t); 1355 uint32_t __ahdecl(*ah_getTsf32)(struct ath_hal*); 1356 uint64_t __ahdecl(*ah_getTsf64)(struct ath_hal*); 1357 void __ahdecl(*ah_setTsf64)(struct ath_hal *, uint64_t); 1358 void __ahdecl(*ah_resetTsf)(struct ath_hal*); 1359 HAL_BOOL __ahdecl(*ah_detectCardPresent)(struct ath_hal*); 1360 void __ahdecl(*ah_updateMibCounters)(struct ath_hal*, 1361 HAL_MIB_STATS*); 1362 HAL_RFGAIN __ahdecl(*ah_getRfGain)(struct ath_hal*); 1363 u_int __ahdecl(*ah_getDefAntenna)(struct ath_hal*); 1364 void __ahdecl(*ah_setDefAntenna)(struct ath_hal*, u_int); 1365 HAL_ANT_SETTING __ahdecl(*ah_getAntennaSwitch)(struct ath_hal*); 1366 HAL_BOOL __ahdecl(*ah_setAntennaSwitch)(struct ath_hal*, 1367 HAL_ANT_SETTING); 1368 HAL_BOOL __ahdecl(*ah_setSifsTime)(struct ath_hal*, u_int); 1369 u_int __ahdecl(*ah_getSifsTime)(struct ath_hal*); 1370 HAL_BOOL __ahdecl(*ah_setSlotTime)(struct ath_hal*, u_int); 1371 u_int __ahdecl(*ah_getSlotTime)(struct ath_hal*); 1372 HAL_BOOL __ahdecl(*ah_setAckTimeout)(struct ath_hal*, u_int); 1373 u_int __ahdecl(*ah_getAckTimeout)(struct ath_hal*); 1374 HAL_BOOL __ahdecl(*ah_setAckCTSRate)(struct ath_hal*, u_int); 1375 u_int __ahdecl(*ah_getAckCTSRate)(struct ath_hal*); 1376 HAL_BOOL __ahdecl(*ah_setCTSTimeout)(struct ath_hal*, u_int); 1377 u_int __ahdecl(*ah_getCTSTimeout)(struct ath_hal*); 1378 HAL_BOOL __ahdecl(*ah_setDecompMask)(struct ath_hal*, uint16_t, int); 1379 void __ahdecl(*ah_setCoverageClass)(struct ath_hal*, uint8_t, int); 1380 HAL_STATUS __ahdecl(*ah_setQuiet)(struct ath_hal *ah, uint32_t period, 1381 uint32_t duration, uint32_t nextStart, 1382 HAL_QUIET_FLAG flag); 1383 void __ahdecl(*ah_setChainMasks)(struct ath_hal *, 1384 uint32_t, uint32_t); 1385 1386 /* DFS functions */ 1387 void __ahdecl(*ah_enableDfs)(struct ath_hal *ah, 1388 HAL_PHYERR_PARAM *pe); 1389 void __ahdecl(*ah_getDfsThresh)(struct ath_hal *ah, 1390 HAL_PHYERR_PARAM *pe); 1391 HAL_BOOL __ahdecl(*ah_getDfsDefaultThresh)(struct ath_hal *ah, 1392 HAL_PHYERR_PARAM *pe); 1393 HAL_BOOL __ahdecl(*ah_procRadarEvent)(struct ath_hal *ah, 1394 struct ath_rx_status *rxs, uint64_t fulltsf, 1395 const char *buf, HAL_DFS_EVENT *event); 1396 HAL_BOOL __ahdecl(*ah_isFastClockEnabled)(struct ath_hal *ah); 1397 1398 /* Spectral Scan functions */ 1399 void __ahdecl(*ah_spectralConfigure)(struct ath_hal *ah, 1400 HAL_SPECTRAL_PARAM *sp); 1401 void __ahdecl(*ah_spectralGetConfig)(struct ath_hal *ah, 1402 HAL_SPECTRAL_PARAM *sp); 1403 void __ahdecl(*ah_spectralStart)(struct ath_hal *); 1404 void __ahdecl(*ah_spectralStop)(struct ath_hal *); 1405 HAL_BOOL __ahdecl(*ah_spectralIsEnabled)(struct ath_hal *); 1406 HAL_BOOL __ahdecl(*ah_spectralIsActive)(struct ath_hal *); 1407 /* XXX getNfPri() and getNfExt() */ 1408 1409 /* Key Cache Functions */ 1410 uint32_t __ahdecl(*ah_getKeyCacheSize)(struct ath_hal*); 1411 HAL_BOOL __ahdecl(*ah_resetKeyCacheEntry)(struct ath_hal*, uint16_t); 1412 HAL_BOOL __ahdecl(*ah_isKeyCacheEntryValid)(struct ath_hal *, 1413 uint16_t); 1414 HAL_BOOL __ahdecl(*ah_setKeyCacheEntry)(struct ath_hal*, 1415 uint16_t, const HAL_KEYVAL *, 1416 const uint8_t *, int); 1417 HAL_BOOL __ahdecl(*ah_setKeyCacheEntryMac)(struct ath_hal*, 1418 uint16_t, const uint8_t *); 1419 1420 /* Power Management Functions */ 1421 HAL_BOOL __ahdecl(*ah_setPowerMode)(struct ath_hal*, 1422 HAL_POWER_MODE mode, int setChip); 1423 HAL_POWER_MODE __ahdecl(*ah_getPowerMode)(struct ath_hal*); 1424 int16_t __ahdecl(*ah_getChanNoise)(struct ath_hal *, 1425 const struct ieee80211_channel *); 1426 1427 /* Beacon Management Functions */ 1428 void __ahdecl(*ah_setBeaconTimers)(struct ath_hal*, 1429 const HAL_BEACON_TIMERS *); 1430 /* NB: deprecated, use ah_setBeaconTimers instead */ 1431 void __ahdecl(*ah_beaconInit)(struct ath_hal *, 1432 uint32_t nexttbtt, uint32_t intval); 1433 void __ahdecl(*ah_setStationBeaconTimers)(struct ath_hal*, 1434 const HAL_BEACON_STATE *); 1435 void __ahdecl(*ah_resetStationBeaconTimers)(struct ath_hal*); 1436 uint64_t __ahdecl(*ah_getNextTBTT)(struct ath_hal *); 1437 1438 /* 802.11n Functions */ 1439 HAL_BOOL __ahdecl(*ah_chainTxDesc)(struct ath_hal *, 1440 struct ath_desc *, 1441 HAL_DMA_ADDR *bufAddrList, 1442 uint32_t *segLenList, 1443 u_int, u_int, HAL_PKT_TYPE, 1444 u_int, HAL_CIPHER, uint8_t, HAL_BOOL, 1445 HAL_BOOL, HAL_BOOL); 1446 HAL_BOOL __ahdecl(*ah_setupFirstTxDesc)(struct ath_hal *, 1447 struct ath_desc *, u_int, u_int, u_int, 1448 u_int, u_int, u_int, u_int, u_int); 1449 HAL_BOOL __ahdecl(*ah_setupLastTxDesc)(struct ath_hal *, 1450 struct ath_desc *, const struct ath_desc *); 1451 void __ahdecl(*ah_set11nRateScenario)(struct ath_hal *, 1452 struct ath_desc *, u_int, u_int, 1453 HAL_11N_RATE_SERIES [], u_int, u_int); 1454 1455 /* 1456 * The next 4 (set11ntxdesc -> set11naggrlast) are specific 1457 * to the EDMA HAL. Descriptors are chained together by 1458 * using filltxdesc (not ChainTxDesc) and then setting the 1459 * aggregate flags appropriately using first/middle/last. 1460 */ 1461 void __ahdecl(*ah_set11nTxDesc)(struct ath_hal *, 1462 void *, u_int, HAL_PKT_TYPE, u_int, u_int, 1463 u_int); 1464 void __ahdecl(*ah_set11nAggrFirst)(struct ath_hal *, 1465 struct ath_desc *, u_int, u_int); 1466 void __ahdecl(*ah_set11nAggrMiddle)(struct ath_hal *, 1467 struct ath_desc *, u_int); 1468 void __ahdecl(*ah_set11nAggrLast)(struct ath_hal *, 1469 struct ath_desc *); 1470 void __ahdecl(*ah_clr11nAggr)(struct ath_hal *, 1471 struct ath_desc *); 1472 void __ahdecl(*ah_set11nBurstDuration)(struct ath_hal *, 1473 struct ath_desc *, u_int); 1474 void __ahdecl(*ah_set11nVirtMoreFrag)(struct ath_hal *, 1475 struct ath_desc *, u_int); 1476 1477 HAL_BOOL __ahdecl(*ah_getMibCycleCounts) (struct ath_hal *, 1478 HAL_SURVEY_SAMPLE *); 1479 1480 uint32_t __ahdecl(*ah_get11nExtBusy)(struct ath_hal *); 1481 void __ahdecl(*ah_set11nMac2040)(struct ath_hal *, 1482 HAL_HT_MACMODE); 1483 HAL_HT_RXCLEAR __ahdecl(*ah_get11nRxClear)(struct ath_hal *ah); 1484 void __ahdecl(*ah_set11nRxClear)(struct ath_hal *, 1485 HAL_HT_RXCLEAR); 1486 1487 /* Interrupt functions */ 1488 HAL_BOOL __ahdecl(*ah_isInterruptPending)(struct ath_hal*); 1489 HAL_BOOL __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT*); 1490 HAL_INT __ahdecl(*ah_getInterrupts)(struct ath_hal*); 1491 HAL_INT __ahdecl(*ah_setInterrupts)(struct ath_hal*, HAL_INT); 1492 1493 /* Bluetooth Coexistence functions */ 1494 void __ahdecl(*ah_btCoexSetInfo)(struct ath_hal *, 1495 HAL_BT_COEX_INFO *); 1496 void __ahdecl(*ah_btCoexSetConfig)(struct ath_hal *, 1497 HAL_BT_COEX_CONFIG *); 1498 void __ahdecl(*ah_btCoexSetQcuThresh)(struct ath_hal *, 1499 int); 1500 void __ahdecl(*ah_btCoexSetWeights)(struct ath_hal *, 1501 uint32_t); 1502 void __ahdecl(*ah_btCoexSetBmissThresh)(struct ath_hal *, 1503 uint32_t); 1504 void __ahdecl(*ah_btCoexSetParameter)(struct ath_hal *, 1505 uint32_t, uint32_t); 1506 void __ahdecl(*ah_btCoexDisable)(struct ath_hal *); 1507 int __ahdecl(*ah_btCoexEnable)(struct ath_hal *); 1508 1509 /* Bluetooth MCI methods */ 1510 void __ahdecl(*ah_btMciSetup)(struct ath_hal *, 1511 uint32_t, void *, uint16_t, uint32_t); 1512 HAL_BOOL __ahdecl(*ah_btMciSendMessage)(struct ath_hal *, 1513 uint8_t, uint32_t, uint32_t *, uint8_t, 1514 HAL_BOOL, HAL_BOOL); 1515 uint32_t __ahdecl(*ah_btMciGetInterrupt)(struct ath_hal *, 1516 uint32_t *, uint32_t *); 1517 uint32_t __ahdecl(*ah_btMciState)(struct ath_hal *, 1518 uint32_t, uint32_t *); 1519 void __ahdecl(*ah_btMciDetach)(struct ath_hal *); 1520 1521 /* LNA diversity configuration */ 1522 void __ahdecl(*ah_divLnaConfGet)(struct ath_hal *, 1523 HAL_ANT_COMB_CONFIG *); 1524 void __ahdecl(*ah_divLnaConfSet)(struct ath_hal *, 1525 HAL_ANT_COMB_CONFIG *); 1526 }; 1527 1528 /* 1529 * Check the PCI vendor ID and device ID against Atheros' values 1530 * and return a printable description for any Atheros hardware. 1531 * AH_NULL is returned if the ID's do not describe Atheros hardware. 1532 */ 1533 extern const char *__ahdecl ath_hal_probe(uint16_t vendorid, uint16_t devid); 1534 1535 /* 1536 * Attach the HAL for use with the specified device. The device is 1537 * defined by the PCI device ID. The caller provides an opaque pointer 1538 * to an upper-layer data structure (HAL_SOFTC) that is stored in the 1539 * HAL state block for later use. Hardware register accesses are done 1540 * using the specified bus tag and handle. On successful return a 1541 * reference to a state block is returned that must be supplied in all 1542 * subsequent HAL calls. Storage associated with this reference is 1543 * dynamically allocated and must be freed by calling the ah_detach 1544 * method when the client is done. If the attach operation fails a 1545 * null (AH_NULL) reference will be returned and a status code will 1546 * be returned if the status parameter is non-zero. 1547 */ 1548 extern struct ath_hal * __ahdecl ath_hal_attach(uint16_t devid, HAL_SOFTC, 1549 HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, 1550 HAL_OPS_CONFIG *ah_config, HAL_STATUS* status); 1551 1552 extern const char *ath_hal_mac_name(struct ath_hal *); 1553 extern const char *ath_hal_rf_name(struct ath_hal *); 1554 1555 /* 1556 * Regulatory interfaces. Drivers should use ath_hal_init_channels to 1557 * request a set of channels for a particular country code and/or 1558 * regulatory domain. If CTRY_DEFAULT and SKU_NONE are specified then 1559 * this list is constructed according to the contents of the EEPROM. 1560 * ath_hal_getchannels acts similarly but does not alter the operating 1561 * state; this can be used to collect information for a particular 1562 * regulatory configuration. Finally ath_hal_set_channels installs a 1563 * channel list constructed outside the driver. The HAL will adopt the 1564 * channel list and setup internal state according to the specified 1565 * regulatory configuration (e.g. conformance test limits). 1566 * 1567 * For all interfaces the channel list is returned in the supplied array. 1568 * maxchans defines the maximum size of this array. nchans contains the 1569 * actual number of channels returned. If a problem occurred then a 1570 * status code != HAL_OK is returned. 1571 */ 1572 struct ieee80211_channel; 1573 1574 /* 1575 * Return a list of channels according to the specified regulatory. 1576 */ 1577 extern HAL_STATUS __ahdecl ath_hal_getchannels(struct ath_hal *, 1578 struct ieee80211_channel *chans, u_int maxchans, int *nchans, 1579 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn, 1580 HAL_BOOL enableExtendedChannels); 1581 1582 /* 1583 * Return a list of channels and install it as the current operating 1584 * regulatory list. 1585 */ 1586 extern HAL_STATUS __ahdecl ath_hal_init_channels(struct ath_hal *, 1587 struct ieee80211_channel *chans, u_int maxchans, int *nchans, 1588 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN rd, 1589 HAL_BOOL enableExtendedChannels); 1590 1591 /* 1592 * Install the list of channels as the current operating regulatory 1593 * and setup related state according to the country code and sku. 1594 */ 1595 extern HAL_STATUS __ahdecl ath_hal_set_channels(struct ath_hal *, 1596 struct ieee80211_channel *chans, int nchans, 1597 HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn); 1598 1599 /* 1600 * Fetch the ctl/ext noise floor values reported by a MIMO 1601 * radio. Returns 1 for valid results, 0 for invalid channel. 1602 */ 1603 extern int __ahdecl ath_hal_get_mimo_chan_noise(struct ath_hal *ah, 1604 const struct ieee80211_channel *chan, int16_t *nf_ctl, 1605 int16_t *nf_ext); 1606 1607 /* 1608 * Calibrate noise floor data following a channel scan or similar. 1609 * This must be called prior retrieving noise floor data. 1610 */ 1611 extern void __ahdecl ath_hal_process_noisefloor(struct ath_hal *ah); 1612 1613 /* 1614 * Return bit mask of wireless modes supported by the hardware. 1615 */ 1616 extern u_int __ahdecl ath_hal_getwirelessmodes(struct ath_hal*); 1617 1618 /* 1619 * Get the HAL wireless mode for the given channel. 1620 */ 1621 extern int ath_hal_get_curmode(struct ath_hal *ah, 1622 const struct ieee80211_channel *chan); 1623 1624 /* 1625 * Calculate the packet TX time for a legacy or 11n frame 1626 */ 1627 extern uint32_t __ahdecl ath_hal_pkt_txtime(struct ath_hal *ah, 1628 const HAL_RATE_TABLE *rates, uint32_t frameLen, 1629 uint16_t rateix, HAL_BOOL isht40, HAL_BOOL shortPreamble, 1630 HAL_BOOL includeSifs); 1631 1632 /* 1633 * Calculate the duration of an 11n frame. 1634 */ 1635 extern uint32_t __ahdecl ath_computedur_ht(uint32_t frameLen, uint16_t rate, 1636 int streams, HAL_BOOL isht40, HAL_BOOL isShortGI); 1637 1638 /* 1639 * Calculate the transmit duration of a legacy frame. 1640 */ 1641 extern uint16_t __ahdecl ath_hal_computetxtime(struct ath_hal *, 1642 const HAL_RATE_TABLE *rates, uint32_t frameLen, 1643 uint16_t rateix, HAL_BOOL shortPreamble, 1644 HAL_BOOL includeSifs); 1645 1646 /* 1647 * Adjust the TSF. 1648 */ 1649 extern void __ahdecl ath_hal_adjusttsf(struct ath_hal *ah, int32_t tsfdelta); 1650 1651 /* 1652 * Enable or disable CCA. 1653 */ 1654 void __ahdecl ath_hal_setcca(struct ath_hal *ah, int ena); 1655 1656 /* 1657 * Get CCA setting. 1658 */ 1659 int __ahdecl ath_hal_getcca(struct ath_hal *ah); 1660 1661 /* 1662 * Read EEPROM data from ah_eepromdata 1663 */ 1664 HAL_BOOL __ahdecl ath_hal_EepromDataRead(struct ath_hal *ah, 1665 u_int off, uint16_t *data); 1666 1667 /* 1668 * For now, simply pass through MFP frames. 1669 */ 1670 static inline u_int32_t 1671 ath_hal_get_mfp_qos(struct ath_hal *ah) 1672 { 1673 //return AH_PRIVATE(ah)->ah_mfp_qos; 1674 return HAL_MFP_QOSDATA; 1675 } 1676 1677 /* 1678 * Convert between microseconds and core system clocks. 1679 */ 1680 extern u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs); 1681 extern u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks); 1682 extern uint64_t ath_hal_mac_psec(struct ath_hal *ah, u_int clks); 1683 1684 #endif /* _ATH_AH_H_ */ 1685