1 /*- 2 * SPDX-License-Identifier: ISC 3 * 4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 5 * Copyright (c) 2002-2008 Atheros Communications, Inc. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _ATH_AH_H_ 21 #define _ATH_AH_H_ 22 /* 23 * Atheros Hardware Access Layer 24 * 25 * Clients of the HAL call ath_hal_attach to obtain a reference to an ath_hal 26 * structure for use with the device. Hardware-related operations that 27 * follow must call back into the HAL through interface, supplying the 28 * reference as the first parameter. 29 */ 30 31 #include "ah_osdep.h" 32 33 /* 34 * Endianness macros; used by various structures and code. 35 */ 36 #define AH_BIG_ENDIAN 4321 37 #define AH_LITTLE_ENDIAN 1234 38 39 #if _BYTE_ORDER == _BIG_ENDIAN 40 #define AH_BYTE_ORDER AH_BIG_ENDIAN 41 #else 42 #define AH_BYTE_ORDER AH_LITTLE_ENDIAN 43 #endif 44 45 /* 46 * The maximum number of TX/RX chains supported. 47 * This is intended to be used by various statistics gathering operations 48 * (NF, RSSI, EVM). 49 */ 50 #define AH_MAX_CHAINS 3 51 #define AH_MIMO_MAX_EVM_PILOTS 6 52 53 /* 54 * __ahdecl is analogous to _cdecl; it defines the calling 55 * convention used within the HAL. For most systems this 56 * can just default to be empty and the compiler will (should) 57 * use _cdecl. For systems where _cdecl is not compatible this 58 * must be defined. See linux/ah_osdep.h for an example. 59 */ 60 #ifndef __ahdecl 61 #define __ahdecl 62 #endif 63 64 /* 65 * Status codes that may be returned by the HAL. Note that 66 * interfaces that return a status code set it only when an 67 * error occurs--i.e. you cannot check it for success. 68 */ 69 typedef enum { 70 HAL_OK = 0, /* No error */ 71 HAL_ENXIO = 1, /* No hardware present */ 72 HAL_ENOMEM = 2, /* Memory allocation failed */ 73 HAL_EIO = 3, /* Hardware didn't respond as expected */ 74 HAL_EEMAGIC = 4, /* EEPROM magic number invalid */ 75 HAL_EEVERSION = 5, /* EEPROM version invalid */ 76 HAL_EELOCKED = 6, /* EEPROM unreadable */ 77 HAL_EEBADSUM = 7, /* EEPROM checksum invalid */ 78 HAL_EEREAD = 8, /* EEPROM read problem */ 79 HAL_EEBADMAC = 9, /* EEPROM mac address invalid */ 80 HAL_EESIZE = 10, /* EEPROM size not supported */ 81 HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */ 82 HAL_EINVAL = 12, /* Invalid parameter to function */ 83 HAL_ENOTSUPP = 13, /* Hardware revision not supported */ 84 HAL_ESELFTEST = 14, /* Hardware self-test failed */ 85 HAL_EINPROGRESS = 15, /* Operation incomplete */ 86 HAL_EEBADREG = 16, /* EEPROM invalid regulatory contents */ 87 HAL_EEBADCC = 17, /* EEPROM invalid country code */ 88 HAL_INV_PMODE = 18, /* Couldn't bring out of sleep state */ 89 } HAL_STATUS; 90 91 typedef enum { 92 AH_FALSE = 0, /* NB: lots of code assumes false is zero */ 93 AH_TRUE = 1, 94 } HAL_BOOL; 95 96 typedef enum { 97 HAL_CAP_REG_DMN = 0, /* current regulatory domain */ 98 HAL_CAP_CIPHER = 1, /* hardware supports cipher */ 99 HAL_CAP_TKIP_MIC = 2, /* handle TKIP MIC in hardware */ 100 HAL_CAP_TKIP_SPLIT = 3, /* hardware TKIP uses split keys */ 101 HAL_CAP_PHYCOUNTERS = 4, /* hardware PHY error counters */ 102 HAL_CAP_DIVERSITY = 5, /* hardware supports fast diversity */ 103 HAL_CAP_KEYCACHE_SIZE = 6, /* number of entries in key cache */ 104 HAL_CAP_NUM_TXQUEUES = 7, /* number of hardware xmit queues */ 105 HAL_CAP_VEOL = 9, /* hardware supports virtual EOL */ 106 HAL_CAP_PSPOLL = 10, /* hardware has working PS-Poll support */ 107 HAL_CAP_DIAG = 11, /* hardware diagnostic support */ 108 HAL_CAP_COMPRESSION = 12, /* hardware supports compression */ 109 HAL_CAP_BURST = 13, /* hardware supports packet bursting */ 110 HAL_CAP_FASTFRAME = 14, /* hardware supoprts fast frames */ 111 HAL_CAP_TXPOW = 15, /* global tx power limit */ 112 HAL_CAP_TPC = 16, /* per-packet tx power control */ 113 HAL_CAP_PHYDIAG = 17, /* hardware phy error diagnostic */ 114 HAL_CAP_BSSIDMASK = 18, /* hardware supports bssid mask */ 115 HAL_CAP_MCAST_KEYSRCH = 19, /* hardware has multicast key search */ 116 HAL_CAP_TSF_ADJUST = 20, /* hardware has beacon tsf adjust */ 117 /* 21 was HAL_CAP_XR */ 118 HAL_CAP_WME_TKIPMIC = 22, /* hardware can support TKIP MIC when WMM is turned on */ 119 /* 23 was HAL_CAP_CHAN_HALFRATE */ 120 /* 24 was HAL_CAP_CHAN_QUARTERRATE */ 121 HAL_CAP_RFSILENT = 25, /* hardware has rfsilent support */ 122 HAL_CAP_TPC_ACK = 26, /* ack txpower with per-packet tpc */ 123 HAL_CAP_TPC_CTS = 27, /* cts txpower with per-packet tpc */ 124 HAL_CAP_11D = 28, /* 11d beacon support for changing cc */ 125 HAL_CAP_PCIE_PS = 29, 126 HAL_CAP_HT = 30, /* hardware can support HT */ 127 HAL_CAP_GTXTO = 31, /* hardware supports global tx timeout */ 128 HAL_CAP_FAST_CC = 32, /* hardware supports fast channel change */ 129 HAL_CAP_TX_CHAINMASK = 33, /* mask of TX chains supported */ 130 HAL_CAP_RX_CHAINMASK = 34, /* mask of RX chains supported */ 131 HAL_CAP_NUM_GPIO_PINS = 36, /* number of GPIO pins */ 132 133 HAL_CAP_CST = 38, /* hardware supports carrier sense timeout */ 134 HAL_CAP_RIFS_RX = 39, 135 HAL_CAP_RIFS_TX = 40, 136 HAL_CAP_FORCE_PPM = 41, 137 HAL_CAP_RTS_AGGR_LIMIT = 42, /* aggregation limit with RTS */ 138 HAL_CAP_4ADDR_AGGR = 43, /* hardware is capable of 4addr aggregation */ 139 HAL_CAP_DFS_DMN = 44, /* current DFS domain */ 140 HAL_CAP_EXT_CHAN_DFS = 45, /* DFS support for extension channel */ 141 HAL_CAP_COMBINED_RADAR_RSSI = 46, /* Is combined RSSI for radar accurate */ 142 143 HAL_CAP_AUTO_SLEEP = 48, /* hardware can go to network sleep 144 automatically after waking up to receive TIM */ 145 HAL_CAP_MBSSID_AGGR_SUPPORT = 49, /* Support for mBSSID Aggregation */ 146 HAL_CAP_SPLIT_4KB_TRANS = 50, /* hardware supports descriptors straddling a 4k page boundary */ 147 HAL_CAP_REG_FLAG = 51, /* Regulatory domain flags */ 148 HAL_CAP_BB_RIFS_HANG = 52, 149 HAL_CAP_RIFS_RX_ENABLED = 53, 150 HAL_CAP_BB_DFS_HANG = 54, 151 152 HAL_CAP_RX_STBC = 58, 153 HAL_CAP_TX_STBC = 59, 154 155 HAL_CAP_BT_COEX = 60, /* hardware is capable of bluetooth coexistence */ 156 HAL_CAP_DYNAMIC_SMPS = 61, /* Dynamic MIMO Power Save hardware support */ 157 158 HAL_CAP_DS = 67, /* 2 stream */ 159 HAL_CAP_BB_RX_CLEAR_STUCK_HANG = 68, 160 HAL_CAP_MAC_HANG = 69, /* can MAC hang */ 161 HAL_CAP_MFP = 70, /* Management Frame Protection in hardware */ 162 163 HAL_CAP_TS = 72, /* 3 stream */ 164 165 HAL_CAP_ENHANCED_DMA_SUPPORT = 75, /* DMA FIFO support */ 166 HAL_CAP_NUM_TXMAPS = 76, /* Number of buffers in a transmit descriptor */ 167 HAL_CAP_TXDESCLEN = 77, /* Length of transmit descriptor */ 168 HAL_CAP_TXSTATUSLEN = 78, /* Length of transmit status descriptor */ 169 HAL_CAP_RXSTATUSLEN = 79, /* Length of transmit status descriptor */ 170 HAL_CAP_RXFIFODEPTH = 80, /* Receive hardware FIFO depth */ 171 HAL_CAP_RXBUFSIZE = 81, /* Receive Buffer Length */ 172 HAL_CAP_NUM_MR_RETRIES = 82, /* limit on multirate retries */ 173 HAL_CAP_OL_PWRCTRL = 84, /* Open loop TX power control */ 174 HAL_CAP_SPECTRAL_SCAN = 90, /* Hardware supports spectral scan */ 175 176 HAL_CAP_BB_PANIC_WATCHDOG = 92, 177 178 HAL_CAP_HT20_SGI = 96, /* hardware supports HT20 short GI */ 179 180 HAL_CAP_LDPC = 99, 181 182 HAL_CAP_RXTSTAMP_PREC = 100, /* rx desc tstamp precision (bits) */ 183 184 HAL_CAP_ANT_DIV_COMB = 105, /* Enable antenna diversity/combining */ 185 HAL_CAP_PHYRESTART_CLR_WAR = 106, /* in some cases, clear phy restart to fix bb hang */ 186 HAL_CAP_ENTERPRISE_MODE = 107, /* Enterprise mode features */ 187 HAL_CAP_LDPCWAR = 108, 188 HAL_CAP_CHANNEL_SWITCH_TIME_USEC = 109, /* Channel change time, usec */ 189 HAL_CAP_ENABLE_APM = 110, /* APM enabled */ 190 HAL_CAP_PCIE_LCR_EXTSYNC_EN = 111, 191 HAL_CAP_PCIE_LCR_OFFSET = 112, 192 193 HAL_CAP_ENHANCED_DFS_SUPPORT = 117, /* hardware supports enhanced DFS */ 194 HAL_CAP_MCI = 118, 195 HAL_CAP_SMARTANTENNA = 119, 196 HAL_CAP_TRAFFIC_FAST_RECOVER = 120, 197 HAL_CAP_TX_DIVERSITY = 121, 198 HAL_CAP_CRDC = 122, 199 200 /* The following are private to the FreeBSD HAL (224 onward) */ 201 202 HAL_CAP_INTMIT = 229, /* interference mitigation */ 203 HAL_CAP_RXORN_FATAL = 230, /* HAL_INT_RXORN treated as fatal */ 204 HAL_CAP_BB_HANG = 235, /* can baseband hang */ 205 HAL_CAP_INTRMASK = 237, /* bitmask of supported interrupts */ 206 HAL_CAP_BSSIDMATCH = 238, /* hardware has disable bssid match */ 207 HAL_CAP_STREAMS = 239, /* how many 802.11n spatial streams are available */ 208 HAL_CAP_RXDESC_SELFLINK = 242, /* support a self-linked tail RX descriptor */ 209 HAL_CAP_BB_READ_WAR = 244, /* baseband read WAR */ 210 HAL_CAP_SERIALISE_WAR = 245, /* serialise register access on PCI */ 211 HAL_CAP_ENFORCE_TXOP = 246, /* Enforce TXOP if supported */ 212 HAL_CAP_RX_LNA_MIXING = 247, /* RX hardware uses LNA mixing */ 213 HAL_CAP_DO_MYBEACON = 248, /* Supports HAL_RX_FILTER_MYBEACON */ 214 HAL_CAP_TOA_LOCATIONING = 249, /* time of flight / arrival locationing */ 215 HAL_CAP_TXTSTAMP_PREC = 250, /* tx desc tstamp precision (bits) */ 216 } HAL_CAPABILITY_TYPE; 217 218 /* 219 * "States" for setting the LED. These correspond to 220 * the possible 802.11 operational states and there may 221 * be a many-to-one mapping between these states and the 222 * actual hardware state for the LED's (i.e. the hardware 223 * may have fewer states). 224 */ 225 typedef enum { 226 HAL_LED_INIT = 0, 227 HAL_LED_SCAN = 1, 228 HAL_LED_AUTH = 2, 229 HAL_LED_ASSOC = 3, 230 HAL_LED_RUN = 4 231 } HAL_LED_STATE; 232 233 /* 234 * Transmit queue types/numbers. These are used to tag 235 * each transmit queue in the hardware and to identify a set 236 * of transmit queues for operations such as start/stop dma. 237 */ 238 typedef enum { 239 HAL_TX_QUEUE_INACTIVE = 0, /* queue is inactive/unused */ 240 HAL_TX_QUEUE_DATA = 1, /* data xmit q's */ 241 HAL_TX_QUEUE_BEACON = 2, /* beacon xmit q */ 242 HAL_TX_QUEUE_CAB = 3, /* "crap after beacon" xmit q */ 243 HAL_TX_QUEUE_UAPSD = 4, /* u-apsd power save xmit q */ 244 HAL_TX_QUEUE_PSPOLL = 5, /* power save poll xmit q */ 245 HAL_TX_QUEUE_CFEND = 6, 246 HAL_TX_QUEUE_PAPRD = 7, 247 } HAL_TX_QUEUE; 248 249 #define HAL_NUM_TX_QUEUES 10 /* max possible # of queues */ 250 251 /* 252 * Receive queue types. These are used to tag 253 * each transmit queue in the hardware and to identify a set 254 * of transmit queues for operations such as start/stop dma. 255 */ 256 typedef enum { 257 HAL_RX_QUEUE_HP = 0, /* high priority recv queue */ 258 HAL_RX_QUEUE_LP = 1, /* low priority recv queue */ 259 } HAL_RX_QUEUE; 260 261 #define HAL_NUM_RX_QUEUES 2 /* max possible # of queues */ 262 263 #define HAL_TXFIFO_DEPTH 8 /* transmit fifo depth */ 264 265 /* 266 * Transmit queue subtype. These map directly to 267 * WME Access Categories (except for UPSD). Refer 268 * to Table 5 of the WME spec. 269 */ 270 typedef enum { 271 HAL_WME_AC_BK = 0, /* background access category */ 272 HAL_WME_AC_BE = 1, /* best effort access category*/ 273 HAL_WME_AC_VI = 2, /* video access category */ 274 HAL_WME_AC_VO = 3, /* voice access category */ 275 HAL_WME_UPSD = 4, /* uplink power save */ 276 } HAL_TX_QUEUE_SUBTYPE; 277 278 /* 279 * Transmit queue flags that control various 280 * operational parameters. 281 */ 282 typedef enum { 283 /* 284 * Per queue interrupt enables. When set the associated 285 * interrupt may be delivered for packets sent through 286 * the queue. Without these enabled no interrupts will 287 * be delivered for transmits through the queue. 288 */ 289 HAL_TXQ_TXOKINT_ENABLE = 0x0001, /* enable TXOK interrupt */ 290 HAL_TXQ_TXERRINT_ENABLE = 0x0001, /* enable TXERR interrupt */ 291 HAL_TXQ_TXDESCINT_ENABLE = 0x0002, /* enable TXDESC interrupt */ 292 HAL_TXQ_TXEOLINT_ENABLE = 0x0004, /* enable TXEOL interrupt */ 293 HAL_TXQ_TXURNINT_ENABLE = 0x0008, /* enable TXURN interrupt */ 294 /* 295 * Enable hardware compression for packets sent through 296 * the queue. The compression buffer must be setup and 297 * packets must have a key entry marked in the tx descriptor. 298 */ 299 HAL_TXQ_COMPRESSION_ENABLE = 0x0010, /* enable h/w compression */ 300 /* 301 * Disable queue when veol is hit or ready time expires. 302 * By default the queue is disabled only on reaching the 303 * physical end of queue (i.e. a null link ptr in the 304 * descriptor chain). 305 */ 306 HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE = 0x0020, 307 /* 308 * Schedule frames on delivery of a DBA (DMA Beacon Alert) 309 * event. Frames will be transmitted only when this timer 310 * fires, e.g to transmit a beacon in ap or adhoc modes. 311 */ 312 HAL_TXQ_DBA_GATED = 0x0040, /* schedule based on DBA */ 313 /* 314 * Each transmit queue has a counter that is incremented 315 * each time the queue is enabled and decremented when 316 * the list of frames to transmit is traversed (or when 317 * the ready time for the queue expires). This counter 318 * must be non-zero for frames to be scheduled for 319 * transmission. The following controls disable bumping 320 * this counter under certain conditions. Typically this 321 * is used to gate frames based on the contents of another 322 * queue (e.g. CAB traffic may only follow a beacon frame). 323 * These are meaningful only when frames are scheduled 324 * with a non-ASAP policy (e.g. DBA-gated). 325 */ 326 HAL_TXQ_CBR_DIS_QEMPTY = 0x0080, /* disable on this q empty */ 327 HAL_TXQ_CBR_DIS_BEMPTY = 0x0100, /* disable on beacon q empty */ 328 329 /* 330 * Fragment burst backoff policy. Normally the no backoff 331 * is done after a successful transmission, the next fragment 332 * is sent at SIFS. If this flag is set backoff is done 333 * after each fragment, regardless whether it was ack'd or 334 * not, after the backoff count reaches zero a normal channel 335 * access procedure is done before the next transmit (i.e. 336 * wait AIFS instead of SIFS). 337 */ 338 HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE = 0x00800000, 339 /* 340 * Disable post-tx backoff following each frame. 341 */ 342 HAL_TXQ_BACKOFF_DISABLE = 0x00010000, /* disable post backoff */ 343 /* 344 * DCU arbiter lockout control. This controls how 345 * lower priority tx queues are handled with respect to 346 * to a specific queue when multiple queues have frames 347 * to send. No lockout means lower priority queues arbitrate 348 * concurrently with this queue. Intra-frame lockout 349 * means lower priority queues are locked out until the 350 * current frame transmits (e.g. including backoffs and bursting). 351 * Global lockout means nothing lower can arbitrary so 352 * long as there is traffic activity on this queue (frames, 353 * backoff, etc). 354 */ 355 HAL_TXQ_ARB_LOCKOUT_INTRA = 0x00020000, /* intra-frame lockout */ 356 HAL_TXQ_ARB_LOCKOUT_GLOBAL = 0x00040000, /* full lockout s */ 357 358 HAL_TXQ_IGNORE_VIRTCOL = 0x00080000, /* ignore virt collisions */ 359 HAL_TXQ_SEQNUM_INC_DIS = 0x00100000, /* disable seqnum increment */ 360 } HAL_TX_QUEUE_FLAGS; 361 362 typedef struct { 363 uint32_t tqi_ver; /* hal TXQ version */ 364 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* subtype if applicable */ 365 HAL_TX_QUEUE_FLAGS tqi_qflags; /* flags (see above) */ 366 uint32_t tqi_priority; /* (not used) */ 367 uint32_t tqi_aifs; /* aifs */ 368 uint32_t tqi_cwmin; /* cwMin */ 369 uint32_t tqi_cwmax; /* cwMax */ 370 uint16_t tqi_shretry; /* rts retry limit */ 371 uint16_t tqi_lgretry; /* long retry limit (not used)*/ 372 uint32_t tqi_cbrPeriod; /* CBR period (us) */ 373 uint32_t tqi_cbrOverflowLimit; /* threshold for CBROVF int */ 374 uint32_t tqi_burstTime; /* max burst duration (us) */ 375 uint32_t tqi_readyTime; /* frame schedule time (us) */ 376 uint32_t tqi_compBuf; /* comp buffer phys addr */ 377 } HAL_TXQ_INFO; 378 379 #define HAL_TQI_NONVAL 0xffff 380 381 /* token to use for aifs, cwmin, cwmax */ 382 #define HAL_TXQ_USEDEFAULT ((uint32_t) -1) 383 384 /* compression definitions */ 385 #define HAL_COMP_BUF_MAX_SIZE 9216 /* 9K */ 386 #define HAL_COMP_BUF_ALIGN_SIZE 512 387 388 /* 389 * Transmit packet types. This belongs in ah_desc.h, but 390 * is here so we can give a proper type to various parameters 391 * (and not require everyone include the file). 392 * 393 * NB: These values are intentionally assigned for 394 * direct use when setting up h/w descriptors. 395 */ 396 typedef enum { 397 HAL_PKT_TYPE_NORMAL = 0, 398 HAL_PKT_TYPE_ATIM = 1, 399 HAL_PKT_TYPE_PSPOLL = 2, 400 HAL_PKT_TYPE_BEACON = 3, 401 HAL_PKT_TYPE_PROBE_RESP = 4, 402 HAL_PKT_TYPE_CHIRP = 5, 403 HAL_PKT_TYPE_GRP_POLL = 6, 404 HAL_PKT_TYPE_AMPDU = 7, 405 } HAL_PKT_TYPE; 406 407 /* Rx Filter Frame Types */ 408 typedef enum { 409 /* 410 * These bits correspond to AR_RX_FILTER for all chips. 411 * Not all bits are supported by all chips. 412 */ 413 HAL_RX_FILTER_UCAST = 0x00000001, /* Allow unicast frames */ 414 HAL_RX_FILTER_MCAST = 0x00000002, /* Allow multicast frames */ 415 HAL_RX_FILTER_BCAST = 0x00000004, /* Allow broadcast frames */ 416 HAL_RX_FILTER_CONTROL = 0x00000008, /* Allow control frames */ 417 HAL_RX_FILTER_BEACON = 0x00000010, /* Allow beacon frames */ 418 HAL_RX_FILTER_PROM = 0x00000020, /* Promiscuous mode */ 419 HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */ 420 HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */ 421 HAL_RX_FILTER_MYBEACON = 0x00000200, /* Filter beacons other than mine */ 422 HAL_RX_FILTER_COMPBAR = 0x00000400, /* Allow compressed BAR */ 423 HAL_RX_FILTER_COMP_BA = 0x00000800, /* Allow compressed blockack */ 424 HAL_RX_FILTER_PHYRADAR = 0x00002000, /* Allow phy radar errors */ 425 HAL_RX_FILTER_PSPOLL = 0x00004000, /* Allow PS-POLL frames */ 426 HAL_RX_FILTER_MCAST_BCAST_ALL = 0x00008000, 427 /* Allow all mcast/bcast frames */ 428 429 /* 430 * Magic RX filter flags that aren't targeting hardware bits 431 * but instead the HAL sets individual bits - eg PHYERR will result 432 * in OFDM/CCK timing error frames being received. 433 */ 434 HAL_RX_FILTER_BSSID = 0x40000000, /* Disable BSSID match */ 435 } HAL_RX_FILTER; 436 437 typedef enum { 438 HAL_PM_AWAKE = 0, 439 HAL_PM_FULL_SLEEP = 1, 440 HAL_PM_NETWORK_SLEEP = 2, 441 HAL_PM_UNDEFINED = 3 442 } HAL_POWER_MODE; 443 444 /* 445 * Enterprise mode flags 446 */ 447 #define AH_ENT_DUAL_BAND_DISABLE 0x00000001 448 #define AH_ENT_CHAIN2_DISABLE 0x00000002 449 #define AH_ENT_5MHZ_DISABLE 0x00000004 450 #define AH_ENT_10MHZ_DISABLE 0x00000008 451 #define AH_ENT_49GHZ_DISABLE 0x00000010 452 #define AH_ENT_LOOPBACK_DISABLE 0x00000020 453 #define AH_ENT_TPC_PERF_DISABLE 0x00000040 454 #define AH_ENT_MIN_PKT_SIZE_DISABLE 0x00000080 455 #define AH_ENT_SPECTRAL_PRECISION 0x00000300 456 #define AH_ENT_SPECTRAL_PRECISION_S 8 457 #define AH_ENT_RTSCTS_DELIM_WAR 0x00010000 458 459 #define AH_FIRST_DESC_NDELIMS 60 460 461 /* 462 * NOTE WELL: 463 * These are mapped to take advantage of the common locations for many of 464 * the bits on all of the currently supported MAC chips. This is to make 465 * the ISR as efficient as possible, while still abstracting HW differences. 466 * When new hardware breaks this commonality this enumerated type, as well 467 * as the HAL functions using it, must be modified. All values are directly 468 * mapped unless commented otherwise. 469 */ 470 typedef enum { 471 HAL_INT_RX = 0x00000001, /* Non-common mapping */ 472 HAL_INT_RXDESC = 0x00000002, /* Legacy mapping */ 473 HAL_INT_RXERR = 0x00000004, 474 HAL_INT_RXHP = 0x00000001, /* EDMA */ 475 HAL_INT_RXLP = 0x00000002, /* EDMA */ 476 HAL_INT_RXNOFRM = 0x00000008, 477 HAL_INT_RXEOL = 0x00000010, 478 HAL_INT_RXORN = 0x00000020, 479 HAL_INT_TX = 0x00000040, /* Non-common mapping */ 480 HAL_INT_TXDESC = 0x00000080, 481 HAL_INT_TIM_TIMER= 0x00000100, 482 HAL_INT_MCI = 0x00000200, 483 HAL_INT_BBPANIC = 0x00000400, 484 HAL_INT_TXURN = 0x00000800, 485 HAL_INT_MIB = 0x00001000, 486 HAL_INT_RXPHY = 0x00004000, 487 HAL_INT_RXKCM = 0x00008000, 488 HAL_INT_SWBA = 0x00010000, 489 HAL_INT_BRSSI = 0x00020000, 490 HAL_INT_BMISS = 0x00040000, 491 HAL_INT_BNR = 0x00100000, 492 HAL_INT_TIM = 0x00200000, /* Non-common mapping */ 493 HAL_INT_DTIM = 0x00400000, /* Non-common mapping */ 494 HAL_INT_DTIMSYNC= 0x00800000, /* Non-common mapping */ 495 HAL_INT_GPIO = 0x01000000, 496 HAL_INT_CABEND = 0x02000000, /* Non-common mapping */ 497 HAL_INT_TSFOOR = 0x04000000, /* Non-common mapping */ 498 HAL_INT_TBTT = 0x08000000, /* Non-common mapping */ 499 /* Atheros ref driver has a generic timer interrupt now..*/ 500 HAL_INT_GENTIMER = 0x08000000, /* Non-common mapping */ 501 HAL_INT_CST = 0x10000000, /* Non-common mapping */ 502 HAL_INT_GTT = 0x20000000, /* Non-common mapping */ 503 HAL_INT_FATAL = 0x40000000, /* Non-common mapping */ 504 #define HAL_INT_GLOBAL 0x80000000 /* Set/clear IER */ 505 HAL_INT_BMISC = HAL_INT_TIM 506 | HAL_INT_DTIM 507 | HAL_INT_DTIMSYNC 508 | HAL_INT_CABEND 509 | HAL_INT_TBTT, 510 511 /* Interrupt bits that map directly to ISR/IMR bits */ 512 HAL_INT_COMMON = HAL_INT_RXNOFRM 513 | HAL_INT_RXDESC 514 | HAL_INT_RXEOL 515 | HAL_INT_RXORN 516 | HAL_INT_TXDESC 517 | HAL_INT_TXURN 518 | HAL_INT_MIB 519 | HAL_INT_RXPHY 520 | HAL_INT_RXKCM 521 | HAL_INT_SWBA 522 | HAL_INT_BMISS 523 | HAL_INT_BRSSI 524 | HAL_INT_BNR 525 | HAL_INT_GPIO, 526 } HAL_INT; 527 528 /* 529 * MSI vector assignments 530 */ 531 typedef enum { 532 HAL_MSIVEC_MISC = 0, 533 HAL_MSIVEC_TX = 1, 534 HAL_MSIVEC_RXLP = 2, 535 HAL_MSIVEC_RXHP = 3, 536 } HAL_MSIVEC; 537 538 typedef enum { 539 HAL_INT_LINE = 0, 540 HAL_INT_MSI = 1, 541 } HAL_INT_TYPE; 542 543 /* For interrupt mitigation registers */ 544 typedef enum { 545 HAL_INT_RX_FIRSTPKT=0, 546 HAL_INT_RX_LASTPKT, 547 HAL_INT_TX_FIRSTPKT, 548 HAL_INT_TX_LASTPKT, 549 HAL_INT_THRESHOLD 550 } HAL_INT_MITIGATION; 551 552 /* XXX this is duplicate information! */ 553 typedef struct { 554 u_int32_t cyclecnt_diff; /* delta cycle count */ 555 u_int32_t rxclr_cnt; /* rx clear count */ 556 u_int32_t extrxclr_cnt; /* ext chan rx clear count */ 557 u_int32_t txframecnt_diff; /* delta tx frame count */ 558 u_int32_t rxframecnt_diff; /* delta rx frame count */ 559 u_int32_t listen_time; /* listen time in msec - time for which ch is free */ 560 u_int32_t ofdmphyerr_cnt; /* OFDM err count since last reset */ 561 u_int32_t cckphyerr_cnt; /* CCK err count since last reset */ 562 u_int32_t ofdmphyerrcnt_diff; /* delta OFDM Phy Error Count */ 563 HAL_BOOL valid; /* if the stats are valid*/ 564 } HAL_ANISTATS; 565 566 typedef struct { 567 u_int8_t txctl_offset; 568 u_int8_t txctl_numwords; 569 u_int8_t txstatus_offset; 570 u_int8_t txstatus_numwords; 571 572 u_int8_t rxctl_offset; 573 u_int8_t rxctl_numwords; 574 u_int8_t rxstatus_offset; 575 u_int8_t rxstatus_numwords; 576 577 u_int8_t macRevision; 578 } HAL_DESC_INFO; 579 580 typedef enum { 581 HAL_GPIO_OUTPUT_MUX_AS_OUTPUT = 0, 582 HAL_GPIO_OUTPUT_MUX_PCIE_ATTENTION_LED = 1, 583 HAL_GPIO_OUTPUT_MUX_PCIE_POWER_LED = 2, 584 HAL_GPIO_OUTPUT_MUX_MAC_NETWORK_LED = 3, 585 HAL_GPIO_OUTPUT_MUX_MAC_POWER_LED = 4, 586 HAL_GPIO_OUTPUT_MUX_AS_WLAN_ACTIVE = 5, 587 HAL_GPIO_OUTPUT_MUX_AS_TX_FRAME = 6, 588 589 HAL_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA, 590 HAL_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK, 591 HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA, 592 HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK, 593 HAL_GPIO_OUTPUT_MUX_AS_WL_IN_TX, 594 HAL_GPIO_OUTPUT_MUX_AS_WL_IN_RX, 595 HAL_GPIO_OUTPUT_MUX_AS_BT_IN_TX, 596 HAL_GPIO_OUTPUT_MUX_AS_BT_IN_RX, 597 HAL_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE, 598 HAL_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA, 599 HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL0, 600 HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL1, 601 HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL2, 602 HAL_GPIO_OUTPUT_MUX_NUM_ENTRIES 603 } HAL_GPIO_MUX_TYPE; 604 605 typedef enum { 606 HAL_GPIO_INTR_LOW = 0, 607 HAL_GPIO_INTR_HIGH = 1, 608 HAL_GPIO_INTR_DISABLE = 2 609 } HAL_GPIO_INTR_TYPE; 610 611 typedef struct halCounters { 612 u_int32_t tx_frame_count; 613 u_int32_t rx_frame_count; 614 u_int32_t rx_clear_count; 615 u_int32_t cycle_count; 616 u_int8_t is_rx_active; // true (1) or false (0) 617 u_int8_t is_tx_active; // true (1) or false (0) 618 } HAL_COUNTERS; 619 620 typedef enum { 621 HAL_RFGAIN_INACTIVE = 0, 622 HAL_RFGAIN_READ_REQUESTED = 1, 623 HAL_RFGAIN_NEED_CHANGE = 2 624 } HAL_RFGAIN; 625 626 typedef uint16_t HAL_CTRY_CODE; /* country code */ 627 typedef uint16_t HAL_REG_DOMAIN; /* regulatory domain code */ 628 629 #define HAL_ANTENNA_MIN_MODE 0 630 #define HAL_ANTENNA_FIXED_A 1 631 #define HAL_ANTENNA_FIXED_B 2 632 #define HAL_ANTENNA_MAX_MODE 3 633 634 typedef struct { 635 uint32_t ackrcv_bad; 636 uint32_t rts_bad; 637 uint32_t rts_good; 638 uint32_t fcs_bad; 639 uint32_t beacons; 640 } HAL_MIB_STATS; 641 642 /* 643 * These bits represent what's in ah_currentRDext. 644 */ 645 typedef enum { 646 REG_EXT_FCC_MIDBAND = 0, 647 REG_EXT_JAPAN_MIDBAND = 1, 648 REG_EXT_FCC_DFS_HT40 = 2, 649 REG_EXT_JAPAN_NONDFS_HT40 = 3, 650 REG_EXT_JAPAN_DFS_HT40 = 4, 651 REG_EXT_FCC_CH_144 = 5, 652 } REG_EXT_BITMAP; 653 654 enum { 655 HAL_MODE_11A = 0x001, /* 11a channels */ 656 HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */ 657 HAL_MODE_11B = 0x004, /* 11b channels */ 658 HAL_MODE_PUREG = 0x008, /* 11g channels (OFDM only) */ 659 #ifdef notdef 660 HAL_MODE_11G = 0x010, /* 11g channels (OFDM/CCK) */ 661 #else 662 HAL_MODE_11G = 0x008, /* XXX historical */ 663 #endif 664 HAL_MODE_108G = 0x020, /* 11g+Turbo channels */ 665 HAL_MODE_108A = 0x040, /* 11a+Turbo channels */ 666 HAL_MODE_11A_HALF_RATE = 0x200, /* 11a half width channels */ 667 HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11a quarter width channels */ 668 HAL_MODE_11G_HALF_RATE = 0x800, /* 11g half width channels */ 669 HAL_MODE_11G_QUARTER_RATE = 0x1000, /* 11g quarter width channels */ 670 HAL_MODE_11NG_HT20 = 0x008000, 671 HAL_MODE_11NA_HT20 = 0x010000, 672 HAL_MODE_11NG_HT40PLUS = 0x020000, 673 HAL_MODE_11NG_HT40MINUS = 0x040000, 674 HAL_MODE_11NA_HT40PLUS = 0x080000, 675 HAL_MODE_11NA_HT40MINUS = 0x100000, 676 HAL_MODE_ALL = 0xffffff 677 }; 678 679 typedef struct { 680 int rateCount; /* NB: for proper padding */ 681 uint8_t rateCodeToIndex[256]; /* back mapping */ 682 struct { 683 uint8_t valid; /* valid for rate control use */ 684 uint8_t phy; /* CCK/OFDM/XR */ 685 uint32_t rateKbps; /* transfer rate in kbs */ 686 uint8_t rateCode; /* rate for h/w descriptors */ 687 uint8_t shortPreamble; /* mask for enabling short 688 * preamble in CCK rate code */ 689 uint8_t dot11Rate; /* value for supported rates 690 * info element of MLME */ 691 uint8_t controlRate; /* index of next lower basic 692 * rate; used for dur. calcs */ 693 uint16_t lpAckDuration; /* long preamble ACK duration */ 694 uint16_t spAckDuration; /* short preamble ACK duration*/ 695 } info[64]; 696 } HAL_RATE_TABLE; 697 698 typedef struct { 699 u_int rs_count; /* number of valid entries */ 700 uint8_t rs_rates[64]; /* rates */ 701 } HAL_RATE_SET; 702 703 /* 704 * 802.11n specific structures and enums 705 */ 706 typedef enum { 707 HAL_CHAINTYPE_TX = 1, /* Tx chain type */ 708 HAL_CHAINTYPE_RX = 2, /* RX chain type */ 709 } HAL_CHAIN_TYPE; 710 711 typedef struct { 712 u_int Tries; 713 u_int Rate; /* hardware rate code */ 714 u_int RateIndex; /* rate series table index */ 715 u_int PktDuration; 716 u_int ChSel; 717 u_int RateFlags; 718 #define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */ 719 #define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */ 720 #define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */ 721 #define HAL_RATESERIES_STBC 0x0008 /* use STBC for series */ 722 u_int tx_power_cap; /* in 1/2 dBm units XXX TODO */ 723 } HAL_11N_RATE_SERIES; 724 725 typedef enum { 726 HAL_HT_MACMODE_20 = 0, /* 20 MHz operation */ 727 HAL_HT_MACMODE_2040 = 1, /* 20/40 MHz operation */ 728 } HAL_HT_MACMODE; 729 730 typedef enum { 731 HAL_HT_PHYMODE_20 = 0, /* 20 MHz operation */ 732 HAL_HT_PHYMODE_2040 = 1, /* 20/40 MHz operation */ 733 } HAL_HT_PHYMODE; 734 735 typedef enum { 736 HAL_HT_EXTPROTSPACING_20 = 0, /* 20 MHz spacing */ 737 HAL_HT_EXTPROTSPACING_25 = 1, /* 25 MHz spacing */ 738 } HAL_HT_EXTPROTSPACING; 739 740 typedef enum { 741 HAL_RX_CLEAR_CTL_LOW = 0x1, /* force control channel to appear busy */ 742 HAL_RX_CLEAR_EXT_LOW = 0x2, /* force extension channel to appear busy */ 743 } HAL_HT_RXCLEAR; 744 745 typedef enum { 746 HAL_FREQ_BAND_5GHZ = 0, 747 HAL_FREQ_BAND_2GHZ = 1, 748 } HAL_FREQ_BAND; 749 750 /* 751 * Antenna switch control. By default antenna selection 752 * enables multiple (2) antenna use. To force use of the 753 * A or B antenna only specify a fixed setting. Fixing 754 * the antenna will also disable any diversity support. 755 */ 756 typedef enum { 757 HAL_ANT_VARIABLE = 0, /* variable by programming */ 758 HAL_ANT_FIXED_A = 1, /* fixed antenna A */ 759 HAL_ANT_FIXED_B = 2, /* fixed antenna B */ 760 } HAL_ANT_SETTING; 761 762 typedef enum { 763 HAL_M_STA = 1, /* infrastructure station */ 764 HAL_M_IBSS = 0, /* IBSS (adhoc) station */ 765 HAL_M_HOSTAP = 6, /* Software Access Point */ 766 HAL_M_MONITOR = 8 /* Monitor mode */ 767 } HAL_OPMODE; 768 769 typedef enum { 770 HAL_RESET_NORMAL = 0, /* Do normal reset */ 771 HAL_RESET_BBPANIC = 1, /* Reset because of BB panic */ 772 HAL_RESET_FORCE_COLD = 2, /* Force full reset */ 773 } HAL_RESET_TYPE; 774 775 enum { 776 HAL_RESET_POWER_ON, 777 HAL_RESET_WARM, 778 HAL_RESET_COLD 779 }; 780 781 typedef struct { 782 uint8_t kv_type; /* one of HAL_CIPHER */ 783 uint8_t kv_apsd; /* Mask for APSD enabled ACs */ 784 uint16_t kv_len; /* length in bits */ 785 uint8_t kv_val[16]; /* enough for 128-bit keys */ 786 uint8_t kv_mic[8]; /* TKIP MIC key */ 787 uint8_t kv_txmic[8]; /* TKIP TX MIC key (optional) */ 788 } HAL_KEYVAL; 789 790 /* 791 * This is the TX descriptor field which marks the key padding requirement. 792 * The naming is unfortunately unclear. 793 */ 794 #define AH_KEYTYPE_MASK 0x0F 795 typedef enum { 796 HAL_KEY_TYPE_CLEAR, 797 HAL_KEY_TYPE_WEP, 798 HAL_KEY_TYPE_AES, 799 HAL_KEY_TYPE_TKIP, 800 } HAL_KEY_TYPE; 801 802 typedef enum { 803 HAL_CIPHER_WEP = 0, 804 HAL_CIPHER_AES_OCB = 1, 805 HAL_CIPHER_AES_CCM = 2, 806 HAL_CIPHER_CKIP = 3, 807 HAL_CIPHER_TKIP = 4, 808 HAL_CIPHER_CLR = 5, /* no encryption */ 809 810 HAL_CIPHER_MIC = 127 /* TKIP-MIC, not a cipher */ 811 } HAL_CIPHER; 812 813 enum { 814 HAL_SLOT_TIME_6 = 6, /* NB: for turbo mode */ 815 HAL_SLOT_TIME_9 = 9, 816 HAL_SLOT_TIME_20 = 20, 817 }; 818 819 /* 820 * Per-station beacon timer state. Note that the specified 821 * beacon interval (given in TU's) can also include flags 822 * to force a TSF reset and to enable the beacon xmit logic. 823 * If bs_cfpmaxduration is non-zero the hardware is setup to 824 * coexist with a PCF-capable AP. 825 */ 826 typedef struct { 827 uint32_t bs_nexttbtt; /* next beacon in TU */ 828 uint32_t bs_nextdtim; /* next DTIM in TU */ 829 uint32_t bs_intval; /* beacon interval+flags */ 830 /* 831 * HAL_BEACON_PERIOD, HAL_BEACON_ENA and HAL_BEACON_RESET_TSF 832 * are all 1:1 correspondances with the pre-11n chip AR_BEACON 833 * register. 834 */ 835 #define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */ 836 #define HAL_BEACON_PERIOD_TU8 0x0007ffff /* beacon interval, tu/8 */ 837 #define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */ 838 #define HAL_BEACON_RESET_TSF 0x01000000 /* clear TSF */ 839 #define HAL_TSFOOR_THRESHOLD 0x00004240 /* TSF OOR thresh (16k uS) */ 840 uint32_t bs_dtimperiod; 841 uint16_t bs_cfpperiod; /* CFP period in TU */ 842 uint16_t bs_cfpmaxduration; /* max CFP duration in TU */ 843 uint32_t bs_cfpnext; /* next CFP in TU */ 844 uint16_t bs_timoffset; /* byte offset to TIM bitmap */ 845 uint16_t bs_bmissthreshold; /* beacon miss threshold */ 846 uint32_t bs_sleepduration; /* max sleep duration */ 847 uint32_t bs_tsfoor_threshold; /* TSF out of range threshold */ 848 } HAL_BEACON_STATE; 849 850 /* 851 * Like HAL_BEACON_STATE but for non-station mode setup. 852 * NB: see above flag definitions for bt_intval. 853 */ 854 typedef struct { 855 uint32_t bt_intval; /* beacon interval+flags */ 856 uint32_t bt_nexttbtt; /* next beacon in TU */ 857 uint32_t bt_nextatim; /* next ATIM in TU */ 858 uint32_t bt_nextdba; /* next DBA in 1/8th TU */ 859 uint32_t bt_nextswba; /* next SWBA in 1/8th TU */ 860 uint32_t bt_flags; /* timer enables */ 861 #define HAL_BEACON_TBTT_EN 0x00000001 862 #define HAL_BEACON_DBA_EN 0x00000002 863 #define HAL_BEACON_SWBA_EN 0x00000004 864 } HAL_BEACON_TIMERS; 865 866 /* 867 * Per-node statistics maintained by the driver for use in 868 * optimizing signal quality and other operational aspects. 869 */ 870 typedef struct { 871 uint32_t ns_avgbrssi; /* average beacon rssi */ 872 uint32_t ns_avgrssi; /* average data rssi */ 873 uint32_t ns_avgtxrssi; /* average tx rssi */ 874 } HAL_NODE_STATS; 875 876 #define HAL_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */ 877 878 /* 879 * This is the ANI state and MIB stats. 880 * 881 * It's used by the HAL modules to keep state /and/ by the debug ioctl 882 * to fetch ANI information. 883 */ 884 typedef struct { 885 uint32_t ast_ani_niup; /* ANI increased noise immunity */ 886 uint32_t ast_ani_nidown; /* ANI decreased noise immunity */ 887 uint32_t ast_ani_spurup; /* ANI increased spur immunity */ 888 uint32_t ast_ani_spurdown;/* ANI descreased spur immunity */ 889 uint32_t ast_ani_ofdmon; /* ANI OFDM weak signal detect on */ 890 uint32_t ast_ani_ofdmoff;/* ANI OFDM weak signal detect off */ 891 uint32_t ast_ani_cckhigh;/* ANI CCK weak signal threshold high */ 892 uint32_t ast_ani_ccklow; /* ANI CCK weak signal threshold low */ 893 uint32_t ast_ani_stepup; /* ANI increased first step level */ 894 uint32_t ast_ani_stepdown;/* ANI decreased first step level */ 895 uint32_t ast_ani_ofdmerrs;/* ANI cumulative ofdm phy err count */ 896 uint32_t ast_ani_cckerrs;/* ANI cumulative cck phy err count */ 897 uint32_t ast_ani_reset; /* ANI parameters zero'd for non-STA */ 898 uint32_t ast_ani_lzero; /* ANI listen time forced to zero */ 899 uint32_t ast_ani_lneg; /* ANI listen time calculated < 0 */ 900 HAL_MIB_STATS ast_mibstats; /* MIB counter stats */ 901 HAL_NODE_STATS ast_nodestats; /* Latest rssi stats from driver */ 902 } HAL_ANI_STATS; 903 904 typedef struct { 905 uint8_t noiseImmunityLevel; /* Global for pre-AR9380; OFDM later*/ 906 uint8_t cckNoiseImmunityLevel; /* AR9380: CCK specific NI */ 907 uint8_t spurImmunityLevel; 908 uint8_t firstepLevel; 909 uint8_t ofdmWeakSigDetectOff; 910 uint8_t cckWeakSigThreshold; 911 uint8_t mrcCck; /* MRC CCK is enabled */ 912 uint32_t listenTime; 913 914 /* NB: intentionally ordered so data exported to user space is first */ 915 uint32_t txFrameCount; /* Last txFrameCount */ 916 uint32_t rxFrameCount; /* Last rx Frame count */ 917 uint32_t cycleCount; /* Last cycleCount 918 (to detect wrap-around) */ 919 uint32_t ofdmPhyErrCount;/* OFDM err count since last reset */ 920 uint32_t cckPhyErrCount; /* CCK err count since last reset */ 921 } HAL_ANI_STATE; 922 923 struct ath_desc; 924 struct ath_tx_status; 925 struct ath_rx_status; 926 struct ieee80211_channel; 927 928 /* 929 * This is a channel survey sample entry. 930 * 931 * The AR5212 ANI routines fill these samples. The ANI code then uses it 932 * when calculating listen time; it is also exported via a diagnostic 933 * API. 934 */ 935 typedef struct { 936 uint32_t seq_num; 937 uint32_t tx_busy; 938 uint32_t rx_busy; 939 uint32_t chan_busy; 940 uint32_t ext_chan_busy; 941 uint32_t cycle_count; 942 /* XXX TODO */ 943 uint32_t ofdm_phyerr_count; 944 uint32_t cck_phyerr_count; 945 } HAL_SURVEY_SAMPLE; 946 947 /* 948 * This provides 3.2 seconds of sample space given an 949 * ANI time of 1/10th of a second. This may not be enough! 950 */ 951 #define CHANNEL_SURVEY_SAMPLE_COUNT 32 952 953 typedef struct { 954 HAL_SURVEY_SAMPLE samples[CHANNEL_SURVEY_SAMPLE_COUNT]; 955 uint32_t cur_sample; /* current sample in sequence */ 956 uint32_t cur_seq; /* current sequence number */ 957 } HAL_CHANNEL_SURVEY; 958 959 /* 960 * ANI commands. 961 * 962 * These are used both internally and externally via the diagnostic 963 * API. 964 * 965 * Note that this is NOT the ANI commands being used via the INTMIT 966 * capability - that has a different mapping for some reason. 967 */ 968 typedef enum { 969 HAL_ANI_PRESENT = 0, /* is ANI support present */ 970 HAL_ANI_NOISE_IMMUNITY_LEVEL = 1, /* set level (global or ofdm) */ 971 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION = 2, /* enable/disable */ 972 HAL_ANI_CCK_WEAK_SIGNAL_THR = 3, /* enable/disable */ 973 HAL_ANI_FIRSTEP_LEVEL = 4, /* set level */ 974 HAL_ANI_SPUR_IMMUNITY_LEVEL = 5, /* set level */ 975 HAL_ANI_MODE = 6, /* 0 => manual, 1 => auto (XXX do not change) */ 976 HAL_ANI_PHYERR_RESET = 7, /* reset phy error stats */ 977 HAL_ANI_MRC_CCK = 8, 978 HAL_ANI_CCK_NOISE_IMMUNITY_LEVEL = 9, /* set level (cck) */ 979 } HAL_ANI_CMD; 980 981 #define HAL_ANI_ALL 0xffffffff 982 983 /* 984 * This is the layout of the ANI INTMIT capability. 985 * 986 * Notice that the command values differ to HAL_ANI_CMD. 987 */ 988 typedef enum { 989 HAL_CAP_INTMIT_PRESENT = 0, 990 HAL_CAP_INTMIT_ENABLE = 1, 991 HAL_CAP_INTMIT_NOISE_IMMUNITY_LEVEL = 2, 992 HAL_CAP_INTMIT_OFDM_WEAK_SIGNAL_LEVEL = 3, 993 HAL_CAP_INTMIT_CCK_WEAK_SIGNAL_THR = 4, 994 HAL_CAP_INTMIT_FIRSTEP_LEVEL = 5, 995 HAL_CAP_INTMIT_SPUR_IMMUNITY_LEVEL = 6 996 } HAL_CAP_INTMIT_CMD; 997 998 typedef struct { 999 int32_t pe_firpwr; /* FIR pwr out threshold */ 1000 int32_t pe_rrssi; /* Radar rssi thresh */ 1001 int32_t pe_height; /* Pulse height thresh */ 1002 int32_t pe_prssi; /* Pulse rssi thresh */ 1003 int32_t pe_inband; /* Inband thresh */ 1004 1005 /* The following params are only for AR5413 and later */ 1006 u_int32_t pe_relpwr; /* Relative power threshold in 0.5dB steps */ 1007 u_int32_t pe_relstep; /* Pulse Relative step threshold in 0.5dB steps */ 1008 u_int32_t pe_maxlen; /* Max length of radar sign in 0.8us units */ 1009 int32_t pe_usefir128; /* Use the average in-band power measured over 128 cycles */ 1010 int32_t pe_blockradar; /* 1011 * Enable to block radar check if pkt detect is done via OFDM 1012 * weak signal detect or pkt is detected immediately after tx 1013 * to rx transition 1014 */ 1015 int32_t pe_enmaxrssi; /* 1016 * Enable to use the max rssi instead of the last rssi during 1017 * fine gain changes for radar detection 1018 */ 1019 int32_t pe_extchannel; /* Enable DFS on ext channel */ 1020 int32_t pe_enabled; /* Whether radar detection is enabled */ 1021 int32_t pe_enrelpwr; 1022 int32_t pe_en_relstep_check; 1023 } HAL_PHYERR_PARAM; 1024 1025 #define HAL_PHYERR_PARAM_NOVAL 65535 1026 1027 typedef struct { 1028 u_int16_t ss_fft_period; /* Skip interval for FFT reports */ 1029 u_int16_t ss_period; /* Spectral scan period */ 1030 u_int16_t ss_count; /* # of reports to return from ss_active */ 1031 u_int16_t ss_short_report;/* Set to report only 1 set of FFT results */ 1032 u_int8_t radar_bin_thresh_sel; /* strong signal radar FFT threshold configuration */ 1033 u_int16_t ss_spectral_pri; /* are we doing a noise power cal ? */ 1034 int8_t ss_nf_cal[AH_MAX_CHAINS*2]; /* nf calibrated values for ctl+ext from eeprom */ 1035 int8_t ss_nf_pwr[AH_MAX_CHAINS*2]; /* nf pwr values for ctl+ext from eeprom */ 1036 int32_t ss_nf_temp_data; /* temperature data taken during nf scan */ 1037 int ss_enabled; 1038 int ss_active; 1039 } HAL_SPECTRAL_PARAM; 1040 #define HAL_SPECTRAL_PARAM_NOVAL 0xFFFF 1041 #define HAL_SPECTRAL_PARAM_ENABLE 0x8000 /* Enable/Disable if applicable */ 1042 1043 /* 1044 * DFS operating mode flags. 1045 */ 1046 typedef enum { 1047 HAL_DFS_UNINIT_DOMAIN = 0, /* Uninitialized dfs domain */ 1048 HAL_DFS_FCC_DOMAIN = 1, /* FCC3 dfs domain */ 1049 HAL_DFS_ETSI_DOMAIN = 2, /* ETSI dfs domain */ 1050 HAL_DFS_MKK4_DOMAIN = 3, /* Japan dfs domain */ 1051 } HAL_DFS_DOMAIN; 1052 1053 /* 1054 * MFP decryption options for initializing the MAC. 1055 */ 1056 typedef enum { 1057 HAL_MFP_QOSDATA = 0, /* Decrypt MFP frames like QoS data frames. All chips before Merlin. */ 1058 HAL_MFP_PASSTHRU, /* Don't decrypt MFP frames at all. Passthrough */ 1059 HAL_MFP_HW_CRYPTO /* hardware decryption enabled. Merlin can do it. */ 1060 } HAL_MFP_OPT_T; 1061 1062 /* LNA config supported */ 1063 typedef enum { 1064 HAL_ANT_DIV_COMB_LNA1_MINUS_LNA2 = 0, 1065 HAL_ANT_DIV_COMB_LNA2 = 1, 1066 HAL_ANT_DIV_COMB_LNA1 = 2, 1067 HAL_ANT_DIV_COMB_LNA1_PLUS_LNA2 = 3, 1068 } HAL_ANT_DIV_COMB_LNA_CONF; 1069 1070 typedef struct { 1071 u_int8_t main_lna_conf; 1072 u_int8_t alt_lna_conf; 1073 u_int8_t fast_div_bias; 1074 u_int8_t main_gaintb; 1075 u_int8_t alt_gaintb; 1076 u_int8_t antdiv_configgroup; 1077 int8_t lna1_lna2_delta; 1078 } HAL_ANT_COMB_CONFIG; 1079 1080 #define DEFAULT_ANTDIV_CONFIG_GROUP 0x00 1081 #define HAL_ANTDIV_CONFIG_GROUP_1 0x01 1082 #define HAL_ANTDIV_CONFIG_GROUP_2 0x02 1083 #define HAL_ANTDIV_CONFIG_GROUP_3 0x03 1084 1085 /* 1086 * Flag for setting QUIET period 1087 */ 1088 typedef enum { 1089 HAL_QUIET_DISABLE = 0x0, 1090 HAL_QUIET_ENABLE = 0x1, 1091 HAL_QUIET_ADD_CURRENT_TSF = 0x2, /* add current TSF to next_start offset */ 1092 HAL_QUIET_ADD_SWBA_RESP_TIME = 0x4, /* add beacon response time to next_start offset */ 1093 } HAL_QUIET_FLAG; 1094 1095 #define HAL_DFS_EVENT_PRICH 0x0000001 1096 #define HAL_DFS_EVENT_EXTCH 0x0000002 1097 #define HAL_DFS_EVENT_EXTEARLY 0x0000004 1098 #define HAL_DFS_EVENT_ISDC 0x0000008 1099 1100 struct hal_dfs_event { 1101 uint64_t re_full_ts; /* 64-bit full timestamp from interrupt time */ 1102 uint32_t re_ts; /* Original 15 bit recv timestamp */ 1103 uint8_t re_rssi; /* rssi of radar event */ 1104 uint8_t re_dur; /* duration of radar pulse */ 1105 uint32_t re_flags; /* Flags (see above) */ 1106 }; 1107 typedef struct hal_dfs_event HAL_DFS_EVENT; 1108 1109 /* 1110 * Generic Timer domain 1111 */ 1112 typedef enum { 1113 HAL_GEN_TIMER_TSF = 0, 1114 HAL_GEN_TIMER_TSF2, 1115 HAL_GEN_TIMER_TSF_ANY 1116 } HAL_GEN_TIMER_DOMAIN; 1117 1118 /* 1119 * BT Co-existence definitions 1120 */ 1121 #include "ath_hal/ah_btcoex.h" 1122 1123 struct hal_bb_panic_info { 1124 u_int32_t status; 1125 u_int32_t tsf; 1126 u_int32_t phy_panic_wd_ctl1; 1127 u_int32_t phy_panic_wd_ctl2; 1128 u_int32_t phy_gen_ctrl; 1129 u_int32_t rxc_pcnt; 1130 u_int32_t rxf_pcnt; 1131 u_int32_t txf_pcnt; 1132 u_int32_t cycles; 1133 u_int32_t wd; 1134 u_int32_t det; 1135 u_int32_t rdar; 1136 u_int32_t r_odfm; 1137 u_int32_t r_cck; 1138 u_int32_t t_odfm; 1139 u_int32_t t_cck; 1140 u_int32_t agc; 1141 u_int32_t src; 1142 }; 1143 1144 /* Serialize Register Access Mode */ 1145 typedef enum { 1146 SER_REG_MODE_OFF = 0, 1147 SER_REG_MODE_ON = 1, 1148 SER_REG_MODE_AUTO = 2, 1149 } SER_REG_MODE; 1150 1151 typedef struct 1152 { 1153 int ah_debug; /* only used if AH_DEBUG is defined */ 1154 int ah_ar5416_biasadj; /* enable AR2133 radio specific bias fiddling */ 1155 1156 /* NB: these are deprecated; they exist for now for compatibility */ 1157 int ah_dma_beacon_response_time;/* in TU's */ 1158 int ah_sw_beacon_response_time; /* in TU's */ 1159 int ah_additional_swba_backoff; /* in TU's */ 1160 int ah_force_full_reset; /* force full chip reset rather then warm reset */ 1161 int ah_serialise_reg_war; /* force serialisation of register IO */ 1162 1163 /* XXX these don't belong here, they're just for the ar9300 HAL port effort */ 1164 int ath_hal_desc_tpc; /* Per-packet TPC */ 1165 int ath_hal_sta_update_tx_pwr_enable; /* GreenTX */ 1166 int ath_hal_sta_update_tx_pwr_enable_S1; /* GreenTX */ 1167 int ath_hal_sta_update_tx_pwr_enable_S2; /* GreenTX */ 1168 int ath_hal_sta_update_tx_pwr_enable_S3; /* GreenTX */ 1169 1170 /* I'm not sure what the default values for these should be */ 1171 int ath_hal_pll_pwr_save; 1172 int ath_hal_pcie_power_save_enable; 1173 int ath_hal_intr_mitigation_rx; 1174 int ath_hal_intr_mitigation_tx; 1175 1176 int ath_hal_pcie_clock_req; 1177 #define AR_PCIE_PLL_PWRSAVE_CONTROL (1<<0) 1178 #define AR_PCIE_PLL_PWRSAVE_ON_D3 (1<<1) 1179 #define AR_PCIE_PLL_PWRSAVE_ON_D0 (1<<2) 1180 1181 int ath_hal_pcie_waen; 1182 int ath_hal_pcie_ser_des_write; 1183 1184 /* these are important for correct AR9300 behaviour */ 1185 int ath_hal_ht_enable; /* needs to be enabled for AR9300 HT */ 1186 int ath_hal_diversity_control; 1187 int ath_hal_antenna_switch_swap; 1188 int ath_hal_ext_lna_ctl_gpio; 1189 int ath_hal_spur_mode; 1190 int ath_hal_6mb_ack; /* should set this to 1 for 11a/11na? */ 1191 int ath_hal_enable_msi; /* enable MSI interrupts (needed?) */ 1192 int ath_hal_beacon_filter_interval; /* ok to be 0 for now? */ 1193 1194 /* For now, set this to 0 - net80211 needs to know about hardware MFP support */ 1195 int ath_hal_mfp_support; 1196 1197 int ath_hal_enable_ani; /* should set this.. */ 1198 int ath_hal_cwm_ignore_ext_cca; 1199 int ath_hal_show_bb_panic; 1200 int ath_hal_ant_ctrl_comm2g_switch_enable; 1201 int ath_hal_ext_atten_margin_cfg; 1202 int ath_hal_min_gainidx; 1203 int ath_hal_war70c; 1204 uint32_t ath_hal_mci_config; 1205 } HAL_OPS_CONFIG; 1206 1207 /* 1208 * Hardware Access Layer (HAL) API. 1209 * 1210 * Clients of the HAL call ath_hal_attach to obtain a reference to an 1211 * ath_hal structure for use with the device. Hardware-related operations 1212 * that follow must call back into the HAL through interface, supplying 1213 * the reference as the first parameter. Note that before using the 1214 * reference returned by ath_hal_attach the caller should verify the 1215 * ABI version number. 1216 */ 1217 struct ath_hal { 1218 uint32_t ah_magic; /* consistency check magic number */ 1219 uint16_t ah_devid; /* PCI device ID */ 1220 uint16_t ah_subvendorid; /* PCI subvendor ID */ 1221 HAL_SOFTC ah_sc; /* back pointer to driver/os state */ 1222 HAL_BUS_TAG ah_st; /* params for register r+w */ 1223 HAL_BUS_HANDLE ah_sh; 1224 HAL_CTRY_CODE ah_countryCode; 1225 1226 uint32_t ah_macVersion; /* MAC version id */ 1227 uint16_t ah_macRev; /* MAC revision */ 1228 uint16_t ah_phyRev; /* PHY revision */ 1229 /* NB: when only one radio is present the rev is in 5Ghz */ 1230 uint16_t ah_analog5GhzRev;/* 5GHz radio revision */ 1231 uint16_t ah_analog2GhzRev;/* 2GHz radio revision */ 1232 1233 uint16_t *ah_eepromdata; /* eeprom buffer, if needed */ 1234 1235 uint32_t ah_intrstate[8]; /* last int state */ 1236 uint32_t ah_syncstate; /* last sync intr state */ 1237 1238 /* Current powerstate from HAL calls */ 1239 HAL_POWER_MODE ah_powerMode; 1240 1241 HAL_OPS_CONFIG ah_config; 1242 const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *, 1243 u_int mode); 1244 void __ahdecl(*ah_detach)(struct ath_hal*); 1245 1246 /* Reset functions */ 1247 HAL_BOOL __ahdecl(*ah_reset)(struct ath_hal *, HAL_OPMODE, 1248 struct ieee80211_channel *, 1249 HAL_BOOL bChannelChange, 1250 HAL_RESET_TYPE resetType, 1251 HAL_STATUS *status); 1252 HAL_BOOL __ahdecl(*ah_phyDisable)(struct ath_hal *); 1253 HAL_BOOL __ahdecl(*ah_disable)(struct ath_hal *); 1254 void __ahdecl(*ah_configPCIE)(struct ath_hal *, HAL_BOOL restore, 1255 HAL_BOOL power_off); 1256 void __ahdecl(*ah_disablePCIE)(struct ath_hal *); 1257 void __ahdecl(*ah_setPCUConfig)(struct ath_hal *); 1258 HAL_BOOL __ahdecl(*ah_perCalibration)(struct ath_hal*, 1259 struct ieee80211_channel *, HAL_BOOL *); 1260 HAL_BOOL __ahdecl(*ah_perCalibrationN)(struct ath_hal *, 1261 struct ieee80211_channel *, u_int chainMask, 1262 HAL_BOOL longCal, HAL_BOOL *isCalDone); 1263 HAL_BOOL __ahdecl(*ah_resetCalValid)(struct ath_hal *, 1264 const struct ieee80211_channel *); 1265 HAL_BOOL __ahdecl(*ah_setTxPower)(struct ath_hal *, 1266 const struct ieee80211_channel *, uint16_t *); 1267 HAL_BOOL __ahdecl(*ah_setTxPowerLimit)(struct ath_hal *, uint32_t); 1268 HAL_BOOL __ahdecl(*ah_setBoardValues)(struct ath_hal *, 1269 const struct ieee80211_channel *); 1270 1271 /* Transmit functions */ 1272 HAL_BOOL __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*, 1273 HAL_BOOL incTrigLevel); 1274 int __ahdecl(*ah_setupTxQueue)(struct ath_hal *, HAL_TX_QUEUE, 1275 const HAL_TXQ_INFO *qInfo); 1276 HAL_BOOL __ahdecl(*ah_setTxQueueProps)(struct ath_hal *, int q, 1277 const HAL_TXQ_INFO *qInfo); 1278 HAL_BOOL __ahdecl(*ah_getTxQueueProps)(struct ath_hal *, int q, 1279 HAL_TXQ_INFO *qInfo); 1280 HAL_BOOL __ahdecl(*ah_releaseTxQueue)(struct ath_hal *ah, u_int q); 1281 HAL_BOOL __ahdecl(*ah_resetTxQueue)(struct ath_hal *ah, u_int q); 1282 uint32_t __ahdecl(*ah_getTxDP)(struct ath_hal*, u_int); 1283 HAL_BOOL __ahdecl(*ah_setTxDP)(struct ath_hal*, u_int, uint32_t txdp); 1284 uint32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, u_int q); 1285 HAL_BOOL __ahdecl(*ah_startTxDma)(struct ath_hal*, u_int); 1286 HAL_BOOL __ahdecl(*ah_stopTxDma)(struct ath_hal*, u_int); 1287 HAL_BOOL __ahdecl(*ah_setupTxDesc)(struct ath_hal *, struct ath_desc *, 1288 u_int pktLen, u_int hdrLen, 1289 HAL_PKT_TYPE type, u_int txPower, 1290 u_int txRate0, u_int txTries0, 1291 u_int keyIx, u_int antMode, u_int flags, 1292 u_int rtsctsRate, u_int rtsctsDuration, 1293 u_int compicvLen, u_int compivLen, 1294 u_int comp); 1295 HAL_BOOL __ahdecl(*ah_setupXTxDesc)(struct ath_hal *, struct ath_desc*, 1296 u_int txRate1, u_int txTries1, 1297 u_int txRate2, u_int txTries2, 1298 u_int txRate3, u_int txTries3); 1299 HAL_BOOL __ahdecl(*ah_fillTxDesc)(struct ath_hal *, struct ath_desc *, 1300 HAL_DMA_ADDR *bufAddrList, uint32_t *segLenList, 1301 u_int descId, u_int qcuId, HAL_BOOL firstSeg, 1302 HAL_BOOL lastSeg, const struct ath_desc *); 1303 HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *, 1304 struct ath_desc *, struct ath_tx_status *); 1305 void __ahdecl(*ah_getTxIntrQueue)(struct ath_hal *, uint32_t *); 1306 void __ahdecl(*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc*); 1307 HAL_BOOL __ahdecl(*ah_getTxCompletionRates)(struct ath_hal *, 1308 const struct ath_desc *ds, int *rates, int *tries); 1309 void __ahdecl(*ah_setTxDescLink)(struct ath_hal *ah, void *ds, 1310 uint32_t link); 1311 void __ahdecl(*ah_getTxDescLink)(struct ath_hal *ah, void *ds, 1312 uint32_t *link); 1313 void __ahdecl(*ah_getTxDescLinkPtr)(struct ath_hal *ah, void *ds, 1314 uint32_t **linkptr); 1315 void __ahdecl(*ah_setupTxStatusRing)(struct ath_hal *, 1316 void *ts_start, uint32_t ts_paddr_start, 1317 uint16_t size); 1318 void __ahdecl(*ah_getTxRawTxDesc)(struct ath_hal *, u_int32_t *); 1319 1320 /* Receive Functions */ 1321 uint32_t __ahdecl(*ah_getRxDP)(struct ath_hal*, HAL_RX_QUEUE); 1322 void __ahdecl(*ah_setRxDP)(struct ath_hal*, uint32_t rxdp, HAL_RX_QUEUE); 1323 void __ahdecl(*ah_enableReceive)(struct ath_hal*); 1324 HAL_BOOL __ahdecl(*ah_stopDmaReceive)(struct ath_hal*); 1325 void __ahdecl(*ah_startPcuReceive)(struct ath_hal*, HAL_BOOL); 1326 void __ahdecl(*ah_stopPcuReceive)(struct ath_hal*); 1327 void __ahdecl(*ah_setMulticastFilter)(struct ath_hal*, 1328 uint32_t filter0, uint32_t filter1); 1329 HAL_BOOL __ahdecl(*ah_setMulticastFilterIndex)(struct ath_hal*, 1330 uint32_t index); 1331 HAL_BOOL __ahdecl(*ah_clrMulticastFilterIndex)(struct ath_hal*, 1332 uint32_t index); 1333 uint32_t __ahdecl(*ah_getRxFilter)(struct ath_hal*); 1334 void __ahdecl(*ah_setRxFilter)(struct ath_hal*, uint32_t); 1335 HAL_BOOL __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_desc *, 1336 uint32_t size, u_int flags); 1337 HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *, 1338 struct ath_desc *, uint32_t phyAddr, 1339 struct ath_desc *next, uint64_t tsf, 1340 struct ath_rx_status *); 1341 void __ahdecl(*ah_rxMonitor)(struct ath_hal *, 1342 const HAL_NODE_STATS *, 1343 const struct ieee80211_channel *); 1344 void __ahdecl(*ah_aniPoll)(struct ath_hal *, 1345 const struct ieee80211_channel *); 1346 void __ahdecl(*ah_procMibEvent)(struct ath_hal *, 1347 const HAL_NODE_STATS *); 1348 1349 /* Misc Functions */ 1350 HAL_STATUS __ahdecl(*ah_getCapability)(struct ath_hal *, 1351 HAL_CAPABILITY_TYPE, uint32_t capability, 1352 uint32_t *result); 1353 HAL_BOOL __ahdecl(*ah_setCapability)(struct ath_hal *, 1354 HAL_CAPABILITY_TYPE, uint32_t capability, 1355 uint32_t setting, HAL_STATUS *); 1356 HAL_BOOL __ahdecl(*ah_getDiagState)(struct ath_hal *, int request, 1357 const void *args, uint32_t argsize, 1358 void **result, uint32_t *resultsize); 1359 void __ahdecl(*ah_getMacAddress)(struct ath_hal *, uint8_t *); 1360 HAL_BOOL __ahdecl(*ah_setMacAddress)(struct ath_hal *, const uint8_t*); 1361 void __ahdecl(*ah_getBssIdMask)(struct ath_hal *, uint8_t *); 1362 HAL_BOOL __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const uint8_t*); 1363 HAL_BOOL __ahdecl(*ah_setRegulatoryDomain)(struct ath_hal*, 1364 uint16_t, HAL_STATUS *); 1365 void __ahdecl(*ah_setLedState)(struct ath_hal*, HAL_LED_STATE); 1366 void __ahdecl(*ah_writeAssocid)(struct ath_hal*, 1367 const uint8_t *bssid, uint16_t assocId); 1368 HAL_BOOL __ahdecl(*ah_gpioCfgOutput)(struct ath_hal *, 1369 uint32_t gpio, HAL_GPIO_MUX_TYPE); 1370 HAL_BOOL __ahdecl(*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio); 1371 uint32_t __ahdecl(*ah_gpioGet)(struct ath_hal *, uint32_t gpio); 1372 HAL_BOOL __ahdecl(*ah_gpioSet)(struct ath_hal *, 1373 uint32_t gpio, uint32_t val); 1374 void __ahdecl(*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t); 1375 uint32_t __ahdecl(*ah_getTsf32)(struct ath_hal*); 1376 uint64_t __ahdecl(*ah_getTsf64)(struct ath_hal*); 1377 void __ahdecl(*ah_setTsf64)(struct ath_hal *, uint64_t); 1378 void __ahdecl(*ah_resetTsf)(struct ath_hal*); 1379 HAL_BOOL __ahdecl(*ah_detectCardPresent)(struct ath_hal*); 1380 void __ahdecl(*ah_updateMibCounters)(struct ath_hal*, 1381 HAL_MIB_STATS*); 1382 HAL_RFGAIN __ahdecl(*ah_getRfGain)(struct ath_hal*); 1383 u_int __ahdecl(*ah_getDefAntenna)(struct ath_hal*); 1384 void __ahdecl(*ah_setDefAntenna)(struct ath_hal*, u_int); 1385 HAL_ANT_SETTING __ahdecl(*ah_getAntennaSwitch)(struct ath_hal*); 1386 HAL_BOOL __ahdecl(*ah_setAntennaSwitch)(struct ath_hal*, 1387 HAL_ANT_SETTING); 1388 HAL_BOOL __ahdecl(*ah_setSifsTime)(struct ath_hal*, u_int); 1389 u_int __ahdecl(*ah_getSifsTime)(struct ath_hal*); 1390 HAL_BOOL __ahdecl(*ah_setSlotTime)(struct ath_hal*, u_int); 1391 u_int __ahdecl(*ah_getSlotTime)(struct ath_hal*); 1392 HAL_BOOL __ahdecl(*ah_setAckTimeout)(struct ath_hal*, u_int); 1393 u_int __ahdecl(*ah_getAckTimeout)(struct ath_hal*); 1394 HAL_BOOL __ahdecl(*ah_setAckCTSRate)(struct ath_hal*, u_int); 1395 u_int __ahdecl(*ah_getAckCTSRate)(struct ath_hal*); 1396 HAL_BOOL __ahdecl(*ah_setCTSTimeout)(struct ath_hal*, u_int); 1397 u_int __ahdecl(*ah_getCTSTimeout)(struct ath_hal*); 1398 HAL_BOOL __ahdecl(*ah_setDecompMask)(struct ath_hal*, uint16_t, int); 1399 void __ahdecl(*ah_setCoverageClass)(struct ath_hal*, uint8_t, int); 1400 HAL_STATUS __ahdecl(*ah_setQuiet)(struct ath_hal *ah, uint32_t period, 1401 uint32_t duration, uint32_t nextStart, 1402 HAL_QUIET_FLAG flag); 1403 void __ahdecl(*ah_setChainMasks)(struct ath_hal *, 1404 uint32_t, uint32_t); 1405 u_int __ahdecl(*ah_getNav)(struct ath_hal*); 1406 void __ahdecl(*ah_setNav)(struct ath_hal*, u_int); 1407 1408 /* DFS functions */ 1409 void __ahdecl(*ah_enableDfs)(struct ath_hal *ah, 1410 HAL_PHYERR_PARAM *pe); 1411 void __ahdecl(*ah_getDfsThresh)(struct ath_hal *ah, 1412 HAL_PHYERR_PARAM *pe); 1413 HAL_BOOL __ahdecl(*ah_getDfsDefaultThresh)(struct ath_hal *ah, 1414 HAL_PHYERR_PARAM *pe); 1415 HAL_BOOL __ahdecl(*ah_procRadarEvent)(struct ath_hal *ah, 1416 struct ath_rx_status *rxs, uint64_t fulltsf, 1417 const char *buf, HAL_DFS_EVENT *event); 1418 HAL_BOOL __ahdecl(*ah_isFastClockEnabled)(struct ath_hal *ah); 1419 void __ahdecl(*ah_setDfsCacTxQuiet)(struct ath_hal *, HAL_BOOL); 1420 1421 /* Spectral Scan functions */ 1422 void __ahdecl(*ah_spectralConfigure)(struct ath_hal *ah, 1423 HAL_SPECTRAL_PARAM *sp); 1424 void __ahdecl(*ah_spectralGetConfig)(struct ath_hal *ah, 1425 HAL_SPECTRAL_PARAM *sp); 1426 void __ahdecl(*ah_spectralStart)(struct ath_hal *); 1427 void __ahdecl(*ah_spectralStop)(struct ath_hal *); 1428 HAL_BOOL __ahdecl(*ah_spectralIsEnabled)(struct ath_hal *); 1429 HAL_BOOL __ahdecl(*ah_spectralIsActive)(struct ath_hal *); 1430 /* XXX getNfPri() and getNfExt() */ 1431 1432 /* Key Cache Functions */ 1433 uint32_t __ahdecl(*ah_getKeyCacheSize)(struct ath_hal*); 1434 HAL_BOOL __ahdecl(*ah_resetKeyCacheEntry)(struct ath_hal*, uint16_t); 1435 HAL_BOOL __ahdecl(*ah_isKeyCacheEntryValid)(struct ath_hal *, 1436 uint16_t); 1437 HAL_BOOL __ahdecl(*ah_setKeyCacheEntry)(struct ath_hal*, 1438 uint16_t, const HAL_KEYVAL *, 1439 const uint8_t *, int); 1440 HAL_BOOL __ahdecl(*ah_setKeyCacheEntryMac)(struct ath_hal*, 1441 uint16_t, const uint8_t *); 1442 1443 /* Power Management Functions */ 1444 HAL_BOOL __ahdecl(*ah_setPowerMode)(struct ath_hal*, 1445 HAL_POWER_MODE mode, int setChip); 1446 HAL_POWER_MODE __ahdecl(*ah_getPowerMode)(struct ath_hal*); 1447 int16_t __ahdecl(*ah_getChanNoise)(struct ath_hal *, 1448 const struct ieee80211_channel *); 1449 1450 /* Beacon Management Functions */ 1451 void __ahdecl(*ah_setBeaconTimers)(struct ath_hal*, 1452 const HAL_BEACON_TIMERS *); 1453 /* NB: deprecated, use ah_setBeaconTimers instead */ 1454 void __ahdecl(*ah_beaconInit)(struct ath_hal *, 1455 uint32_t nexttbtt, uint32_t intval); 1456 void __ahdecl(*ah_setStationBeaconTimers)(struct ath_hal*, 1457 const HAL_BEACON_STATE *); 1458 void __ahdecl(*ah_resetStationBeaconTimers)(struct ath_hal*); 1459 uint64_t __ahdecl(*ah_getNextTBTT)(struct ath_hal *); 1460 1461 /* 802.11n Functions */ 1462 HAL_BOOL __ahdecl(*ah_chainTxDesc)(struct ath_hal *, 1463 struct ath_desc *, 1464 HAL_DMA_ADDR *bufAddrList, 1465 uint32_t *segLenList, 1466 u_int, u_int, HAL_PKT_TYPE, 1467 u_int, HAL_CIPHER, uint8_t, HAL_BOOL, 1468 HAL_BOOL, HAL_BOOL); 1469 HAL_BOOL __ahdecl(*ah_setupFirstTxDesc)(struct ath_hal *, 1470 struct ath_desc *, u_int, u_int, u_int, 1471 u_int, u_int, u_int, u_int, u_int); 1472 HAL_BOOL __ahdecl(*ah_setupLastTxDesc)(struct ath_hal *, 1473 struct ath_desc *, const struct ath_desc *); 1474 void __ahdecl(*ah_set11nRateScenario)(struct ath_hal *, 1475 struct ath_desc *, u_int, u_int, 1476 HAL_11N_RATE_SERIES [], u_int, u_int); 1477 1478 /* 1479 * The next 4 (set11ntxdesc -> set11naggrlast) are specific 1480 * to the EDMA HAL. Descriptors are chained together by 1481 * using filltxdesc (not ChainTxDesc) and then setting the 1482 * aggregate flags appropriately using first/middle/last. 1483 */ 1484 void __ahdecl(*ah_set11nTxDesc)(struct ath_hal *, 1485 void *, u_int, HAL_PKT_TYPE, u_int, u_int, 1486 u_int); 1487 void __ahdecl(*ah_set11nAggrFirst)(struct ath_hal *, 1488 struct ath_desc *, u_int, u_int); 1489 void __ahdecl(*ah_set11nAggrMiddle)(struct ath_hal *, 1490 struct ath_desc *, u_int); 1491 void __ahdecl(*ah_set11nAggrLast)(struct ath_hal *, 1492 struct ath_desc *); 1493 void __ahdecl(*ah_clr11nAggr)(struct ath_hal *, 1494 struct ath_desc *); 1495 void __ahdecl(*ah_set11nBurstDuration)(struct ath_hal *, 1496 struct ath_desc *, u_int); 1497 void __ahdecl(*ah_set11nVirtMoreFrag)(struct ath_hal *, 1498 struct ath_desc *, u_int); 1499 1500 HAL_BOOL __ahdecl(*ah_getMibCycleCounts) (struct ath_hal *, 1501 HAL_SURVEY_SAMPLE *); 1502 1503 uint32_t __ahdecl(*ah_get11nExtBusy)(struct ath_hal *); 1504 void __ahdecl(*ah_set11nMac2040)(struct ath_hal *, 1505 HAL_HT_MACMODE); 1506 HAL_HT_RXCLEAR __ahdecl(*ah_get11nRxClear)(struct ath_hal *ah); 1507 void __ahdecl(*ah_set11nRxClear)(struct ath_hal *, 1508 HAL_HT_RXCLEAR); 1509 1510 /* Interrupt functions */ 1511 HAL_BOOL __ahdecl(*ah_isInterruptPending)(struct ath_hal*); 1512 HAL_BOOL __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT*); 1513 HAL_INT __ahdecl(*ah_getInterrupts)(struct ath_hal*); 1514 HAL_INT __ahdecl(*ah_setInterrupts)(struct ath_hal*, HAL_INT); 1515 1516 /* Bluetooth Coexistence functions */ 1517 void __ahdecl(*ah_btCoexSetInfo)(struct ath_hal *, 1518 HAL_BT_COEX_INFO *); 1519 void __ahdecl(*ah_btCoexSetConfig)(struct ath_hal *, 1520 HAL_BT_COEX_CONFIG *); 1521 void __ahdecl(*ah_btCoexSetQcuThresh)(struct ath_hal *, 1522 int); 1523 void __ahdecl(*ah_btCoexSetWeights)(struct ath_hal *, 1524 uint32_t); 1525 void __ahdecl(*ah_btCoexSetBmissThresh)(struct ath_hal *, 1526 uint32_t); 1527 void __ahdecl(*ah_btCoexSetParameter)(struct ath_hal *, 1528 uint32_t, uint32_t); 1529 void __ahdecl(*ah_btCoexDisable)(struct ath_hal *); 1530 int __ahdecl(*ah_btCoexEnable)(struct ath_hal *); 1531 1532 /* Bluetooth MCI methods */ 1533 void __ahdecl(*ah_btMciSetup)(struct ath_hal *, 1534 uint32_t, void *, uint16_t, uint32_t); 1535 HAL_BOOL __ahdecl(*ah_btMciSendMessage)(struct ath_hal *, 1536 uint8_t, uint32_t, uint32_t *, uint8_t, 1537 HAL_BOOL, HAL_BOOL); 1538 uint32_t __ahdecl(*ah_btMciGetInterrupt)(struct ath_hal *, 1539 uint32_t *, uint32_t *); 1540 uint32_t __ahdecl(*ah_btMciState)(struct ath_hal *, 1541 uint32_t, uint32_t *); 1542 void __ahdecl(*ah_btMciDetach)(struct ath_hal *); 1543 1544 /* LNA diversity configuration */ 1545 void __ahdecl(*ah_divLnaConfGet)(struct ath_hal *, 1546 HAL_ANT_COMB_CONFIG *); 1547 void __ahdecl(*ah_divLnaConfSet)(struct ath_hal *, 1548 HAL_ANT_COMB_CONFIG *); 1549 }; 1550 1551 /* 1552 * Check the PCI vendor ID and device ID against Atheros' values 1553 * and return a printable description for any Atheros hardware. 1554 * AH_NULL is returned if the ID's do not describe Atheros hardware. 1555 */ 1556 extern const char *__ahdecl ath_hal_probe(uint16_t vendorid, uint16_t devid); 1557 1558 /* 1559 * Attach the HAL for use with the specified device. The device is 1560 * defined by the PCI device ID. The caller provides an opaque pointer 1561 * to an upper-layer data structure (HAL_SOFTC) that is stored in the 1562 * HAL state block for later use. Hardware register accesses are done 1563 * using the specified bus tag and handle. On successful return a 1564 * reference to a state block is returned that must be supplied in all 1565 * subsequent HAL calls. Storage associated with this reference is 1566 * dynamically allocated and must be freed by calling the ah_detach 1567 * method when the client is done. If the attach operation fails a 1568 * null (AH_NULL) reference will be returned and a status code will 1569 * be returned if the status parameter is non-zero. 1570 */ 1571 extern struct ath_hal * __ahdecl ath_hal_attach(uint16_t devid, HAL_SOFTC, 1572 HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, 1573 HAL_OPS_CONFIG *ah_config, HAL_STATUS* status); 1574 1575 extern const char *ath_hal_mac_name(struct ath_hal *); 1576 extern const char *ath_hal_rf_name(struct ath_hal *); 1577 1578 /* 1579 * Regulatory interfaces. Drivers should use ath_hal_init_channels to 1580 * request a set of channels for a particular country code and/or 1581 * regulatory domain. If CTRY_DEFAULT and SKU_NONE are specified then 1582 * this list is constructed according to the contents of the EEPROM. 1583 * ath_hal_getchannels acts similarly but does not alter the operating 1584 * state; this can be used to collect information for a particular 1585 * regulatory configuration. Finally ath_hal_set_channels installs a 1586 * channel list constructed outside the driver. The HAL will adopt the 1587 * channel list and setup internal state according to the specified 1588 * regulatory configuration (e.g. conformance test limits). 1589 * 1590 * For all interfaces the channel list is returned in the supplied array. 1591 * maxchans defines the maximum size of this array. nchans contains the 1592 * actual number of channels returned. If a problem occurred then a 1593 * status code != HAL_OK is returned. 1594 */ 1595 struct ieee80211_channel; 1596 1597 /* 1598 * Return a list of channels according to the specified regulatory. 1599 */ 1600 extern HAL_STATUS __ahdecl ath_hal_getchannels(struct ath_hal *, 1601 struct ieee80211_channel *chans, u_int maxchans, int *nchans, 1602 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn, 1603 HAL_BOOL enableExtendedChannels); 1604 1605 /* 1606 * Return a list of channels and install it as the current operating 1607 * regulatory list. 1608 */ 1609 extern HAL_STATUS __ahdecl ath_hal_init_channels(struct ath_hal *, 1610 struct ieee80211_channel *chans, u_int maxchans, int *nchans, 1611 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN rd, 1612 HAL_BOOL enableExtendedChannels); 1613 1614 /* 1615 * Install the list of channels as the current operating regulatory 1616 * and setup related state according to the country code and sku. 1617 */ 1618 extern HAL_STATUS __ahdecl ath_hal_set_channels(struct ath_hal *, 1619 struct ieee80211_channel *chans, int nchans, 1620 HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn); 1621 1622 /* 1623 * Fetch the ctl/ext noise floor values reported by a MIMO 1624 * radio. Returns 1 for valid results, 0 for invalid channel. 1625 */ 1626 extern int __ahdecl ath_hal_get_mimo_chan_noise(struct ath_hal *ah, 1627 const struct ieee80211_channel *chan, int16_t *nf_ctl, 1628 int16_t *nf_ext); 1629 1630 /* 1631 * Calibrate noise floor data following a channel scan or similar. 1632 * This must be called prior retrieving noise floor data. 1633 */ 1634 extern void __ahdecl ath_hal_process_noisefloor(struct ath_hal *ah); 1635 1636 /* 1637 * Return bit mask of wireless modes supported by the hardware. 1638 */ 1639 extern u_int __ahdecl ath_hal_getwirelessmodes(struct ath_hal*); 1640 1641 /* 1642 * Get the HAL wireless mode for the given channel. 1643 */ 1644 extern int ath_hal_get_curmode(struct ath_hal *ah, 1645 const struct ieee80211_channel *chan); 1646 1647 /* 1648 * Calculate the packet TX time for a legacy or 11n frame 1649 */ 1650 extern uint32_t __ahdecl ath_hal_pkt_txtime(struct ath_hal *ah, 1651 const HAL_RATE_TABLE *rates, uint32_t frameLen, 1652 uint16_t rateix, HAL_BOOL isht40, HAL_BOOL shortPreamble, 1653 HAL_BOOL includeSifs); 1654 1655 /* 1656 * Calculate the duration of an 11n frame. 1657 */ 1658 extern uint32_t __ahdecl ath_computedur_ht(uint32_t frameLen, uint16_t rate, 1659 int streams, HAL_BOOL isht40, HAL_BOOL isShortGI); 1660 1661 /* 1662 * Calculate the transmit duration of a legacy frame. 1663 */ 1664 extern uint16_t __ahdecl ath_hal_computetxtime(struct ath_hal *, 1665 const HAL_RATE_TABLE *rates, uint32_t frameLen, 1666 uint16_t rateix, HAL_BOOL shortPreamble, 1667 HAL_BOOL includeSifs); 1668 1669 /* 1670 * Adjust the TSF. 1671 */ 1672 extern void __ahdecl ath_hal_adjusttsf(struct ath_hal *ah, int32_t tsfdelta); 1673 1674 /* 1675 * Enable or disable CCA. 1676 */ 1677 void __ahdecl ath_hal_setcca(struct ath_hal *ah, int ena); 1678 1679 /* 1680 * Get CCA setting. 1681 */ 1682 int __ahdecl ath_hal_getcca(struct ath_hal *ah); 1683 1684 /* 1685 * Enable/disable and get self-gen frame (ACK, CTS) for CAC. 1686 */ 1687 void __ahdecl ath_hal_set_dfs_cac_tx_quiet(struct ath_hal *ah, HAL_BOOL ena); 1688 1689 /* 1690 * Read EEPROM data from ah_eepromdata 1691 */ 1692 HAL_BOOL __ahdecl ath_hal_EepromDataRead(struct ath_hal *ah, 1693 u_int off, uint16_t *data); 1694 1695 /* 1696 * For now, simply pass through MFP frames. 1697 */ 1698 static inline u_int32_t 1699 ath_hal_get_mfp_qos(struct ath_hal *ah) 1700 { 1701 //return AH_PRIVATE(ah)->ah_mfp_qos; 1702 return HAL_MFP_QOSDATA; 1703 } 1704 1705 /* 1706 * Convert between microseconds and core system clocks. 1707 */ 1708 extern u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs); 1709 extern u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks); 1710 extern uint64_t ath_hal_mac_psec(struct ath_hal *ah, u_int clks); 1711 1712 #endif /* _ATH_AH_H_ */ 1713