1 /* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19 20 #ifndef _ATH_AH_H_ 21 #define _ATH_AH_H_ 22 /* 23 * Atheros Hardware Access Layer 24 * 25 * Clients of the HAL call ath_hal_attach to obtain a reference to an ath_hal 26 * structure for use with the device. Hardware-related operations that 27 * follow must call back into the HAL through interface, supplying the 28 * reference as the first parameter. 29 */ 30 31 #include "ah_osdep.h" 32 33 /* 34 * The maximum number of TX/RX chains supported. 35 * This is intended to be used by various statistics gathering operations 36 * (NF, RSSI, EVM). 37 */ 38 #define AH_MAX_CHAINS 3 39 #define AH_MIMO_MAX_EVM_PILOTS 6 40 41 /* 42 * __ahdecl is analogous to _cdecl; it defines the calling 43 * convention used within the HAL. For most systems this 44 * can just default to be empty and the compiler will (should) 45 * use _cdecl. For systems where _cdecl is not compatible this 46 * must be defined. See linux/ah_osdep.h for an example. 47 */ 48 #ifndef __ahdecl 49 #define __ahdecl 50 #endif 51 52 /* 53 * Status codes that may be returned by the HAL. Note that 54 * interfaces that return a status code set it only when an 55 * error occurs--i.e. you cannot check it for success. 56 */ 57 typedef enum { 58 HAL_OK = 0, /* No error */ 59 HAL_ENXIO = 1, /* No hardware present */ 60 HAL_ENOMEM = 2, /* Memory allocation failed */ 61 HAL_EIO = 3, /* Hardware didn't respond as expected */ 62 HAL_EEMAGIC = 4, /* EEPROM magic number invalid */ 63 HAL_EEVERSION = 5, /* EEPROM version invalid */ 64 HAL_EELOCKED = 6, /* EEPROM unreadable */ 65 HAL_EEBADSUM = 7, /* EEPROM checksum invalid */ 66 HAL_EEREAD = 8, /* EEPROM read problem */ 67 HAL_EEBADMAC = 9, /* EEPROM mac address invalid */ 68 HAL_EESIZE = 10, /* EEPROM size not supported */ 69 HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */ 70 HAL_EINVAL = 12, /* Invalid parameter to function */ 71 HAL_ENOTSUPP = 13, /* Hardware revision not supported */ 72 HAL_ESELFTEST = 14, /* Hardware self-test failed */ 73 HAL_EINPROGRESS = 15, /* Operation incomplete */ 74 HAL_EEBADREG = 16, /* EEPROM invalid regulatory contents */ 75 HAL_EEBADCC = 17, /* EEPROM invalid country code */ 76 HAL_INV_PMODE = 18, /* Couldn't bring out of sleep state */ 77 } HAL_STATUS; 78 79 typedef enum { 80 AH_FALSE = 0, /* NB: lots of code assumes false is zero */ 81 AH_TRUE = 1, 82 } HAL_BOOL; 83 84 typedef enum { 85 HAL_CAP_REG_DMN = 0, /* current regulatory domain */ 86 HAL_CAP_CIPHER = 1, /* hardware supports cipher */ 87 HAL_CAP_TKIP_MIC = 2, /* handle TKIP MIC in hardware */ 88 HAL_CAP_TKIP_SPLIT = 3, /* hardware TKIP uses split keys */ 89 HAL_CAP_PHYCOUNTERS = 4, /* hardware PHY error counters */ 90 HAL_CAP_DIVERSITY = 5, /* hardware supports fast diversity */ 91 HAL_CAP_KEYCACHE_SIZE = 6, /* number of entries in key cache */ 92 HAL_CAP_NUM_TXQUEUES = 7, /* number of hardware xmit queues */ 93 HAL_CAP_VEOL = 9, /* hardware supports virtual EOL */ 94 HAL_CAP_PSPOLL = 10, /* hardware has working PS-Poll support */ 95 HAL_CAP_DIAG = 11, /* hardware diagnostic support */ 96 HAL_CAP_COMPRESSION = 12, /* hardware supports compression */ 97 HAL_CAP_BURST = 13, /* hardware supports packet bursting */ 98 HAL_CAP_FASTFRAME = 14, /* hardware supoprts fast frames */ 99 HAL_CAP_TXPOW = 15, /* global tx power limit */ 100 HAL_CAP_TPC = 16, /* per-packet tx power control */ 101 HAL_CAP_PHYDIAG = 17, /* hardware phy error diagnostic */ 102 HAL_CAP_BSSIDMASK = 18, /* hardware supports bssid mask */ 103 HAL_CAP_MCAST_KEYSRCH = 19, /* hardware has multicast key search */ 104 HAL_CAP_TSF_ADJUST = 20, /* hardware has beacon tsf adjust */ 105 /* 21 was HAL_CAP_XR */ 106 HAL_CAP_WME_TKIPMIC = 22, /* hardware can support TKIP MIC when WMM is turned on */ 107 /* 23 was HAL_CAP_CHAN_HALFRATE */ 108 /* 24 was HAL_CAP_CHAN_QUARTERRATE */ 109 HAL_CAP_RFSILENT = 25, /* hardware has rfsilent support */ 110 HAL_CAP_TPC_ACK = 26, /* ack txpower with per-packet tpc */ 111 HAL_CAP_TPC_CTS = 27, /* cts txpower with per-packet tpc */ 112 HAL_CAP_11D = 28, /* 11d beacon support for changing cc */ 113 HAL_CAP_PCIE_PS = 29, 114 HAL_CAP_HT = 30, /* hardware can support HT */ 115 HAL_CAP_GTXTO = 31, /* hardware supports global tx timeout */ 116 HAL_CAP_FAST_CC = 32, /* hardware supports fast channel change */ 117 HAL_CAP_TX_CHAINMASK = 33, /* mask of TX chains supported */ 118 HAL_CAP_RX_CHAINMASK = 34, /* mask of RX chains supported */ 119 HAL_CAP_NUM_GPIO_PINS = 36, /* number of GPIO pins */ 120 121 HAL_CAP_CST = 38, /* hardware supports carrier sense timeout */ 122 HAL_CAP_RIFS_RX = 39, 123 HAL_CAP_RIFS_TX = 40, 124 HAL_CAP_FORCE_PPM = 41, 125 HAL_CAP_RTS_AGGR_LIMIT = 42, /* aggregation limit with RTS */ 126 HAL_CAP_4ADDR_AGGR = 43, /* hardware is capable of 4addr aggregation */ 127 HAL_CAP_DFS_DMN = 44, /* current DFS domain */ 128 HAL_CAP_EXT_CHAN_DFS = 45, /* DFS support for extension channel */ 129 HAL_CAP_COMBINED_RADAR_RSSI = 46, /* Is combined RSSI for radar accurate */ 130 131 HAL_CAP_AUTO_SLEEP = 48, /* hardware can go to network sleep 132 automatically after waking up to receive TIM */ 133 HAL_CAP_MBSSID_AGGR_SUPPORT = 49, /* Support for mBSSID Aggregation */ 134 HAL_CAP_SPLIT_4KB_TRANS = 50, /* hardware supports descriptors straddling a 4k page boundary */ 135 HAL_CAP_REG_FLAG = 51, /* Regulatory domain flags */ 136 HAL_CAP_BB_RIFS_HANG = 52, 137 HAL_CAP_RIFS_RX_ENABLED = 53, 138 HAL_CAP_BB_DFS_HANG = 54, 139 140 HAL_CAP_BT_COEX = 60, /* hardware is capable of bluetooth coexistence */ 141 HAL_CAP_DYNAMIC_SMPS = 61, /* Dynamic MIMO Power Save hardware support */ 142 143 HAL_CAP_DS = 67, /* 2 stream */ 144 HAL_CAP_BB_RX_CLEAR_STUCK_HANG = 68, 145 HAL_CAP_MAC_HANG = 69, /* can MAC hang */ 146 HAL_CAP_MFP = 70, /* Management Frame Protection in hardware */ 147 148 HAL_CAP_TS = 72, /* 3 stream */ 149 150 HAL_CAP_ENHANCED_DMA_SUPPORT = 75, /* DMA FIFO support */ 151 HAL_CAP_NUM_TXMAPS = 76, /* Number of buffers in a transmit descriptor */ 152 HAL_CAP_TXDESCLEN = 77, /* Length of transmit descriptor */ 153 HAL_CAP_TXSTATUSLEN = 78, /* Length of transmit status descriptor */ 154 HAL_CAP_RXSTATUSLEN = 79, /* Length of transmit status descriptor */ 155 HAL_CAP_RXFIFODEPTH = 80, /* Receive hardware FIFO depth */ 156 HAL_CAP_RXBUFSIZE = 81, /* Receive Buffer Length */ 157 HAL_CAP_NUM_MR_RETRIES = 82, /* limit on multirate retries */ 158 HAL_CAP_OL_PWRCTRL = 84, /* Open loop TX power control */ 159 160 HAL_CAP_BB_PANIC_WATCHDOG = 92, 161 162 HAL_CAP_HT20_SGI = 96, /* hardware supports HT20 short GI */ 163 164 HAL_CAP_LDPC = 99, 165 166 HAL_CAP_RXTSTAMP_PREC = 100, /* rx desc tstamp precision (bits) */ 167 168 HAL_CAP_PHYRESTART_CLR_WAR = 106, /* in some cases, clear phy restart to fix bb hang */ 169 HAL_CAP_ENTERPRISE_MODE = 107, /* Enterprise mode features */ 170 HAL_CAP_LDPCWAR = 108, 171 HAL_CAP_CHANNEL_SWITCH_TIME_USEC = 109, /* Channel change time, usec */ 172 HAL_CAP_ENABLE_APM = 110, /* APM enabled */ 173 HAL_CAP_PCIE_LCR_EXTSYNC_EN = 111, 174 HAL_CAP_PCIE_LCR_OFFSET = 112, 175 176 HAL_CAP_ENHANCED_DFS_SUPPORT = 117, /* hardware supports enhanced DFS */ 177 HAL_CAP_MCI = 118, 178 HAL_CAP_SMARTANTENNA = 119, 179 HAL_CAP_TRAFFIC_FAST_RECOVER = 120, 180 HAL_CAP_TX_DIVERSITY = 121, 181 HAL_CAP_CRDC = 122, 182 183 /* The following are private to the FreeBSD HAL (224 onward) */ 184 185 HAL_CAP_INTMIT = 229, /* interference mitigation */ 186 HAL_CAP_RXORN_FATAL = 230, /* HAL_INT_RXORN treated as fatal */ 187 HAL_CAP_BB_HANG = 235, /* can baseband hang */ 188 HAL_CAP_INTRMASK = 237, /* bitmask of supported interrupts */ 189 HAL_CAP_BSSIDMATCH = 238, /* hardware has disable bssid match */ 190 HAL_CAP_STREAMS = 239, /* how many 802.11n spatial streams are available */ 191 HAL_CAP_RXDESC_SELFLINK = 242, /* support a self-linked tail RX descriptor */ 192 HAL_CAP_LONG_RXDESC_TSF = 243, /* hardware supports 32bit TSF in RX descriptor */ 193 HAL_CAP_BB_READ_WAR = 244, /* baseband read WAR */ 194 HAL_CAP_SERIALISE_WAR = 245, /* serialise register access on PCI */ 195 HAL_CAP_ENFORCE_TXOP = 246, /* Enforce TXOP if supported */ 196 } HAL_CAPABILITY_TYPE; 197 198 /* 199 * "States" for setting the LED. These correspond to 200 * the possible 802.11 operational states and there may 201 * be a many-to-one mapping between these states and the 202 * actual hardware state for the LED's (i.e. the hardware 203 * may have fewer states). 204 */ 205 typedef enum { 206 HAL_LED_INIT = 0, 207 HAL_LED_SCAN = 1, 208 HAL_LED_AUTH = 2, 209 HAL_LED_ASSOC = 3, 210 HAL_LED_RUN = 4 211 } HAL_LED_STATE; 212 213 /* 214 * Transmit queue types/numbers. These are used to tag 215 * each transmit queue in the hardware and to identify a set 216 * of transmit queues for operations such as start/stop dma. 217 */ 218 typedef enum { 219 HAL_TX_QUEUE_INACTIVE = 0, /* queue is inactive/unused */ 220 HAL_TX_QUEUE_DATA = 1, /* data xmit q's */ 221 HAL_TX_QUEUE_BEACON = 2, /* beacon xmit q */ 222 HAL_TX_QUEUE_CAB = 3, /* "crap after beacon" xmit q */ 223 HAL_TX_QUEUE_UAPSD = 4, /* u-apsd power save xmit q */ 224 HAL_TX_QUEUE_PSPOLL = 5, /* power save poll xmit q */ 225 HAL_TX_QUEUE_CFEND = 6, 226 HAL_TX_QUEUE_PAPRD = 7, 227 } HAL_TX_QUEUE; 228 229 #define HAL_NUM_TX_QUEUES 10 /* max possible # of queues */ 230 231 /* 232 * Receive queue types. These are used to tag 233 * each transmit queue in the hardware and to identify a set 234 * of transmit queues for operations such as start/stop dma. 235 */ 236 typedef enum { 237 HAL_RX_QUEUE_HP = 0, /* high priority recv queue */ 238 HAL_RX_QUEUE_LP = 1, /* low priority recv queue */ 239 } HAL_RX_QUEUE; 240 241 #define HAL_NUM_RX_QUEUES 2 /* max possible # of queues */ 242 243 #define HAL_TXFIFO_DEPTH 8 /* transmit fifo depth */ 244 245 /* 246 * Transmit queue subtype. These map directly to 247 * WME Access Categories (except for UPSD). Refer 248 * to Table 5 of the WME spec. 249 */ 250 typedef enum { 251 HAL_WME_AC_BK = 0, /* background access category */ 252 HAL_WME_AC_BE = 1, /* best effort access category*/ 253 HAL_WME_AC_VI = 2, /* video access category */ 254 HAL_WME_AC_VO = 3, /* voice access category */ 255 HAL_WME_UPSD = 4, /* uplink power save */ 256 } HAL_TX_QUEUE_SUBTYPE; 257 258 /* 259 * Transmit queue flags that control various 260 * operational parameters. 261 */ 262 typedef enum { 263 /* 264 * Per queue interrupt enables. When set the associated 265 * interrupt may be delivered for packets sent through 266 * the queue. Without these enabled no interrupts will 267 * be delivered for transmits through the queue. 268 */ 269 HAL_TXQ_TXOKINT_ENABLE = 0x0001, /* enable TXOK interrupt */ 270 HAL_TXQ_TXERRINT_ENABLE = 0x0001, /* enable TXERR interrupt */ 271 HAL_TXQ_TXDESCINT_ENABLE = 0x0002, /* enable TXDESC interrupt */ 272 HAL_TXQ_TXEOLINT_ENABLE = 0x0004, /* enable TXEOL interrupt */ 273 HAL_TXQ_TXURNINT_ENABLE = 0x0008, /* enable TXURN interrupt */ 274 /* 275 * Enable hardware compression for packets sent through 276 * the queue. The compression buffer must be setup and 277 * packets must have a key entry marked in the tx descriptor. 278 */ 279 HAL_TXQ_COMPRESSION_ENABLE = 0x0010, /* enable h/w compression */ 280 /* 281 * Disable queue when veol is hit or ready time expires. 282 * By default the queue is disabled only on reaching the 283 * physical end of queue (i.e. a null link ptr in the 284 * descriptor chain). 285 */ 286 HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE = 0x0020, 287 /* 288 * Schedule frames on delivery of a DBA (DMA Beacon Alert) 289 * event. Frames will be transmitted only when this timer 290 * fires, e.g to transmit a beacon in ap or adhoc modes. 291 */ 292 HAL_TXQ_DBA_GATED = 0x0040, /* schedule based on DBA */ 293 /* 294 * Each transmit queue has a counter that is incremented 295 * each time the queue is enabled and decremented when 296 * the list of frames to transmit is traversed (or when 297 * the ready time for the queue expires). This counter 298 * must be non-zero for frames to be scheduled for 299 * transmission. The following controls disable bumping 300 * this counter under certain conditions. Typically this 301 * is used to gate frames based on the contents of another 302 * queue (e.g. CAB traffic may only follow a beacon frame). 303 * These are meaningful only when frames are scheduled 304 * with a non-ASAP policy (e.g. DBA-gated). 305 */ 306 HAL_TXQ_CBR_DIS_QEMPTY = 0x0080, /* disable on this q empty */ 307 HAL_TXQ_CBR_DIS_BEMPTY = 0x0100, /* disable on beacon q empty */ 308 309 /* 310 * Fragment burst backoff policy. Normally the no backoff 311 * is done after a successful transmission, the next fragment 312 * is sent at SIFS. If this flag is set backoff is done 313 * after each fragment, regardless whether it was ack'd or 314 * not, after the backoff count reaches zero a normal channel 315 * access procedure is done before the next transmit (i.e. 316 * wait AIFS instead of SIFS). 317 */ 318 HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE = 0x00800000, 319 /* 320 * Disable post-tx backoff following each frame. 321 */ 322 HAL_TXQ_BACKOFF_DISABLE = 0x00010000, /* disable post backoff */ 323 /* 324 * DCU arbiter lockout control. This controls how 325 * lower priority tx queues are handled with respect to 326 * to a specific queue when multiple queues have frames 327 * to send. No lockout means lower priority queues arbitrate 328 * concurrently with this queue. Intra-frame lockout 329 * means lower priority queues are locked out until the 330 * current frame transmits (e.g. including backoffs and bursting). 331 * Global lockout means nothing lower can arbitrary so 332 * long as there is traffic activity on this queue (frames, 333 * backoff, etc). 334 */ 335 HAL_TXQ_ARB_LOCKOUT_INTRA = 0x00020000, /* intra-frame lockout */ 336 HAL_TXQ_ARB_LOCKOUT_GLOBAL = 0x00040000, /* full lockout s */ 337 338 HAL_TXQ_IGNORE_VIRTCOL = 0x00080000, /* ignore virt collisions */ 339 HAL_TXQ_SEQNUM_INC_DIS = 0x00100000, /* disable seqnum increment */ 340 } HAL_TX_QUEUE_FLAGS; 341 342 typedef struct { 343 uint32_t tqi_ver; /* hal TXQ version */ 344 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* subtype if applicable */ 345 HAL_TX_QUEUE_FLAGS tqi_qflags; /* flags (see above) */ 346 uint32_t tqi_priority; /* (not used) */ 347 uint32_t tqi_aifs; /* aifs */ 348 uint32_t tqi_cwmin; /* cwMin */ 349 uint32_t tqi_cwmax; /* cwMax */ 350 uint16_t tqi_shretry; /* rts retry limit */ 351 uint16_t tqi_lgretry; /* long retry limit (not used)*/ 352 uint32_t tqi_cbrPeriod; /* CBR period (us) */ 353 uint32_t tqi_cbrOverflowLimit; /* threshold for CBROVF int */ 354 uint32_t tqi_burstTime; /* max burst duration (us) */ 355 uint32_t tqi_readyTime; /* frame schedule time (us) */ 356 uint32_t tqi_compBuf; /* comp buffer phys addr */ 357 } HAL_TXQ_INFO; 358 359 #define HAL_TQI_NONVAL 0xffff 360 361 /* token to use for aifs, cwmin, cwmax */ 362 #define HAL_TXQ_USEDEFAULT ((uint32_t) -1) 363 364 /* compression definitions */ 365 #define HAL_COMP_BUF_MAX_SIZE 9216 /* 9K */ 366 #define HAL_COMP_BUF_ALIGN_SIZE 512 367 368 /* 369 * Transmit packet types. This belongs in ah_desc.h, but 370 * is here so we can give a proper type to various parameters 371 * (and not require everyone include the file). 372 * 373 * NB: These values are intentionally assigned for 374 * direct use when setting up h/w descriptors. 375 */ 376 typedef enum { 377 HAL_PKT_TYPE_NORMAL = 0, 378 HAL_PKT_TYPE_ATIM = 1, 379 HAL_PKT_TYPE_PSPOLL = 2, 380 HAL_PKT_TYPE_BEACON = 3, 381 HAL_PKT_TYPE_PROBE_RESP = 4, 382 HAL_PKT_TYPE_CHIRP = 5, 383 HAL_PKT_TYPE_GRP_POLL = 6, 384 HAL_PKT_TYPE_AMPDU = 7, 385 } HAL_PKT_TYPE; 386 387 /* Rx Filter Frame Types */ 388 typedef enum { 389 /* 390 * These bits correspond to AR_RX_FILTER for all chips. 391 * Not all bits are supported by all chips. 392 */ 393 HAL_RX_FILTER_UCAST = 0x00000001, /* Allow unicast frames */ 394 HAL_RX_FILTER_MCAST = 0x00000002, /* Allow multicast frames */ 395 HAL_RX_FILTER_BCAST = 0x00000004, /* Allow broadcast frames */ 396 HAL_RX_FILTER_CONTROL = 0x00000008, /* Allow control frames */ 397 HAL_RX_FILTER_BEACON = 0x00000010, /* Allow beacon frames */ 398 HAL_RX_FILTER_PROM = 0x00000020, /* Promiscuous mode */ 399 HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */ 400 HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */ 401 HAL_RX_FILTER_COMPBAR = 0x00000400, /* Allow compressed BAR */ 402 HAL_RX_FILTER_COMP_BA = 0x00000800, /* Allow compressed blockack */ 403 HAL_RX_FILTER_PHYRADAR = 0x00002000, /* Allow phy radar errors */ 404 HAL_RX_FILTER_PSPOLL = 0x00004000, /* Allow PS-POLL frames */ 405 HAL_RX_FILTER_MCAST_BCAST_ALL = 0x00008000, 406 /* Allow all mcast/bcast frames */ 407 408 /* 409 * Magic RX filter flags that aren't targetting hardware bits 410 * but instead the HAL sets individual bits - eg PHYERR will result 411 * in OFDM/CCK timing error frames being received. 412 */ 413 HAL_RX_FILTER_BSSID = 0x40000000, /* Disable BSSID match */ 414 } HAL_RX_FILTER; 415 416 typedef enum { 417 HAL_PM_AWAKE = 0, 418 HAL_PM_FULL_SLEEP = 1, 419 HAL_PM_NETWORK_SLEEP = 2, 420 HAL_PM_UNDEFINED = 3 421 } HAL_POWER_MODE; 422 423 /* 424 * Enterprise mode flags 425 */ 426 #define AH_ENT_DUAL_BAND_DISABLE 0x00000001 427 #define AH_ENT_CHAIN2_DISABLE 0x00000002 428 #define AH_ENT_5MHZ_DISABLE 0x00000004 429 #define AH_ENT_10MHZ_DISABLE 0x00000008 430 #define AH_ENT_49GHZ_DISABLE 0x00000010 431 #define AH_ENT_LOOPBACK_DISABLE 0x00000020 432 #define AH_ENT_TPC_PERF_DISABLE 0x00000040 433 #define AH_ENT_MIN_PKT_SIZE_DISABLE 0x00000080 434 #define AH_ENT_SPECTRAL_PRECISION 0x00000300 435 #define AH_ENT_SPECTRAL_PRECISION_S 8 436 #define AH_ENT_RTSCTS_DELIM_WAR 0x00010000 437 438 #define AH_FIRST_DESC_NDELIMS 60 439 440 /* 441 * NOTE WELL: 442 * These are mapped to take advantage of the common locations for many of 443 * the bits on all of the currently supported MAC chips. This is to make 444 * the ISR as efficient as possible, while still abstracting HW differences. 445 * When new hardware breaks this commonality this enumerated type, as well 446 * as the HAL functions using it, must be modified. All values are directly 447 * mapped unless commented otherwise. 448 */ 449 typedef enum { 450 HAL_INT_RX = 0x00000001, /* Non-common mapping */ 451 HAL_INT_RXDESC = 0x00000002, /* Legacy mapping */ 452 HAL_INT_RXERR = 0x00000004, 453 HAL_INT_RXHP = 0x00000001, /* EDMA */ 454 HAL_INT_RXLP = 0x00000002, /* EDMA */ 455 HAL_INT_RXNOFRM = 0x00000008, 456 HAL_INT_RXEOL = 0x00000010, 457 HAL_INT_RXORN = 0x00000020, 458 HAL_INT_TX = 0x00000040, /* Non-common mapping */ 459 HAL_INT_TXDESC = 0x00000080, 460 HAL_INT_TIM_TIMER= 0x00000100, 461 HAL_INT_MCI = 0x00000200, 462 HAL_INT_BBPANIC = 0x00000400, 463 HAL_INT_TXURN = 0x00000800, 464 HAL_INT_MIB = 0x00001000, 465 HAL_INT_RXPHY = 0x00004000, 466 HAL_INT_RXKCM = 0x00008000, 467 HAL_INT_SWBA = 0x00010000, 468 HAL_INT_BRSSI = 0x00020000, 469 HAL_INT_BMISS = 0x00040000, 470 HAL_INT_BNR = 0x00100000, 471 HAL_INT_TIM = 0x00200000, /* Non-common mapping */ 472 HAL_INT_DTIM = 0x00400000, /* Non-common mapping */ 473 HAL_INT_DTIMSYNC= 0x00800000, /* Non-common mapping */ 474 HAL_INT_GPIO = 0x01000000, 475 HAL_INT_CABEND = 0x02000000, /* Non-common mapping */ 476 HAL_INT_TSFOOR = 0x04000000, /* Non-common mapping */ 477 HAL_INT_TBTT = 0x08000000, /* Non-common mapping */ 478 /* Atheros ref driver has a generic timer interrupt now..*/ 479 HAL_INT_GENTIMER = 0x08000000, /* Non-common mapping */ 480 HAL_INT_CST = 0x10000000, /* Non-common mapping */ 481 HAL_INT_GTT = 0x20000000, /* Non-common mapping */ 482 HAL_INT_FATAL = 0x40000000, /* Non-common mapping */ 483 #define HAL_INT_GLOBAL 0x80000000 /* Set/clear IER */ 484 HAL_INT_BMISC = HAL_INT_TIM 485 | HAL_INT_DTIM 486 | HAL_INT_DTIMSYNC 487 | HAL_INT_CABEND 488 | HAL_INT_TBTT, 489 490 /* Interrupt bits that map directly to ISR/IMR bits */ 491 HAL_INT_COMMON = HAL_INT_RXNOFRM 492 | HAL_INT_RXDESC 493 | HAL_INT_RXEOL 494 | HAL_INT_RXORN 495 | HAL_INT_TXDESC 496 | HAL_INT_TXURN 497 | HAL_INT_MIB 498 | HAL_INT_RXPHY 499 | HAL_INT_RXKCM 500 | HAL_INT_SWBA 501 | HAL_INT_BMISS 502 | HAL_INT_BRSSI 503 | HAL_INT_BNR 504 | HAL_INT_GPIO, 505 } HAL_INT; 506 507 /* 508 * MSI vector assignments 509 */ 510 typedef enum { 511 HAL_MSIVEC_MISC = 0, 512 HAL_MSIVEC_TX = 1, 513 HAL_MSIVEC_RXLP = 2, 514 HAL_MSIVEC_RXHP = 3, 515 } HAL_MSIVEC; 516 517 typedef enum { 518 HAL_INT_LINE = 0, 519 HAL_INT_MSI = 1, 520 } HAL_INT_TYPE; 521 522 /* For interrupt mitigation registers */ 523 typedef enum { 524 HAL_INT_RX_FIRSTPKT=0, 525 HAL_INT_RX_LASTPKT, 526 HAL_INT_TX_FIRSTPKT, 527 HAL_INT_TX_LASTPKT, 528 HAL_INT_THRESHOLD 529 } HAL_INT_MITIGATION; 530 531 /* XXX this is duplicate information! */ 532 typedef struct { 533 u_int32_t cyclecnt_diff; /* delta cycle count */ 534 u_int32_t rxclr_cnt; /* rx clear count */ 535 u_int32_t txframecnt_diff; /* delta tx frame count */ 536 u_int32_t rxframecnt_diff; /* delta rx frame count */ 537 u_int32_t listen_time; /* listen time in msec - time for which ch is free */ 538 u_int32_t ofdmphyerr_cnt; /* OFDM err count since last reset */ 539 u_int32_t cckphyerr_cnt; /* CCK err count since last reset */ 540 u_int32_t ofdmphyerrcnt_diff; /* delta OFDM Phy Error Count */ 541 HAL_BOOL valid; /* if the stats are valid*/ 542 } HAL_ANISTATS; 543 544 typedef struct { 545 u_int8_t txctl_offset; 546 u_int8_t txctl_numwords; 547 u_int8_t txstatus_offset; 548 u_int8_t txstatus_numwords; 549 550 u_int8_t rxctl_offset; 551 u_int8_t rxctl_numwords; 552 u_int8_t rxstatus_offset; 553 u_int8_t rxstatus_numwords; 554 555 u_int8_t macRevision; 556 } HAL_DESC_INFO; 557 558 typedef enum { 559 HAL_GPIO_OUTPUT_MUX_AS_OUTPUT = 0, 560 HAL_GPIO_OUTPUT_MUX_PCIE_ATTENTION_LED = 1, 561 HAL_GPIO_OUTPUT_MUX_PCIE_POWER_LED = 2, 562 HAL_GPIO_OUTPUT_MUX_MAC_NETWORK_LED = 3, 563 HAL_GPIO_OUTPUT_MUX_MAC_POWER_LED = 4, 564 HAL_GPIO_OUTPUT_MUX_AS_WLAN_ACTIVE = 5, 565 HAL_GPIO_OUTPUT_MUX_AS_TX_FRAME = 6 566 } HAL_GPIO_MUX_TYPE; 567 568 typedef enum { 569 HAL_GPIO_INTR_LOW = 0, 570 HAL_GPIO_INTR_HIGH = 1, 571 HAL_GPIO_INTR_DISABLE = 2 572 } HAL_GPIO_INTR_TYPE; 573 574 typedef struct halCounters { 575 u_int32_t tx_frame_count; 576 u_int32_t rx_frame_count; 577 u_int32_t rx_clear_count; 578 u_int32_t cycle_count; 579 u_int8_t is_rx_active; // true (1) or false (0) 580 u_int8_t is_tx_active; // true (1) or false (0) 581 } HAL_COUNTERS; 582 583 typedef enum { 584 HAL_RFGAIN_INACTIVE = 0, 585 HAL_RFGAIN_READ_REQUESTED = 1, 586 HAL_RFGAIN_NEED_CHANGE = 2 587 } HAL_RFGAIN; 588 589 typedef uint16_t HAL_CTRY_CODE; /* country code */ 590 typedef uint16_t HAL_REG_DOMAIN; /* regulatory domain code */ 591 592 #define HAL_ANTENNA_MIN_MODE 0 593 #define HAL_ANTENNA_FIXED_A 1 594 #define HAL_ANTENNA_FIXED_B 2 595 #define HAL_ANTENNA_MAX_MODE 3 596 597 typedef struct { 598 uint32_t ackrcv_bad; 599 uint32_t rts_bad; 600 uint32_t rts_good; 601 uint32_t fcs_bad; 602 uint32_t beacons; 603 } HAL_MIB_STATS; 604 605 /* 606 * These bits represent what's in ah_currentRDext. 607 */ 608 typedef enum { 609 REG_EXT_FCC_MIDBAND = 0, 610 REG_EXT_JAPAN_MIDBAND = 1, 611 REG_EXT_FCC_DFS_HT40 = 2, 612 REG_EXT_JAPAN_NONDFS_HT40 = 3, 613 REG_EXT_JAPAN_DFS_HT40 = 4 614 } REG_EXT_BITMAP; 615 616 enum { 617 HAL_MODE_11A = 0x001, /* 11a channels */ 618 HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */ 619 HAL_MODE_11B = 0x004, /* 11b channels */ 620 HAL_MODE_PUREG = 0x008, /* 11g channels (OFDM only) */ 621 #ifdef notdef 622 HAL_MODE_11G = 0x010, /* 11g channels (OFDM/CCK) */ 623 #else 624 HAL_MODE_11G = 0x008, /* XXX historical */ 625 #endif 626 HAL_MODE_108G = 0x020, /* 11g+Turbo channels */ 627 HAL_MODE_108A = 0x040, /* 11a+Turbo channels */ 628 HAL_MODE_11A_HALF_RATE = 0x200, /* 11a half width channels */ 629 HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11a quarter width channels */ 630 HAL_MODE_11G_HALF_RATE = 0x800, /* 11g half width channels */ 631 HAL_MODE_11G_QUARTER_RATE = 0x1000, /* 11g quarter width channels */ 632 HAL_MODE_11NG_HT20 = 0x008000, 633 HAL_MODE_11NA_HT20 = 0x010000, 634 HAL_MODE_11NG_HT40PLUS = 0x020000, 635 HAL_MODE_11NG_HT40MINUS = 0x040000, 636 HAL_MODE_11NA_HT40PLUS = 0x080000, 637 HAL_MODE_11NA_HT40MINUS = 0x100000, 638 HAL_MODE_ALL = 0xffffff 639 }; 640 641 typedef struct { 642 int rateCount; /* NB: for proper padding */ 643 uint8_t rateCodeToIndex[256]; /* back mapping */ 644 struct { 645 uint8_t valid; /* valid for rate control use */ 646 uint8_t phy; /* CCK/OFDM/XR */ 647 uint32_t rateKbps; /* transfer rate in kbs */ 648 uint8_t rateCode; /* rate for h/w descriptors */ 649 uint8_t shortPreamble; /* mask for enabling short 650 * preamble in CCK rate code */ 651 uint8_t dot11Rate; /* value for supported rates 652 * info element of MLME */ 653 uint8_t controlRate; /* index of next lower basic 654 * rate; used for dur. calcs */ 655 uint16_t lpAckDuration; /* long preamble ACK duration */ 656 uint16_t spAckDuration; /* short preamble ACK duration*/ 657 } info[64]; 658 } HAL_RATE_TABLE; 659 660 typedef struct { 661 u_int rs_count; /* number of valid entries */ 662 uint8_t rs_rates[64]; /* rates */ 663 } HAL_RATE_SET; 664 665 /* 666 * 802.11n specific structures and enums 667 */ 668 typedef enum { 669 HAL_CHAINTYPE_TX = 1, /* Tx chain type */ 670 HAL_CHAINTYPE_RX = 2, /* RX chain type */ 671 } HAL_CHAIN_TYPE; 672 673 typedef struct { 674 u_int Tries; 675 u_int Rate; /* hardware rate code */ 676 u_int RateIndex; /* rate series table index */ 677 u_int PktDuration; 678 u_int ChSel; 679 u_int RateFlags; 680 #define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */ 681 #define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */ 682 #define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */ 683 #define HAL_RATESERIES_STBC 0x0008 /* use STBC for series */ 684 u_int tx_power_cap; /* in 1/2 dBm units XXX TODO */ 685 } HAL_11N_RATE_SERIES; 686 687 typedef enum { 688 HAL_HT_MACMODE_20 = 0, /* 20 MHz operation */ 689 HAL_HT_MACMODE_2040 = 1, /* 20/40 MHz operation */ 690 } HAL_HT_MACMODE; 691 692 typedef enum { 693 HAL_HT_PHYMODE_20 = 0, /* 20 MHz operation */ 694 HAL_HT_PHYMODE_2040 = 1, /* 20/40 MHz operation */ 695 } HAL_HT_PHYMODE; 696 697 typedef enum { 698 HAL_HT_EXTPROTSPACING_20 = 0, /* 20 MHz spacing */ 699 HAL_HT_EXTPROTSPACING_25 = 1, /* 25 MHz spacing */ 700 } HAL_HT_EXTPROTSPACING; 701 702 703 typedef enum { 704 HAL_RX_CLEAR_CTL_LOW = 0x1, /* force control channel to appear busy */ 705 HAL_RX_CLEAR_EXT_LOW = 0x2, /* force extension channel to appear busy */ 706 } HAL_HT_RXCLEAR; 707 708 typedef enum { 709 HAL_FREQ_BAND_5GHZ = 0, 710 HAL_FREQ_BAND_2GHZ = 1, 711 } HAL_FREQ_BAND; 712 713 /* 714 * Antenna switch control. By default antenna selection 715 * enables multiple (2) antenna use. To force use of the 716 * A or B antenna only specify a fixed setting. Fixing 717 * the antenna will also disable any diversity support. 718 */ 719 typedef enum { 720 HAL_ANT_VARIABLE = 0, /* variable by programming */ 721 HAL_ANT_FIXED_A = 1, /* fixed antenna A */ 722 HAL_ANT_FIXED_B = 2, /* fixed antenna B */ 723 } HAL_ANT_SETTING; 724 725 typedef enum { 726 HAL_M_STA = 1, /* infrastructure station */ 727 HAL_M_IBSS = 0, /* IBSS (adhoc) station */ 728 HAL_M_HOSTAP = 6, /* Software Access Point */ 729 HAL_M_MONITOR = 8 /* Monitor mode */ 730 } HAL_OPMODE; 731 732 typedef struct { 733 uint8_t kv_type; /* one of HAL_CIPHER */ 734 uint8_t kv_apsd; /* Mask for APSD enabled ACs */ 735 uint16_t kv_len; /* length in bits */ 736 uint8_t kv_val[16]; /* enough for 128-bit keys */ 737 uint8_t kv_mic[8]; /* TKIP MIC key */ 738 uint8_t kv_txmic[8]; /* TKIP TX MIC key (optional) */ 739 } HAL_KEYVAL; 740 741 /* 742 * This is the TX descriptor field which marks the key padding requirement. 743 * The naming is unfortunately unclear. 744 */ 745 #define AH_KEYTYPE_MASK 0x0F 746 typedef enum { 747 HAL_KEY_TYPE_CLEAR, 748 HAL_KEY_TYPE_WEP, 749 HAL_KEY_TYPE_AES, 750 HAL_KEY_TYPE_TKIP, 751 } HAL_KEY_TYPE; 752 753 typedef enum { 754 HAL_CIPHER_WEP = 0, 755 HAL_CIPHER_AES_OCB = 1, 756 HAL_CIPHER_AES_CCM = 2, 757 HAL_CIPHER_CKIP = 3, 758 HAL_CIPHER_TKIP = 4, 759 HAL_CIPHER_CLR = 5, /* no encryption */ 760 761 HAL_CIPHER_MIC = 127 /* TKIP-MIC, not a cipher */ 762 } HAL_CIPHER; 763 764 enum { 765 HAL_SLOT_TIME_6 = 6, /* NB: for turbo mode */ 766 HAL_SLOT_TIME_9 = 9, 767 HAL_SLOT_TIME_20 = 20, 768 }; 769 770 /* 771 * Per-station beacon timer state. Note that the specified 772 * beacon interval (given in TU's) can also include flags 773 * to force a TSF reset and to enable the beacon xmit logic. 774 * If bs_cfpmaxduration is non-zero the hardware is setup to 775 * coexist with a PCF-capable AP. 776 */ 777 typedef struct { 778 uint32_t bs_nexttbtt; /* next beacon in TU */ 779 uint32_t bs_nextdtim; /* next DTIM in TU */ 780 uint32_t bs_intval; /* beacon interval+flags */ 781 /* 782 * HAL_BEACON_PERIOD, HAL_BEACON_ENA and HAL_BEACON_RESET_TSF 783 * are all 1:1 correspondances with the pre-11n chip AR_BEACON 784 * register. 785 */ 786 #define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */ 787 #define HAL_BEACON_PERIOD_TU8 0x0007ffff /* beacon interval, tu/8 */ 788 #define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */ 789 #define HAL_BEACON_RESET_TSF 0x01000000 /* clear TSF */ 790 #define HAL_TSFOOR_THRESHOLD 0x00004240 /* TSF OOR thresh (16k uS) */ 791 uint32_t bs_dtimperiod; 792 uint16_t bs_cfpperiod; /* CFP period in TU */ 793 uint16_t bs_cfpmaxduration; /* max CFP duration in TU */ 794 uint32_t bs_cfpnext; /* next CFP in TU */ 795 uint16_t bs_timoffset; /* byte offset to TIM bitmap */ 796 uint16_t bs_bmissthreshold; /* beacon miss threshold */ 797 uint32_t bs_sleepduration; /* max sleep duration */ 798 uint32_t bs_tsfoor_threshold; /* TSF out of range threshold */ 799 } HAL_BEACON_STATE; 800 801 /* 802 * Like HAL_BEACON_STATE but for non-station mode setup. 803 * NB: see above flag definitions for bt_intval. 804 */ 805 typedef struct { 806 uint32_t bt_intval; /* beacon interval+flags */ 807 uint32_t bt_nexttbtt; /* next beacon in TU */ 808 uint32_t bt_nextatim; /* next ATIM in TU */ 809 uint32_t bt_nextdba; /* next DBA in 1/8th TU */ 810 uint32_t bt_nextswba; /* next SWBA in 1/8th TU */ 811 uint32_t bt_flags; /* timer enables */ 812 #define HAL_BEACON_TBTT_EN 0x00000001 813 #define HAL_BEACON_DBA_EN 0x00000002 814 #define HAL_BEACON_SWBA_EN 0x00000004 815 } HAL_BEACON_TIMERS; 816 817 /* 818 * Per-node statistics maintained by the driver for use in 819 * optimizing signal quality and other operational aspects. 820 */ 821 typedef struct { 822 uint32_t ns_avgbrssi; /* average beacon rssi */ 823 uint32_t ns_avgrssi; /* average data rssi */ 824 uint32_t ns_avgtxrssi; /* average tx rssi */ 825 } HAL_NODE_STATS; 826 827 #define HAL_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */ 828 829 830 struct ath_desc; 831 struct ath_tx_status; 832 struct ath_rx_status; 833 struct ieee80211_channel; 834 835 /* 836 * This is a channel survey sample entry. 837 * 838 * The AR5212 ANI routines fill these samples. The ANI code then uses it 839 * when calculating listen time; it is also exported via a diagnostic 840 * API. 841 */ 842 typedef struct { 843 uint32_t seq_num; 844 uint32_t tx_busy; 845 uint32_t rx_busy; 846 uint32_t chan_busy; 847 uint32_t ext_chan_busy; 848 uint32_t cycle_count; 849 /* XXX TODO */ 850 uint32_t ofdm_phyerr_count; 851 uint32_t cck_phyerr_count; 852 } HAL_SURVEY_SAMPLE; 853 854 /* 855 * This provides 3.2 seconds of sample space given an 856 * ANI time of 1/10th of a second. This may not be enough! 857 */ 858 #define CHANNEL_SURVEY_SAMPLE_COUNT 32 859 860 typedef struct { 861 HAL_SURVEY_SAMPLE samples[CHANNEL_SURVEY_SAMPLE_COUNT]; 862 uint32_t cur_sample; /* current sample in sequence */ 863 uint32_t cur_seq; /* current sequence number */ 864 } HAL_CHANNEL_SURVEY; 865 866 /* 867 * ANI commands. 868 * 869 * These are used both internally and externally via the diagnostic 870 * API. 871 * 872 * Note that this is NOT the ANI commands being used via the INTMIT 873 * capability - that has a different mapping for some reason. 874 */ 875 typedef enum { 876 HAL_ANI_PRESENT = 0, /* is ANI support present */ 877 HAL_ANI_NOISE_IMMUNITY_LEVEL = 1, /* set level */ 878 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION = 2, /* enable/disable */ 879 HAL_ANI_CCK_WEAK_SIGNAL_THR = 3, /* enable/disable */ 880 HAL_ANI_FIRSTEP_LEVEL = 4, /* set level */ 881 HAL_ANI_SPUR_IMMUNITY_LEVEL = 5, /* set level */ 882 HAL_ANI_MODE = 6, /* 0 => manual, 1 => auto (XXX do not change) */ 883 HAL_ANI_PHYERR_RESET = 7, /* reset phy error stats */ 884 HAL_ANI_MRC_CCK = 8, 885 } HAL_ANI_CMD; 886 887 #define HAL_ANI_ALL 0xffffffff 888 889 /* 890 * This is the layout of the ANI INTMIT capability. 891 * 892 * Notice that the command values differ to HAL_ANI_CMD. 893 */ 894 typedef enum { 895 HAL_CAP_INTMIT_PRESENT = 0, 896 HAL_CAP_INTMIT_ENABLE = 1, 897 HAL_CAP_INTMIT_NOISE_IMMUNITY_LEVEL = 2, 898 HAL_CAP_INTMIT_OFDM_WEAK_SIGNAL_LEVEL = 3, 899 HAL_CAP_INTMIT_CCK_WEAK_SIGNAL_THR = 4, 900 HAL_CAP_INTMIT_FIRSTEP_LEVEL = 5, 901 HAL_CAP_INTMIT_SPUR_IMMUNITY_LEVEL = 6 902 } HAL_CAP_INTMIT_CMD; 903 904 typedef struct { 905 int32_t pe_firpwr; /* FIR pwr out threshold */ 906 int32_t pe_rrssi; /* Radar rssi thresh */ 907 int32_t pe_height; /* Pulse height thresh */ 908 int32_t pe_prssi; /* Pulse rssi thresh */ 909 int32_t pe_inband; /* Inband thresh */ 910 911 /* The following params are only for AR5413 and later */ 912 u_int32_t pe_relpwr; /* Relative power threshold in 0.5dB steps */ 913 u_int32_t pe_relstep; /* Pulse Relative step threshold in 0.5dB steps */ 914 u_int32_t pe_maxlen; /* Max length of radar sign in 0.8us units */ 915 int32_t pe_usefir128; /* Use the average in-band power measured over 128 cycles */ 916 int32_t pe_blockradar; /* 917 * Enable to block radar check if pkt detect is done via OFDM 918 * weak signal detect or pkt is detected immediately after tx 919 * to rx transition 920 */ 921 int32_t pe_enmaxrssi; /* 922 * Enable to use the max rssi instead of the last rssi during 923 * fine gain changes for radar detection 924 */ 925 int32_t pe_extchannel; /* Enable DFS on ext channel */ 926 int32_t pe_enabled; /* Whether radar detection is enabled */ 927 int32_t pe_enrelpwr; 928 int32_t pe_en_relstep_check; 929 } HAL_PHYERR_PARAM; 930 931 #define HAL_PHYERR_PARAM_NOVAL 65535 932 933 /* 934 * DFS operating mode flags. 935 */ 936 typedef enum { 937 HAL_DFS_UNINIT_DOMAIN = 0, /* Uninitialized dfs domain */ 938 HAL_DFS_FCC_DOMAIN = 1, /* FCC3 dfs domain */ 939 HAL_DFS_ETSI_DOMAIN = 2, /* ETSI dfs domain */ 940 HAL_DFS_MKK4_DOMAIN = 3, /* Japan dfs domain */ 941 } HAL_DFS_DOMAIN; 942 943 944 /* 945 * MFP decryption options for initializing the MAC. 946 */ 947 typedef enum { 948 HAL_MFP_QOSDATA = 0, /* Decrypt MFP frames like QoS data frames. All chips before Merlin. */ 949 HAL_MFP_PASSTHRU, /* Don't decrypt MFP frames at all. Passthrough */ 950 HAL_MFP_HW_CRYPTO /* hardware decryption enabled. Merlin can do it. */ 951 } HAL_MFP_OPT_T; 952 953 /* LNA config supported */ 954 typedef enum { 955 HAL_ANT_DIV_COMB_LNA1_MINUS_LNA2 = 0, 956 HAL_ANT_DIV_COMB_LNA2 = 1, 957 HAL_ANT_DIV_COMB_LNA1 = 2, 958 HAL_ANT_DIV_COMB_LNA1_PLUS_LNA2 = 3, 959 } HAL_ANT_DIV_COMB_LNA_CONF; 960 961 typedef struct { 962 u_int8_t main_lna_conf; 963 u_int8_t alt_lna_conf; 964 u_int8_t fast_div_bias; 965 u_int8_t main_gaintb; 966 u_int8_t alt_gaintb; 967 u_int8_t antdiv_configgroup; 968 int8_t lna1_lna2_delta; 969 } HAL_ANT_COMB_CONFIG; 970 971 #define DEFAULT_ANTDIV_CONFIG_GROUP 0x00 972 #define HAL_ANTDIV_CONFIG_GROUP_1 0x01 973 #define HAL_ANTDIV_CONFIG_GROUP_2 0x02 974 #define HAL_ANTDIV_CONFIG_GROUP_3 0x03 975 976 /* 977 * Flag for setting QUIET period 978 */ 979 typedef enum { 980 HAL_QUIET_DISABLE = 0x0, 981 HAL_QUIET_ENABLE = 0x1, 982 HAL_QUIET_ADD_CURRENT_TSF = 0x2, /* add current TSF to next_start offset */ 983 HAL_QUIET_ADD_SWBA_RESP_TIME = 0x4, /* add beacon response time to next_start offset */ 984 } HAL_QUIET_FLAG; 985 986 #define HAL_DFS_EVENT_PRICH 0x0000001 987 #define HAL_DFS_EVENT_EXTCH 0x0000002 988 #define HAL_DFS_EVENT_EXTEARLY 0x0000004 989 #define HAL_DFS_EVENT_ISDC 0x0000008 990 991 struct hal_dfs_event { 992 uint64_t re_full_ts; /* 64-bit full timestamp from interrupt time */ 993 uint32_t re_ts; /* Original 15 bit recv timestamp */ 994 uint8_t re_rssi; /* rssi of radar event */ 995 uint8_t re_dur; /* duration of radar pulse */ 996 uint32_t re_flags; /* Flags (see above) */ 997 }; 998 typedef struct hal_dfs_event HAL_DFS_EVENT; 999 1000 /* 1001 * Generic Timer domain 1002 */ 1003 typedef enum { 1004 HAL_GEN_TIMER_TSF = 0, 1005 HAL_GEN_TIMER_TSF2, 1006 HAL_GEN_TIMER_TSF_ANY 1007 } HAL_GEN_TIMER_DOMAIN; 1008 1009 typedef enum { 1010 HAL_RESET_NONE = 0x0, 1011 HAL_RESET_BBPANIC = 0x1, 1012 } HAL_RESET_TYPE; 1013 1014 /* 1015 * BT Co-existence definitions 1016 */ 1017 typedef enum { 1018 HAL_BT_MODULE_CSR_BC4 = 0, /* CSR BlueCore v4 */ 1019 HAL_BT_MODULE_JANUS = 1, /* Kite + Valkyrie combo */ 1020 HAL_BT_MODULE_HELIUS = 2, /* Kiwi + Valkyrie combo */ 1021 HAL_MAX_BT_MODULES 1022 } HAL_BT_MODULE; 1023 1024 typedef struct { 1025 HAL_BT_MODULE bt_module; 1026 u_int8_t bt_coex_config; 1027 u_int8_t bt_gpio_bt_active; 1028 u_int8_t bt_gpio_bt_priority; 1029 u_int8_t bt_gpio_wlan_active; 1030 u_int8_t bt_active_polarity; 1031 HAL_BOOL bt_single_ant; 1032 u_int8_t bt_dutyCycle; 1033 u_int8_t bt_isolation; 1034 u_int8_t bt_period; 1035 } HAL_BT_COEX_INFO; 1036 1037 typedef enum { 1038 HAL_BT_COEX_MODE_LEGACY = 0, /* legacy rx_clear mode */ 1039 HAL_BT_COEX_MODE_UNSLOTTED = 1, /* untimed/unslotted mode */ 1040 HAL_BT_COEX_MODE_SLOTTED = 2, /* slotted mode */ 1041 HAL_BT_COEX_MODE_DISALBED = 3, /* coexistence disabled */ 1042 } HAL_BT_COEX_MODE; 1043 1044 typedef enum { 1045 HAL_BT_COEX_CFG_NONE, /* No bt coex enabled */ 1046 HAL_BT_COEX_CFG_2WIRE_2CH, /* 2-wire with 2 chains */ 1047 HAL_BT_COEX_CFG_2WIRE_CH1, /* 2-wire with ch1 */ 1048 HAL_BT_COEX_CFG_2WIRE_CH0, /* 2-wire with ch0 */ 1049 HAL_BT_COEX_CFG_3WIRE, /* 3-wire */ 1050 HAL_BT_COEX_CFG_MCI /* MCI */ 1051 } HAL_BT_COEX_CFG; 1052 1053 typedef enum { 1054 HAL_BT_COEX_SET_ACK_PWR = 0, /* Change ACK power setting */ 1055 HAL_BT_COEX_LOWER_TX_PWR, /* Change transmit power */ 1056 HAL_BT_COEX_ANTENNA_DIVERSITY, /* Enable RX diversity for Kite */ 1057 } HAL_BT_COEX_SET_PARAMETER; 1058 1059 #define HAL_BT_COEX_FLAG_LOW_ACK_PWR 0x00000001 1060 #define HAL_BT_COEX_FLAG_LOWER_TX_PWR 0x00000002 1061 /* Check Rx Diversity is allowed */ 1062 #define HAL_BT_COEX_FLAG_ANT_DIV_ALLOW 0x00000004 1063 /* Check Diversity is on or off */ 1064 #define HAL_BT_COEX_FLAG_ANT_DIV_ENABLE 0x00000008 1065 1066 #define HAL_BT_COEX_ANTDIV_CONTROL1_ENABLE 0x0b 1067 /* main: LNA1, alt: LNA2 */ 1068 #define HAL_BT_COEX_ANTDIV_CONTROL2_ENABLE 0x09 1069 #define HAL_BT_COEX_ANTDIV_CONTROL1_FIXED_A 0x04 1070 #define HAL_BT_COEX_ANTDIV_CONTROL2_FIXED_A 0x09 1071 #define HAL_BT_COEX_ANTDIV_CONTROL1_FIXED_B 0x02 1072 #define HAL_BT_COEX_ANTDIV_CONTROL2_FIXED_B 0x06 1073 1074 #define HAL_BT_COEX_ISOLATION_FOR_NO_COEX 30 1075 1076 #define HAL_BT_COEX_ANT_DIV_SWITCH_COM 0x66666666 1077 1078 #define HAL_BT_COEX_HELIUS_CHAINMASK 0x02 1079 1080 #define HAL_BT_COEX_LOW_ACK_POWER 0x0 1081 #define HAL_BT_COEX_HIGH_ACK_POWER 0x3f3f3f 1082 1083 typedef enum { 1084 HAL_BT_COEX_NO_STOMP = 0, 1085 HAL_BT_COEX_STOMP_ALL, 1086 HAL_BT_COEX_STOMP_LOW, 1087 HAL_BT_COEX_STOMP_NONE, 1088 HAL_BT_COEX_STOMP_ALL_FORCE, 1089 HAL_BT_COEX_STOMP_LOW_FORCE, 1090 } HAL_BT_COEX_STOMP_TYPE; 1091 1092 typedef struct { 1093 /* extend rx_clear after tx/rx to protect the burst (in usec). */ 1094 u_int8_t bt_time_extend; 1095 1096 /* 1097 * extend rx_clear as long as txsm is 1098 * transmitting or waiting for ack. 1099 */ 1100 HAL_BOOL bt_txstate_extend; 1101 1102 /* 1103 * extend rx_clear so that when tx_frame 1104 * is asserted, rx_clear will drop. 1105 */ 1106 HAL_BOOL bt_txframe_extend; 1107 1108 /* 1109 * coexistence mode 1110 */ 1111 HAL_BT_COEX_MODE bt_mode; 1112 1113 /* 1114 * treat BT high priority traffic as 1115 * a quiet collision 1116 */ 1117 HAL_BOOL bt_quiet_collision; 1118 1119 /* 1120 * invert rx_clear as WLAN_ACTIVE 1121 */ 1122 HAL_BOOL bt_rxclear_polarity; 1123 1124 /* 1125 * slotted mode only. indicate the time in usec 1126 * from the rising edge of BT_ACTIVE to the time 1127 * BT_PRIORITY can be sampled to indicate priority. 1128 */ 1129 u_int8_t bt_priority_time; 1130 1131 /* 1132 * slotted mode only. indicate the time in usec 1133 * from the rising edge of BT_ACTIVE to the time 1134 * BT_PRIORITY can be sampled to indicate tx/rx and 1135 * BT_FREQ is sampled. 1136 */ 1137 u_int8_t bt_first_slot_time; 1138 1139 /* 1140 * slotted mode only. rx_clear and bt_ant decision 1141 * will be held the entire time that BT_ACTIVE is asserted, 1142 * otherwise the decision is made before every slot boundry. 1143 */ 1144 HAL_BOOL bt_hold_rxclear; 1145 } HAL_BT_COEX_CONFIG; 1146 1147 struct hal_bb_panic_info { 1148 u_int32_t status; 1149 u_int32_t tsf; 1150 u_int32_t phy_panic_wd_ctl1; 1151 u_int32_t phy_panic_wd_ctl2; 1152 u_int32_t phy_gen_ctrl; 1153 u_int32_t rxc_pcnt; 1154 u_int32_t rxf_pcnt; 1155 u_int32_t txf_pcnt; 1156 u_int32_t cycles; 1157 u_int32_t wd; 1158 u_int32_t det; 1159 u_int32_t rdar; 1160 u_int32_t r_odfm; 1161 u_int32_t r_cck; 1162 u_int32_t t_odfm; 1163 u_int32_t t_cck; 1164 u_int32_t agc; 1165 u_int32_t src; 1166 }; 1167 1168 /* Serialize Register Access Mode */ 1169 typedef enum { 1170 SER_REG_MODE_OFF = 0, 1171 SER_REG_MODE_ON = 1, 1172 SER_REG_MODE_AUTO = 2, 1173 } SER_REG_MODE; 1174 1175 typedef struct 1176 { 1177 int ah_debug; /* only used if AH_DEBUG is defined */ 1178 int ah_ar5416_biasadj; /* enable AR2133 radio specific bias fiddling */ 1179 1180 /* NB: these are deprecated; they exist for now for compatibility */ 1181 int ah_dma_beacon_response_time;/* in TU's */ 1182 int ah_sw_beacon_response_time; /* in TU's */ 1183 int ah_additional_swba_backoff; /* in TU's */ 1184 int ah_force_full_reset; /* force full chip reset rather then warm reset */ 1185 int ah_serialise_reg_war; /* force serialisation of register IO */ 1186 1187 /* XXX these don't belong here, they're just for the ar9300 HAL port effort */ 1188 int ath_hal_desc_tpc; /* Per-packet TPC */ 1189 int ath_hal_sta_update_tx_pwr_enable; /* GreenTX */ 1190 int ath_hal_sta_update_tx_pwr_enable_S1; /* GreenTX */ 1191 int ath_hal_sta_update_tx_pwr_enable_S2; /* GreenTX */ 1192 int ath_hal_sta_update_tx_pwr_enable_S3; /* GreenTX */ 1193 1194 /* I'm not sure what the default values for these should be */ 1195 int ath_hal_pll_pwr_save; 1196 int ath_hal_pcie_power_save_enable; 1197 int ath_hal_intr_mitigation_rx; 1198 int ath_hal_intr_mitigation_tx; 1199 1200 int ath_hal_pcie_clock_req; 1201 #define AR_PCIE_PLL_PWRSAVE_CONTROL (1<<0) 1202 #define AR_PCIE_PLL_PWRSAVE_ON_D3 (1<<1) 1203 #define AR_PCIE_PLL_PWRSAVE_ON_D0 (1<<2) 1204 1205 int ath_hal_pcie_waen; 1206 int ath_hal_pcie_ser_des_write; 1207 1208 /* these are important for correct AR9300 behaviour */ 1209 int ath_hal_ht_enable; /* needs to be enabled for AR9300 HT */ 1210 int ath_hal_diversity_control; 1211 int ath_hal_antenna_switch_swap; 1212 int ath_hal_ext_lna_ctl_gpio; 1213 int ath_hal_spur_mode; 1214 int ath_hal_6mb_ack; /* should set this to 1 for 11a/11na? */ 1215 int ath_hal_enable_msi; /* enable MSI interrupts (needed?) */ 1216 int ath_hal_beacon_filter_interval; /* ok to be 0 for now? */ 1217 1218 /* For now, set this to 0 - net80211 needs to know about hardware MFP support */ 1219 int ath_hal_mfp_support; 1220 1221 int ath_hal_enable_ani; /* should set this.. */ 1222 int ath_hal_cwm_ignore_ext_cca; 1223 int ath_hal_show_bb_panic; 1224 int ath_hal_ant_ctrl_comm2g_switch_enable; 1225 int ath_hal_ext_atten_margin_cfg; 1226 int ath_hal_war70c; 1227 } HAL_OPS_CONFIG; 1228 1229 /* 1230 * Hardware Access Layer (HAL) API. 1231 * 1232 * Clients of the HAL call ath_hal_attach to obtain a reference to an 1233 * ath_hal structure for use with the device. Hardware-related operations 1234 * that follow must call back into the HAL through interface, supplying 1235 * the reference as the first parameter. Note that before using the 1236 * reference returned by ath_hal_attach the caller should verify the 1237 * ABI version number. 1238 */ 1239 struct ath_hal { 1240 uint32_t ah_magic; /* consistency check magic number */ 1241 uint16_t ah_devid; /* PCI device ID */ 1242 uint16_t ah_subvendorid; /* PCI subvendor ID */ 1243 HAL_SOFTC ah_sc; /* back pointer to driver/os state */ 1244 HAL_BUS_TAG ah_st; /* params for register r+w */ 1245 HAL_BUS_HANDLE ah_sh; 1246 HAL_CTRY_CODE ah_countryCode; 1247 1248 uint32_t ah_macVersion; /* MAC version id */ 1249 uint16_t ah_macRev; /* MAC revision */ 1250 uint16_t ah_phyRev; /* PHY revision */ 1251 /* NB: when only one radio is present the rev is in 5Ghz */ 1252 uint16_t ah_analog5GhzRev;/* 5GHz radio revision */ 1253 uint16_t ah_analog2GhzRev;/* 2GHz radio revision */ 1254 1255 uint16_t *ah_eepromdata; /* eeprom buffer, if needed */ 1256 1257 uint32_t ah_intrstate[8]; /* last int state */ 1258 uint32_t ah_syncstate; /* last sync intr state */ 1259 1260 HAL_OPS_CONFIG ah_config; 1261 const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *, 1262 u_int mode); 1263 void __ahdecl(*ah_detach)(struct ath_hal*); 1264 1265 /* Reset functions */ 1266 HAL_BOOL __ahdecl(*ah_reset)(struct ath_hal *, HAL_OPMODE, 1267 struct ieee80211_channel *, 1268 HAL_BOOL bChannelChange, HAL_STATUS *status); 1269 HAL_BOOL __ahdecl(*ah_phyDisable)(struct ath_hal *); 1270 HAL_BOOL __ahdecl(*ah_disable)(struct ath_hal *); 1271 void __ahdecl(*ah_configPCIE)(struct ath_hal *, HAL_BOOL restore, 1272 HAL_BOOL power_off); 1273 void __ahdecl(*ah_disablePCIE)(struct ath_hal *); 1274 void __ahdecl(*ah_setPCUConfig)(struct ath_hal *); 1275 HAL_BOOL __ahdecl(*ah_perCalibration)(struct ath_hal*, 1276 struct ieee80211_channel *, HAL_BOOL *); 1277 HAL_BOOL __ahdecl(*ah_perCalibrationN)(struct ath_hal *, 1278 struct ieee80211_channel *, u_int chainMask, 1279 HAL_BOOL longCal, HAL_BOOL *isCalDone); 1280 HAL_BOOL __ahdecl(*ah_resetCalValid)(struct ath_hal *, 1281 const struct ieee80211_channel *); 1282 HAL_BOOL __ahdecl(*ah_setTxPower)(struct ath_hal *, 1283 const struct ieee80211_channel *, uint16_t *); 1284 HAL_BOOL __ahdecl(*ah_setTxPowerLimit)(struct ath_hal *, uint32_t); 1285 HAL_BOOL __ahdecl(*ah_setBoardValues)(struct ath_hal *, 1286 const struct ieee80211_channel *); 1287 1288 /* Transmit functions */ 1289 HAL_BOOL __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*, 1290 HAL_BOOL incTrigLevel); 1291 int __ahdecl(*ah_setupTxQueue)(struct ath_hal *, HAL_TX_QUEUE, 1292 const HAL_TXQ_INFO *qInfo); 1293 HAL_BOOL __ahdecl(*ah_setTxQueueProps)(struct ath_hal *, int q, 1294 const HAL_TXQ_INFO *qInfo); 1295 HAL_BOOL __ahdecl(*ah_getTxQueueProps)(struct ath_hal *, int q, 1296 HAL_TXQ_INFO *qInfo); 1297 HAL_BOOL __ahdecl(*ah_releaseTxQueue)(struct ath_hal *ah, u_int q); 1298 HAL_BOOL __ahdecl(*ah_resetTxQueue)(struct ath_hal *ah, u_int q); 1299 uint32_t __ahdecl(*ah_getTxDP)(struct ath_hal*, u_int); 1300 HAL_BOOL __ahdecl(*ah_setTxDP)(struct ath_hal*, u_int, uint32_t txdp); 1301 uint32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, u_int q); 1302 HAL_BOOL __ahdecl(*ah_startTxDma)(struct ath_hal*, u_int); 1303 HAL_BOOL __ahdecl(*ah_stopTxDma)(struct ath_hal*, u_int); 1304 HAL_BOOL __ahdecl(*ah_setupTxDesc)(struct ath_hal *, struct ath_desc *, 1305 u_int pktLen, u_int hdrLen, 1306 HAL_PKT_TYPE type, u_int txPower, 1307 u_int txRate0, u_int txTries0, 1308 u_int keyIx, u_int antMode, u_int flags, 1309 u_int rtsctsRate, u_int rtsctsDuration, 1310 u_int compicvLen, u_int compivLen, 1311 u_int comp); 1312 HAL_BOOL __ahdecl(*ah_setupXTxDesc)(struct ath_hal *, struct ath_desc*, 1313 u_int txRate1, u_int txTries1, 1314 u_int txRate2, u_int txTries2, 1315 u_int txRate3, u_int txTries3); 1316 HAL_BOOL __ahdecl(*ah_fillTxDesc)(struct ath_hal *, struct ath_desc *, 1317 HAL_DMA_ADDR *bufAddrList, uint32_t *segLenList, 1318 u_int descId, u_int qcuId, HAL_BOOL firstSeg, 1319 HAL_BOOL lastSeg, const struct ath_desc *); 1320 HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *, 1321 struct ath_desc *, struct ath_tx_status *); 1322 void __ahdecl(*ah_getTxIntrQueue)(struct ath_hal *, uint32_t *); 1323 void __ahdecl(*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc*); 1324 HAL_BOOL __ahdecl(*ah_getTxCompletionRates)(struct ath_hal *, 1325 const struct ath_desc *ds, int *rates, int *tries); 1326 void __ahdecl(*ah_setTxDescLink)(struct ath_hal *ah, void *ds, 1327 uint32_t link); 1328 void __ahdecl(*ah_getTxDescLink)(struct ath_hal *ah, void *ds, 1329 uint32_t *link); 1330 void __ahdecl(*ah_getTxDescLinkPtr)(struct ath_hal *ah, void *ds, 1331 uint32_t **linkptr); 1332 void __ahdecl(*ah_setupTxStatusRing)(struct ath_hal *, 1333 void *ts_start, uint32_t ts_paddr_start, 1334 uint16_t size); 1335 void __ahdecl(*ah_getTxRawTxDesc)(struct ath_hal *, u_int32_t *); 1336 1337 /* Receive Functions */ 1338 uint32_t __ahdecl(*ah_getRxDP)(struct ath_hal*, HAL_RX_QUEUE); 1339 void __ahdecl(*ah_setRxDP)(struct ath_hal*, uint32_t rxdp, HAL_RX_QUEUE); 1340 void __ahdecl(*ah_enableReceive)(struct ath_hal*); 1341 HAL_BOOL __ahdecl(*ah_stopDmaReceive)(struct ath_hal*); 1342 void __ahdecl(*ah_startPcuReceive)(struct ath_hal*); 1343 void __ahdecl(*ah_stopPcuReceive)(struct ath_hal*); 1344 void __ahdecl(*ah_setMulticastFilter)(struct ath_hal*, 1345 uint32_t filter0, uint32_t filter1); 1346 HAL_BOOL __ahdecl(*ah_setMulticastFilterIndex)(struct ath_hal*, 1347 uint32_t index); 1348 HAL_BOOL __ahdecl(*ah_clrMulticastFilterIndex)(struct ath_hal*, 1349 uint32_t index); 1350 uint32_t __ahdecl(*ah_getRxFilter)(struct ath_hal*); 1351 void __ahdecl(*ah_setRxFilter)(struct ath_hal*, uint32_t); 1352 HAL_BOOL __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_desc *, 1353 uint32_t size, u_int flags); 1354 HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *, 1355 struct ath_desc *, uint32_t phyAddr, 1356 struct ath_desc *next, uint64_t tsf, 1357 struct ath_rx_status *); 1358 void __ahdecl(*ah_rxMonitor)(struct ath_hal *, 1359 const HAL_NODE_STATS *, 1360 const struct ieee80211_channel *); 1361 void __ahdecl(*ah_aniPoll)(struct ath_hal *, 1362 const struct ieee80211_channel *); 1363 void __ahdecl(*ah_procMibEvent)(struct ath_hal *, 1364 const HAL_NODE_STATS *); 1365 void __ahdecl(*ah_rxAntCombDiversity)(struct ath_hal *, 1366 struct ath_rx_status *, 1367 unsigned long, int); 1368 1369 /* Misc Functions */ 1370 HAL_STATUS __ahdecl(*ah_getCapability)(struct ath_hal *, 1371 HAL_CAPABILITY_TYPE, uint32_t capability, 1372 uint32_t *result); 1373 HAL_BOOL __ahdecl(*ah_setCapability)(struct ath_hal *, 1374 HAL_CAPABILITY_TYPE, uint32_t capability, 1375 uint32_t setting, HAL_STATUS *); 1376 HAL_BOOL __ahdecl(*ah_getDiagState)(struct ath_hal *, int request, 1377 const void *args, uint32_t argsize, 1378 void **result, uint32_t *resultsize); 1379 void __ahdecl(*ah_getMacAddress)(struct ath_hal *, uint8_t *); 1380 HAL_BOOL __ahdecl(*ah_setMacAddress)(struct ath_hal *, const uint8_t*); 1381 void __ahdecl(*ah_getBssIdMask)(struct ath_hal *, uint8_t *); 1382 HAL_BOOL __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const uint8_t*); 1383 HAL_BOOL __ahdecl(*ah_setRegulatoryDomain)(struct ath_hal*, 1384 uint16_t, HAL_STATUS *); 1385 void __ahdecl(*ah_setLedState)(struct ath_hal*, HAL_LED_STATE); 1386 void __ahdecl(*ah_writeAssocid)(struct ath_hal*, 1387 const uint8_t *bssid, uint16_t assocId); 1388 HAL_BOOL __ahdecl(*ah_gpioCfgOutput)(struct ath_hal *, 1389 uint32_t gpio, HAL_GPIO_MUX_TYPE); 1390 HAL_BOOL __ahdecl(*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio); 1391 uint32_t __ahdecl(*ah_gpioGet)(struct ath_hal *, uint32_t gpio); 1392 HAL_BOOL __ahdecl(*ah_gpioSet)(struct ath_hal *, 1393 uint32_t gpio, uint32_t val); 1394 void __ahdecl(*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t); 1395 uint32_t __ahdecl(*ah_getTsf32)(struct ath_hal*); 1396 uint64_t __ahdecl(*ah_getTsf64)(struct ath_hal*); 1397 void __ahdecl(*ah_setTsf64)(struct ath_hal *, uint64_t); 1398 void __ahdecl(*ah_resetTsf)(struct ath_hal*); 1399 HAL_BOOL __ahdecl(*ah_detectCardPresent)(struct ath_hal*); 1400 void __ahdecl(*ah_updateMibCounters)(struct ath_hal*, 1401 HAL_MIB_STATS*); 1402 HAL_RFGAIN __ahdecl(*ah_getRfGain)(struct ath_hal*); 1403 u_int __ahdecl(*ah_getDefAntenna)(struct ath_hal*); 1404 void __ahdecl(*ah_setDefAntenna)(struct ath_hal*, u_int); 1405 HAL_ANT_SETTING __ahdecl(*ah_getAntennaSwitch)(struct ath_hal*); 1406 HAL_BOOL __ahdecl(*ah_setAntennaSwitch)(struct ath_hal*, 1407 HAL_ANT_SETTING); 1408 HAL_BOOL __ahdecl(*ah_setSifsTime)(struct ath_hal*, u_int); 1409 u_int __ahdecl(*ah_getSifsTime)(struct ath_hal*); 1410 HAL_BOOL __ahdecl(*ah_setSlotTime)(struct ath_hal*, u_int); 1411 u_int __ahdecl(*ah_getSlotTime)(struct ath_hal*); 1412 HAL_BOOL __ahdecl(*ah_setAckTimeout)(struct ath_hal*, u_int); 1413 u_int __ahdecl(*ah_getAckTimeout)(struct ath_hal*); 1414 HAL_BOOL __ahdecl(*ah_setAckCTSRate)(struct ath_hal*, u_int); 1415 u_int __ahdecl(*ah_getAckCTSRate)(struct ath_hal*); 1416 HAL_BOOL __ahdecl(*ah_setCTSTimeout)(struct ath_hal*, u_int); 1417 u_int __ahdecl(*ah_getCTSTimeout)(struct ath_hal*); 1418 HAL_BOOL __ahdecl(*ah_setDecompMask)(struct ath_hal*, uint16_t, int); 1419 void __ahdecl(*ah_setCoverageClass)(struct ath_hal*, uint8_t, int); 1420 HAL_STATUS __ahdecl(*ah_setQuiet)(struct ath_hal *ah, uint32_t period, 1421 uint32_t duration, uint32_t nextStart, 1422 HAL_QUIET_FLAG flag); 1423 1424 /* DFS functions */ 1425 void __ahdecl(*ah_enableDfs)(struct ath_hal *ah, 1426 HAL_PHYERR_PARAM *pe); 1427 void __ahdecl(*ah_getDfsThresh)(struct ath_hal *ah, 1428 HAL_PHYERR_PARAM *pe); 1429 HAL_BOOL __ahdecl(*ah_getDfsDefaultThresh)(struct ath_hal *ah, 1430 HAL_PHYERR_PARAM *pe); 1431 HAL_BOOL __ahdecl(*ah_procRadarEvent)(struct ath_hal *ah, 1432 struct ath_rx_status *rxs, uint64_t fulltsf, 1433 const char *buf, HAL_DFS_EVENT *event); 1434 HAL_BOOL __ahdecl(*ah_isFastClockEnabled)(struct ath_hal *ah); 1435 1436 /* Key Cache Functions */ 1437 uint32_t __ahdecl(*ah_getKeyCacheSize)(struct ath_hal*); 1438 HAL_BOOL __ahdecl(*ah_resetKeyCacheEntry)(struct ath_hal*, uint16_t); 1439 HAL_BOOL __ahdecl(*ah_isKeyCacheEntryValid)(struct ath_hal *, 1440 uint16_t); 1441 HAL_BOOL __ahdecl(*ah_setKeyCacheEntry)(struct ath_hal*, 1442 uint16_t, const HAL_KEYVAL *, 1443 const uint8_t *, int); 1444 HAL_BOOL __ahdecl(*ah_setKeyCacheEntryMac)(struct ath_hal*, 1445 uint16_t, const uint8_t *); 1446 1447 /* Power Management Functions */ 1448 HAL_BOOL __ahdecl(*ah_setPowerMode)(struct ath_hal*, 1449 HAL_POWER_MODE mode, int setChip); 1450 HAL_POWER_MODE __ahdecl(*ah_getPowerMode)(struct ath_hal*); 1451 int16_t __ahdecl(*ah_getChanNoise)(struct ath_hal *, 1452 const struct ieee80211_channel *); 1453 1454 /* Beacon Management Functions */ 1455 void __ahdecl(*ah_setBeaconTimers)(struct ath_hal*, 1456 const HAL_BEACON_TIMERS *); 1457 /* NB: deprecated, use ah_setBeaconTimers instead */ 1458 void __ahdecl(*ah_beaconInit)(struct ath_hal *, 1459 uint32_t nexttbtt, uint32_t intval); 1460 void __ahdecl(*ah_setStationBeaconTimers)(struct ath_hal*, 1461 const HAL_BEACON_STATE *); 1462 void __ahdecl(*ah_resetStationBeaconTimers)(struct ath_hal*); 1463 uint64_t __ahdecl(*ah_getNextTBTT)(struct ath_hal *); 1464 1465 /* 802.11n Functions */ 1466 HAL_BOOL __ahdecl(*ah_chainTxDesc)(struct ath_hal *, 1467 struct ath_desc *, 1468 HAL_DMA_ADDR *bufAddrList, 1469 uint32_t *segLenList, 1470 u_int, u_int, HAL_PKT_TYPE, 1471 u_int, HAL_CIPHER, uint8_t, HAL_BOOL, 1472 HAL_BOOL, HAL_BOOL); 1473 HAL_BOOL __ahdecl(*ah_setupFirstTxDesc)(struct ath_hal *, 1474 struct ath_desc *, u_int, u_int, u_int, 1475 u_int, u_int, u_int, u_int, u_int); 1476 HAL_BOOL __ahdecl(*ah_setupLastTxDesc)(struct ath_hal *, 1477 struct ath_desc *, const struct ath_desc *); 1478 void __ahdecl(*ah_set11nRateScenario)(struct ath_hal *, 1479 struct ath_desc *, u_int, u_int, 1480 HAL_11N_RATE_SERIES [], u_int, u_int); 1481 1482 /* 1483 * The next 4 (set11ntxdesc -> set11naggrlast) are specific 1484 * to the EDMA HAL. Descriptors are chained together by 1485 * using filltxdesc (not ChainTxDesc) and then setting the 1486 * aggregate flags appropriately using first/middle/last. 1487 */ 1488 void __ahdecl(*ah_set11nTxDesc)(struct ath_hal *, 1489 void *, u_int, HAL_PKT_TYPE, u_int, u_int, 1490 u_int); 1491 void __ahdecl(*ah_set11nAggrFirst)(struct ath_hal *, 1492 struct ath_desc *, u_int, u_int); 1493 void __ahdecl(*ah_set11nAggrMiddle)(struct ath_hal *, 1494 struct ath_desc *, u_int); 1495 void __ahdecl(*ah_set11nAggrLast)(struct ath_hal *, 1496 struct ath_desc *); 1497 1498 void __ahdecl(*ah_clr11nAggr)(struct ath_hal *, 1499 struct ath_desc *); 1500 void __ahdecl(*ah_set11nBurstDuration)(struct ath_hal *, 1501 struct ath_desc *, u_int); 1502 HAL_BOOL __ahdecl(*ah_getMibCycleCounts) (struct ath_hal *, 1503 HAL_SURVEY_SAMPLE *); 1504 1505 uint32_t __ahdecl(*ah_get11nExtBusy)(struct ath_hal *); 1506 void __ahdecl(*ah_set11nMac2040)(struct ath_hal *, 1507 HAL_HT_MACMODE); 1508 HAL_HT_RXCLEAR __ahdecl(*ah_get11nRxClear)(struct ath_hal *ah); 1509 void __ahdecl(*ah_set11nRxClear)(struct ath_hal *, 1510 HAL_HT_RXCLEAR); 1511 1512 /* Interrupt functions */ 1513 HAL_BOOL __ahdecl(*ah_isInterruptPending)(struct ath_hal*); 1514 HAL_BOOL __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT*); 1515 HAL_INT __ahdecl(*ah_getInterrupts)(struct ath_hal*); 1516 HAL_INT __ahdecl(*ah_setInterrupts)(struct ath_hal*, HAL_INT); 1517 1518 /* Bluetooth Coexistence functions */ 1519 void __ahdecl(*ah_btCoexSetInfo)(struct ath_hal *, 1520 HAL_BT_COEX_INFO *); 1521 void __ahdecl(*ah_btCoexSetConfig)(struct ath_hal *, 1522 HAL_BT_COEX_CONFIG *); 1523 void __ahdecl(*ah_btCoexSetQcuThresh)(struct ath_hal *, 1524 int); 1525 void __ahdecl(*ah_btCoexSetWeights)(struct ath_hal *, 1526 uint32_t); 1527 void __ahdecl(*ah_btCoexSetBmissThresh)(struct ath_hal *, 1528 uint32_t); 1529 void __ahdecl(*ah_btcoexSetParameter)(struct ath_hal *, 1530 uint32_t, uint32_t); 1531 void __ahdecl(*ah_btCoexDisable)(struct ath_hal *); 1532 int __ahdecl(*ah_btCoexEnable)(struct ath_hal *); 1533 }; 1534 1535 /* 1536 * Check the PCI vendor ID and device ID against Atheros' values 1537 * and return a printable description for any Atheros hardware. 1538 * AH_NULL is returned if the ID's do not describe Atheros hardware. 1539 */ 1540 extern const char *__ahdecl ath_hal_probe(uint16_t vendorid, uint16_t devid); 1541 1542 /* 1543 * Attach the HAL for use with the specified device. The device is 1544 * defined by the PCI device ID. The caller provides an opaque pointer 1545 * to an upper-layer data structure (HAL_SOFTC) that is stored in the 1546 * HAL state block for later use. Hardware register accesses are done 1547 * using the specified bus tag and handle. On successful return a 1548 * reference to a state block is returned that must be supplied in all 1549 * subsequent HAL calls. Storage associated with this reference is 1550 * dynamically allocated and must be freed by calling the ah_detach 1551 * method when the client is done. If the attach operation fails a 1552 * null (AH_NULL) reference will be returned and a status code will 1553 * be returned if the status parameter is non-zero. 1554 */ 1555 extern struct ath_hal * __ahdecl ath_hal_attach(uint16_t devid, HAL_SOFTC, 1556 HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, HAL_STATUS* status); 1557 1558 extern const char *ath_hal_mac_name(struct ath_hal *); 1559 extern const char *ath_hal_rf_name(struct ath_hal *); 1560 1561 /* 1562 * Regulatory interfaces. Drivers should use ath_hal_init_channels to 1563 * request a set of channels for a particular country code and/or 1564 * regulatory domain. If CTRY_DEFAULT and SKU_NONE are specified then 1565 * this list is constructed according to the contents of the EEPROM. 1566 * ath_hal_getchannels acts similarly but does not alter the operating 1567 * state; this can be used to collect information for a particular 1568 * regulatory configuration. Finally ath_hal_set_channels installs a 1569 * channel list constructed outside the driver. The HAL will adopt the 1570 * channel list and setup internal state according to the specified 1571 * regulatory configuration (e.g. conformance test limits). 1572 * 1573 * For all interfaces the channel list is returned in the supplied array. 1574 * maxchans defines the maximum size of this array. nchans contains the 1575 * actual number of channels returned. If a problem occurred then a 1576 * status code != HAL_OK is returned. 1577 */ 1578 struct ieee80211_channel; 1579 1580 /* 1581 * Return a list of channels according to the specified regulatory. 1582 */ 1583 extern HAL_STATUS __ahdecl ath_hal_getchannels(struct ath_hal *, 1584 struct ieee80211_channel *chans, u_int maxchans, int *nchans, 1585 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn, 1586 HAL_BOOL enableExtendedChannels); 1587 1588 /* 1589 * Return a list of channels and install it as the current operating 1590 * regulatory list. 1591 */ 1592 extern HAL_STATUS __ahdecl ath_hal_init_channels(struct ath_hal *, 1593 struct ieee80211_channel *chans, u_int maxchans, int *nchans, 1594 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN rd, 1595 HAL_BOOL enableExtendedChannels); 1596 1597 /* 1598 * Install the list of channels as the current operating regulatory 1599 * and setup related state according to the country code and sku. 1600 */ 1601 extern HAL_STATUS __ahdecl ath_hal_set_channels(struct ath_hal *, 1602 struct ieee80211_channel *chans, int nchans, 1603 HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn); 1604 1605 /* 1606 * Fetch the ctl/ext noise floor values reported by a MIMO 1607 * radio. Returns 1 for valid results, 0 for invalid channel. 1608 */ 1609 extern int __ahdecl ath_hal_get_mimo_chan_noise(struct ath_hal *ah, 1610 const struct ieee80211_channel *chan, int16_t *nf_ctl, 1611 int16_t *nf_ext); 1612 1613 /* 1614 * Calibrate noise floor data following a channel scan or similar. 1615 * This must be called prior retrieving noise floor data. 1616 */ 1617 extern void __ahdecl ath_hal_process_noisefloor(struct ath_hal *ah); 1618 1619 /* 1620 * Return bit mask of wireless modes supported by the hardware. 1621 */ 1622 extern u_int __ahdecl ath_hal_getwirelessmodes(struct ath_hal*); 1623 1624 /* 1625 * Get the HAL wireless mode for the given channel. 1626 */ 1627 extern int ath_hal_get_curmode(struct ath_hal *ah, 1628 const struct ieee80211_channel *chan); 1629 1630 /* 1631 * Calculate the packet TX time for a legacy or 11n frame 1632 */ 1633 extern uint32_t __ahdecl ath_hal_pkt_txtime(struct ath_hal *ah, 1634 const HAL_RATE_TABLE *rates, uint32_t frameLen, 1635 uint16_t rateix, HAL_BOOL isht40, HAL_BOOL shortPreamble); 1636 1637 /* 1638 * Calculate the duration of an 11n frame. 1639 */ 1640 extern uint32_t __ahdecl ath_computedur_ht(uint32_t frameLen, uint16_t rate, 1641 int streams, HAL_BOOL isht40, HAL_BOOL isShortGI); 1642 1643 /* 1644 * Calculate the transmit duration of a legacy frame. 1645 */ 1646 extern uint16_t __ahdecl ath_hal_computetxtime(struct ath_hal *, 1647 const HAL_RATE_TABLE *rates, uint32_t frameLen, 1648 uint16_t rateix, HAL_BOOL shortPreamble); 1649 1650 /* 1651 * Adjust the TSF. 1652 */ 1653 extern void __ahdecl ath_hal_adjusttsf(struct ath_hal *ah, int32_t tsfdelta); 1654 1655 /* 1656 * Enable or disable CCA. 1657 */ 1658 void __ahdecl ath_hal_setcca(struct ath_hal *ah, int ena); 1659 1660 /* 1661 * Get CCA setting. 1662 */ 1663 int __ahdecl ath_hal_getcca(struct ath_hal *ah); 1664 1665 /* 1666 * Read EEPROM data from ah_eepromdata 1667 */ 1668 HAL_BOOL __ahdecl ath_hal_EepromDataRead(struct ath_hal *ah, 1669 u_int off, uint16_t *data); 1670 1671 /* 1672 * For now, simply pass through MFP frames. 1673 */ 1674 static inline u_int32_t 1675 ath_hal_get_mfp_qos(struct ath_hal *ah) 1676 { 1677 //return AH_PRIVATE(ah)->ah_mfp_qos; 1678 return HAL_MFP_QOSDATA; 1679 } 1680 1681 #endif /* _ATH_AH_H_ */ 1682