1 /* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19 20 #ifndef _ATH_AH_H_ 21 #define _ATH_AH_H_ 22 /* 23 * Atheros Hardware Access Layer 24 * 25 * Clients of the HAL call ath_hal_attach to obtain a reference to an ath_hal 26 * structure for use with the device. Hardware-related operations that 27 * follow must call back into the HAL through interface, supplying the 28 * reference as the first parameter. 29 */ 30 31 #include "ah_osdep.h" 32 33 /* 34 * The maximum number of TX/RX chains supported. 35 * This is intended to be used by various statistics gathering operations 36 * (NF, RSSI, EVM). 37 */ 38 #define AH_MAX_CHAINS 3 39 #define AH_MIMO_MAX_EVM_PILOTS 6 40 41 /* 42 * __ahdecl is analogous to _cdecl; it defines the calling 43 * convention used within the HAL. For most systems this 44 * can just default to be empty and the compiler will (should) 45 * use _cdecl. For systems where _cdecl is not compatible this 46 * must be defined. See linux/ah_osdep.h for an example. 47 */ 48 #ifndef __ahdecl 49 #define __ahdecl 50 #endif 51 52 /* 53 * Status codes that may be returned by the HAL. Note that 54 * interfaces that return a status code set it only when an 55 * error occurs--i.e. you cannot check it for success. 56 */ 57 typedef enum { 58 HAL_OK = 0, /* No error */ 59 HAL_ENXIO = 1, /* No hardware present */ 60 HAL_ENOMEM = 2, /* Memory allocation failed */ 61 HAL_EIO = 3, /* Hardware didn't respond as expected */ 62 HAL_EEMAGIC = 4, /* EEPROM magic number invalid */ 63 HAL_EEVERSION = 5, /* EEPROM version invalid */ 64 HAL_EELOCKED = 6, /* EEPROM unreadable */ 65 HAL_EEBADSUM = 7, /* EEPROM checksum invalid */ 66 HAL_EEREAD = 8, /* EEPROM read problem */ 67 HAL_EEBADMAC = 9, /* EEPROM mac address invalid */ 68 HAL_EESIZE = 10, /* EEPROM size not supported */ 69 HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */ 70 HAL_EINVAL = 12, /* Invalid parameter to function */ 71 HAL_ENOTSUPP = 13, /* Hardware revision not supported */ 72 HAL_ESELFTEST = 14, /* Hardware self-test failed */ 73 HAL_EINPROGRESS = 15, /* Operation incomplete */ 74 HAL_EEBADREG = 16, /* EEPROM invalid regulatory contents */ 75 HAL_EEBADCC = 17, /* EEPROM invalid country code */ 76 HAL_INV_PMODE = 18, /* Couldn't bring out of sleep state */ 77 } HAL_STATUS; 78 79 typedef enum { 80 AH_FALSE = 0, /* NB: lots of code assumes false is zero */ 81 AH_TRUE = 1, 82 } HAL_BOOL; 83 84 typedef enum { 85 HAL_CAP_REG_DMN = 0, /* current regulatory domain */ 86 HAL_CAP_CIPHER = 1, /* hardware supports cipher */ 87 HAL_CAP_TKIP_MIC = 2, /* handle TKIP MIC in hardware */ 88 HAL_CAP_TKIP_SPLIT = 3, /* hardware TKIP uses split keys */ 89 HAL_CAP_PHYCOUNTERS = 4, /* hardware PHY error counters */ 90 HAL_CAP_DIVERSITY = 5, /* hardware supports fast diversity */ 91 HAL_CAP_KEYCACHE_SIZE = 6, /* number of entries in key cache */ 92 HAL_CAP_NUM_TXQUEUES = 7, /* number of hardware xmit queues */ 93 HAL_CAP_VEOL = 9, /* hardware supports virtual EOL */ 94 HAL_CAP_PSPOLL = 10, /* hardware has working PS-Poll support */ 95 HAL_CAP_DIAG = 11, /* hardware diagnostic support */ 96 HAL_CAP_COMPRESSION = 12, /* hardware supports compression */ 97 HAL_CAP_BURST = 13, /* hardware supports packet bursting */ 98 HAL_CAP_FASTFRAME = 14, /* hardware supoprts fast frames */ 99 HAL_CAP_TXPOW = 15, /* global tx power limit */ 100 HAL_CAP_TPC = 16, /* per-packet tx power control */ 101 HAL_CAP_PHYDIAG = 17, /* hardware phy error diagnostic */ 102 HAL_CAP_BSSIDMASK = 18, /* hardware supports bssid mask */ 103 HAL_CAP_MCAST_KEYSRCH = 19, /* hardware has multicast key search */ 104 HAL_CAP_TSF_ADJUST = 20, /* hardware has beacon tsf adjust */ 105 /* 21 was HAL_CAP_XR */ 106 HAL_CAP_WME_TKIPMIC = 22, /* hardware can support TKIP MIC when WMM is turned on */ 107 /* 23 was HAL_CAP_CHAN_HALFRATE */ 108 /* 24 was HAL_CAP_CHAN_QUARTERRATE */ 109 HAL_CAP_RFSILENT = 25, /* hardware has rfsilent support */ 110 HAL_CAP_TPC_ACK = 26, /* ack txpower with per-packet tpc */ 111 HAL_CAP_TPC_CTS = 27, /* cts txpower with per-packet tpc */ 112 HAL_CAP_11D = 28, /* 11d beacon support for changing cc */ 113 HAL_CAP_PCIE_PS = 29, 114 HAL_CAP_HT = 30, /* hardware can support HT */ 115 HAL_CAP_GTXTO = 31, /* hardware supports global tx timeout */ 116 HAL_CAP_FAST_CC = 32, /* hardware supports fast channel change */ 117 HAL_CAP_TX_CHAINMASK = 33, /* mask of TX chains supported */ 118 HAL_CAP_RX_CHAINMASK = 34, /* mask of RX chains supported */ 119 HAL_CAP_NUM_GPIO_PINS = 36, /* number of GPIO pins */ 120 121 HAL_CAP_CST = 38, /* hardware supports carrier sense timeout */ 122 HAL_CAP_RIFS_RX = 39, 123 HAL_CAP_RIFS_TX = 40, 124 HAL_CAP_FORCE_PPM = 41, 125 HAL_CAP_RTS_AGGR_LIMIT = 42, /* aggregation limit with RTS */ 126 HAL_CAP_4ADDR_AGGR = 43, /* hardware is capable of 4addr aggregation */ 127 HAL_CAP_DFS_DMN = 44, /* current DFS domain */ 128 HAL_CAP_EXT_CHAN_DFS = 45, /* DFS support for extension channel */ 129 HAL_CAP_COMBINED_RADAR_RSSI = 46, /* Is combined RSSI for radar accurate */ 130 131 HAL_CAP_AUTO_SLEEP = 48, /* hardware can go to network sleep 132 automatically after waking up to receive TIM */ 133 HAL_CAP_MBSSID_AGGR_SUPPORT = 49, /* Support for mBSSID Aggregation */ 134 HAL_CAP_SPLIT_4KB_TRANS = 50, /* hardware supports descriptors straddling a 4k page boundary */ 135 HAL_CAP_REG_FLAG = 51, /* Regulatory domain flags */ 136 HAL_CAP_BB_RIFS_HANG = 52, 137 HAL_CAP_RIFS_RX_ENABLED = 53, 138 HAL_CAP_BB_DFS_HANG = 54, 139 140 HAL_CAP_BT_COEX = 60, /* hardware is capable of bluetooth coexistence */ 141 HAL_CAP_DYNAMIC_SMPS = 61, /* Dynamic MIMO Power Save hardware support */ 142 143 HAL_CAP_DS = 67, /* 2 stream */ 144 HAL_CAP_BB_RX_CLEAR_STUCK_HANG = 68, 145 HAL_CAP_MAC_HANG = 69, /* can MAC hang */ 146 HAL_CAP_MFP = 70, /* Management Frame Protection in hardware */ 147 148 HAL_CAP_TS = 72, /* 3 stream */ 149 150 HAL_CAP_ENHANCED_DMA_SUPPORT = 75, /* DMA FIFO support */ 151 HAL_CAP_NUM_TXMAPS = 76, /* Number of buffers in a transmit descriptor */ 152 HAL_CAP_TXDESCLEN = 77, /* Length of transmit descriptor */ 153 HAL_CAP_TXSTATUSLEN = 78, /* Length of transmit status descriptor */ 154 HAL_CAP_RXSTATUSLEN = 79, /* Length of transmit status descriptor */ 155 HAL_CAP_RXFIFODEPTH = 80, /* Receive hardware FIFO depth */ 156 HAL_CAP_RXBUFSIZE = 81, /* Receive Buffer Length */ 157 HAL_CAP_NUM_MR_RETRIES = 82, /* limit on multirate retries */ 158 HAL_CAP_OL_PWRCTRL = 84, /* Open loop TX power control */ 159 160 HAL_CAP_BB_PANIC_WATCHDOG = 92, 161 162 HAL_CAP_HT20_SGI = 96, /* hardware supports HT20 short GI */ 163 164 HAL_CAP_LDPC = 99, 165 166 HAL_CAP_RXTSTAMP_PREC = 100, /* rx desc tstamp precision (bits) */ 167 168 HAL_CAP_PHYRESTART_CLR_WAR = 106, /* in some cases, clear phy restart to fix bb hang */ 169 HAL_CAP_ENTERPRISE_MODE = 107, /* Enterprise mode features */ 170 HAL_CAP_LDPCWAR = 108, 171 HAL_CAP_CHANNEL_SWITCH_TIME_USEC = 109, /* Channel change time, usec */ 172 HAL_CAP_ENABLE_APM = 110, /* APM enabled */ 173 HAL_CAP_PCIE_LCR_EXTSYNC_EN = 111, 174 HAL_CAP_PCIE_LCR_OFFSET = 112, 175 176 HAL_CAP_ENHANCED_DFS_SUPPORT = 117, /* hardware supports enhanced DFS */ 177 HAL_CAP_MCI = 118, 178 HAL_CAP_SMARTANTENNA = 119, 179 HAL_CAP_TRAFFIC_FAST_RECOVER = 120, 180 HAL_CAP_TX_DIVERSITY = 121, 181 HAL_CAP_CRDC = 122, 182 183 /* The following are private to the FreeBSD HAL (224 onward) */ 184 185 HAL_CAP_INTMIT = 229, /* interference mitigation */ 186 HAL_CAP_RXORN_FATAL = 230, /* HAL_INT_RXORN treated as fatal */ 187 HAL_CAP_BB_HANG = 235, /* can baseband hang */ 188 HAL_CAP_INTRMASK = 237, /* bitmask of supported interrupts */ 189 HAL_CAP_BSSIDMATCH = 238, /* hardware has disable bssid match */ 190 HAL_CAP_STREAMS = 239, /* how many 802.11n spatial streams are available */ 191 HAL_CAP_RXDESC_SELFLINK = 242, /* support a self-linked tail RX descriptor */ 192 HAL_CAP_LONG_RXDESC_TSF = 243, /* hardware supports 32bit TSF in RX descriptor */ 193 HAL_CAP_BB_READ_WAR = 244, /* baseband read WAR */ 194 HAL_CAP_SERIALISE_WAR = 245, /* serialise register access on PCI */ 195 } HAL_CAPABILITY_TYPE; 196 197 /* 198 * "States" for setting the LED. These correspond to 199 * the possible 802.11 operational states and there may 200 * be a many-to-one mapping between these states and the 201 * actual hardware state for the LED's (i.e. the hardware 202 * may have fewer states). 203 */ 204 typedef enum { 205 HAL_LED_INIT = 0, 206 HAL_LED_SCAN = 1, 207 HAL_LED_AUTH = 2, 208 HAL_LED_ASSOC = 3, 209 HAL_LED_RUN = 4 210 } HAL_LED_STATE; 211 212 /* 213 * Transmit queue types/numbers. These are used to tag 214 * each transmit queue in the hardware and to identify a set 215 * of transmit queues for operations such as start/stop dma. 216 */ 217 typedef enum { 218 HAL_TX_QUEUE_INACTIVE = 0, /* queue is inactive/unused */ 219 HAL_TX_QUEUE_DATA = 1, /* data xmit q's */ 220 HAL_TX_QUEUE_BEACON = 2, /* beacon xmit q */ 221 HAL_TX_QUEUE_CAB = 3, /* "crap after beacon" xmit q */ 222 HAL_TX_QUEUE_UAPSD = 4, /* u-apsd power save xmit q */ 223 HAL_TX_QUEUE_PSPOLL = 5, /* power save poll xmit q */ 224 HAL_TX_QUEUE_CFEND = 6, 225 HAL_TX_QUEUE_PAPRD = 7, 226 } HAL_TX_QUEUE; 227 228 #define HAL_NUM_TX_QUEUES 10 /* max possible # of queues */ 229 230 /* 231 * Receive queue types. These are used to tag 232 * each transmit queue in the hardware and to identify a set 233 * of transmit queues for operations such as start/stop dma. 234 */ 235 typedef enum { 236 HAL_RX_QUEUE_HP = 0, /* high priority recv queue */ 237 HAL_RX_QUEUE_LP = 1, /* low priority recv queue */ 238 } HAL_RX_QUEUE; 239 240 #define HAL_NUM_RX_QUEUES 2 /* max possible # of queues */ 241 242 #define HAL_TXFIFO_DEPTH 8 /* transmit fifo depth */ 243 244 /* 245 * Transmit queue subtype. These map directly to 246 * WME Access Categories (except for UPSD). Refer 247 * to Table 5 of the WME spec. 248 */ 249 typedef enum { 250 HAL_WME_AC_BK = 0, /* background access category */ 251 HAL_WME_AC_BE = 1, /* best effort access category*/ 252 HAL_WME_AC_VI = 2, /* video access category */ 253 HAL_WME_AC_VO = 3, /* voice access category */ 254 HAL_WME_UPSD = 4, /* uplink power save */ 255 } HAL_TX_QUEUE_SUBTYPE; 256 257 /* 258 * Transmit queue flags that control various 259 * operational parameters. 260 */ 261 typedef enum { 262 /* 263 * Per queue interrupt enables. When set the associated 264 * interrupt may be delivered for packets sent through 265 * the queue. Without these enabled no interrupts will 266 * be delivered for transmits through the queue. 267 */ 268 HAL_TXQ_TXOKINT_ENABLE = 0x0001, /* enable TXOK interrupt */ 269 HAL_TXQ_TXERRINT_ENABLE = 0x0001, /* enable TXERR interrupt */ 270 HAL_TXQ_TXDESCINT_ENABLE = 0x0002, /* enable TXDESC interrupt */ 271 HAL_TXQ_TXEOLINT_ENABLE = 0x0004, /* enable TXEOL interrupt */ 272 HAL_TXQ_TXURNINT_ENABLE = 0x0008, /* enable TXURN interrupt */ 273 /* 274 * Enable hardware compression for packets sent through 275 * the queue. The compression buffer must be setup and 276 * packets must have a key entry marked in the tx descriptor. 277 */ 278 HAL_TXQ_COMPRESSION_ENABLE = 0x0010, /* enable h/w compression */ 279 /* 280 * Disable queue when veol is hit or ready time expires. 281 * By default the queue is disabled only on reaching the 282 * physical end of queue (i.e. a null link ptr in the 283 * descriptor chain). 284 */ 285 HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE = 0x0020, 286 /* 287 * Schedule frames on delivery of a DBA (DMA Beacon Alert) 288 * event. Frames will be transmitted only when this timer 289 * fires, e.g to transmit a beacon in ap or adhoc modes. 290 */ 291 HAL_TXQ_DBA_GATED = 0x0040, /* schedule based on DBA */ 292 /* 293 * Each transmit queue has a counter that is incremented 294 * each time the queue is enabled and decremented when 295 * the list of frames to transmit is traversed (or when 296 * the ready time for the queue expires). This counter 297 * must be non-zero for frames to be scheduled for 298 * transmission. The following controls disable bumping 299 * this counter under certain conditions. Typically this 300 * is used to gate frames based on the contents of another 301 * queue (e.g. CAB traffic may only follow a beacon frame). 302 * These are meaningful only when frames are scheduled 303 * with a non-ASAP policy (e.g. DBA-gated). 304 */ 305 HAL_TXQ_CBR_DIS_QEMPTY = 0x0080, /* disable on this q empty */ 306 HAL_TXQ_CBR_DIS_BEMPTY = 0x0100, /* disable on beacon q empty */ 307 308 /* 309 * Fragment burst backoff policy. Normally the no backoff 310 * is done after a successful transmission, the next fragment 311 * is sent at SIFS. If this flag is set backoff is done 312 * after each fragment, regardless whether it was ack'd or 313 * not, after the backoff count reaches zero a normal channel 314 * access procedure is done before the next transmit (i.e. 315 * wait AIFS instead of SIFS). 316 */ 317 HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE = 0x00800000, 318 /* 319 * Disable post-tx backoff following each frame. 320 */ 321 HAL_TXQ_BACKOFF_DISABLE = 0x00010000, /* disable post backoff */ 322 /* 323 * DCU arbiter lockout control. This controls how 324 * lower priority tx queues are handled with respect to 325 * to a specific queue when multiple queues have frames 326 * to send. No lockout means lower priority queues arbitrate 327 * concurrently with this queue. Intra-frame lockout 328 * means lower priority queues are locked out until the 329 * current frame transmits (e.g. including backoffs and bursting). 330 * Global lockout means nothing lower can arbitrary so 331 * long as there is traffic activity on this queue (frames, 332 * backoff, etc). 333 */ 334 HAL_TXQ_ARB_LOCKOUT_INTRA = 0x00020000, /* intra-frame lockout */ 335 HAL_TXQ_ARB_LOCKOUT_GLOBAL = 0x00040000, /* full lockout s */ 336 337 HAL_TXQ_IGNORE_VIRTCOL = 0x00080000, /* ignore virt collisions */ 338 HAL_TXQ_SEQNUM_INC_DIS = 0x00100000, /* disable seqnum increment */ 339 } HAL_TX_QUEUE_FLAGS; 340 341 typedef struct { 342 uint32_t tqi_ver; /* hal TXQ version */ 343 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* subtype if applicable */ 344 HAL_TX_QUEUE_FLAGS tqi_qflags; /* flags (see above) */ 345 uint32_t tqi_priority; /* (not used) */ 346 uint32_t tqi_aifs; /* aifs */ 347 uint32_t tqi_cwmin; /* cwMin */ 348 uint32_t tqi_cwmax; /* cwMax */ 349 uint16_t tqi_shretry; /* rts retry limit */ 350 uint16_t tqi_lgretry; /* long retry limit (not used)*/ 351 uint32_t tqi_cbrPeriod; /* CBR period (us) */ 352 uint32_t tqi_cbrOverflowLimit; /* threshold for CBROVF int */ 353 uint32_t tqi_burstTime; /* max burst duration (us) */ 354 uint32_t tqi_readyTime; /* frame schedule time (us) */ 355 uint32_t tqi_compBuf; /* comp buffer phys addr */ 356 } HAL_TXQ_INFO; 357 358 #define HAL_TQI_NONVAL 0xffff 359 360 /* token to use for aifs, cwmin, cwmax */ 361 #define HAL_TXQ_USEDEFAULT ((uint32_t) -1) 362 363 /* compression definitions */ 364 #define HAL_COMP_BUF_MAX_SIZE 9216 /* 9K */ 365 #define HAL_COMP_BUF_ALIGN_SIZE 512 366 367 /* 368 * Transmit packet types. This belongs in ah_desc.h, but 369 * is here so we can give a proper type to various parameters 370 * (and not require everyone include the file). 371 * 372 * NB: These values are intentionally assigned for 373 * direct use when setting up h/w descriptors. 374 */ 375 typedef enum { 376 HAL_PKT_TYPE_NORMAL = 0, 377 HAL_PKT_TYPE_ATIM = 1, 378 HAL_PKT_TYPE_PSPOLL = 2, 379 HAL_PKT_TYPE_BEACON = 3, 380 HAL_PKT_TYPE_PROBE_RESP = 4, 381 HAL_PKT_TYPE_CHIRP = 5, 382 HAL_PKT_TYPE_GRP_POLL = 6, 383 HAL_PKT_TYPE_AMPDU = 7, 384 } HAL_PKT_TYPE; 385 386 /* Rx Filter Frame Types */ 387 typedef enum { 388 /* 389 * These bits correspond to AR_RX_FILTER for all chips. 390 * Not all bits are supported by all chips. 391 */ 392 HAL_RX_FILTER_UCAST = 0x00000001, /* Allow unicast frames */ 393 HAL_RX_FILTER_MCAST = 0x00000002, /* Allow multicast frames */ 394 HAL_RX_FILTER_BCAST = 0x00000004, /* Allow broadcast frames */ 395 HAL_RX_FILTER_CONTROL = 0x00000008, /* Allow control frames */ 396 HAL_RX_FILTER_BEACON = 0x00000010, /* Allow beacon frames */ 397 HAL_RX_FILTER_PROM = 0x00000020, /* Promiscuous mode */ 398 HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */ 399 HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */ 400 HAL_RX_FILTER_COMPBAR = 0x00000400, /* Allow compressed BAR */ 401 HAL_RX_FILTER_COMP_BA = 0x00000800, /* Allow compressed blockack */ 402 HAL_RX_FILTER_PHYRADAR = 0x00002000, /* Allow phy radar errors */ 403 HAL_RX_FILTER_PSPOLL = 0x00004000, /* Allow PS-POLL frames */ 404 HAL_RX_FILTER_MCAST_BCAST_ALL = 0x00008000, 405 /* Allow all mcast/bcast frames */ 406 407 /* 408 * Magic RX filter flags that aren't targetting hardware bits 409 * but instead the HAL sets individual bits - eg PHYERR will result 410 * in OFDM/CCK timing error frames being received. 411 */ 412 HAL_RX_FILTER_BSSID = 0x40000000, /* Disable BSSID match */ 413 } HAL_RX_FILTER; 414 415 typedef enum { 416 HAL_PM_AWAKE = 0, 417 HAL_PM_FULL_SLEEP = 1, 418 HAL_PM_NETWORK_SLEEP = 2, 419 HAL_PM_UNDEFINED = 3 420 } HAL_POWER_MODE; 421 422 /* 423 * Enterprise mode flags 424 */ 425 #define AH_ENT_DUAL_BAND_DISABLE 0x00000001 426 #define AH_ENT_CHAIN2_DISABLE 0x00000002 427 #define AH_ENT_5MHZ_DISABLE 0x00000004 428 #define AH_ENT_10MHZ_DISABLE 0x00000008 429 #define AH_ENT_49GHZ_DISABLE 0x00000010 430 #define AH_ENT_LOOPBACK_DISABLE 0x00000020 431 #define AH_ENT_TPC_PERF_DISABLE 0x00000040 432 #define AH_ENT_MIN_PKT_SIZE_DISABLE 0x00000080 433 #define AH_ENT_SPECTRAL_PRECISION 0x00000300 434 #define AH_ENT_SPECTRAL_PRECISION_S 8 435 #define AH_ENT_RTSCTS_DELIM_WAR 0x00010000 436 437 #define AH_FIRST_DESC_NDELIMS 60 438 439 /* 440 * NOTE WELL: 441 * These are mapped to take advantage of the common locations for many of 442 * the bits on all of the currently supported MAC chips. This is to make 443 * the ISR as efficient as possible, while still abstracting HW differences. 444 * When new hardware breaks this commonality this enumerated type, as well 445 * as the HAL functions using it, must be modified. All values are directly 446 * mapped unless commented otherwise. 447 */ 448 typedef enum { 449 HAL_INT_RX = 0x00000001, /* Non-common mapping */ 450 HAL_INT_RXDESC = 0x00000002, /* Legacy mapping */ 451 HAL_INT_RXERR = 0x00000004, 452 HAL_INT_RXHP = 0x00000001, /* EDMA */ 453 HAL_INT_RXLP = 0x00000002, /* EDMA */ 454 HAL_INT_RXNOFRM = 0x00000008, 455 HAL_INT_RXEOL = 0x00000010, 456 HAL_INT_RXORN = 0x00000020, 457 HAL_INT_TX = 0x00000040, /* Non-common mapping */ 458 HAL_INT_TXDESC = 0x00000080, 459 HAL_INT_TIM_TIMER= 0x00000100, 460 HAL_INT_MCI = 0x00000200, 461 HAL_INT_BBPANIC = 0x00000400, 462 HAL_INT_TXURN = 0x00000800, 463 HAL_INT_MIB = 0x00001000, 464 HAL_INT_RXPHY = 0x00004000, 465 HAL_INT_RXKCM = 0x00008000, 466 HAL_INT_SWBA = 0x00010000, 467 HAL_INT_BRSSI = 0x00020000, 468 HAL_INT_BMISS = 0x00040000, 469 HAL_INT_BNR = 0x00100000, 470 HAL_INT_TIM = 0x00200000, /* Non-common mapping */ 471 HAL_INT_DTIM = 0x00400000, /* Non-common mapping */ 472 HAL_INT_DTIMSYNC= 0x00800000, /* Non-common mapping */ 473 HAL_INT_GPIO = 0x01000000, 474 HAL_INT_CABEND = 0x02000000, /* Non-common mapping */ 475 HAL_INT_TSFOOR = 0x04000000, /* Non-common mapping */ 476 HAL_INT_TBTT = 0x08000000, /* Non-common mapping */ 477 /* Atheros ref driver has a generic timer interrupt now..*/ 478 HAL_INT_GENTIMER = 0x08000000, /* Non-common mapping */ 479 HAL_INT_CST = 0x10000000, /* Non-common mapping */ 480 HAL_INT_GTT = 0x20000000, /* Non-common mapping */ 481 HAL_INT_FATAL = 0x40000000, /* Non-common mapping */ 482 #define HAL_INT_GLOBAL 0x80000000 /* Set/clear IER */ 483 HAL_INT_BMISC = HAL_INT_TIM 484 | HAL_INT_DTIM 485 | HAL_INT_DTIMSYNC 486 | HAL_INT_CABEND 487 | HAL_INT_TBTT, 488 489 /* Interrupt bits that map directly to ISR/IMR bits */ 490 HAL_INT_COMMON = HAL_INT_RXNOFRM 491 | HAL_INT_RXDESC 492 | HAL_INT_RXEOL 493 | HAL_INT_RXORN 494 | HAL_INT_TXDESC 495 | HAL_INT_TXURN 496 | HAL_INT_MIB 497 | HAL_INT_RXPHY 498 | HAL_INT_RXKCM 499 | HAL_INT_SWBA 500 | HAL_INT_BMISS 501 | HAL_INT_BRSSI 502 | HAL_INT_BNR 503 | HAL_INT_GPIO, 504 } HAL_INT; 505 506 /* 507 * MSI vector assignments 508 */ 509 typedef enum { 510 HAL_MSIVEC_MISC = 0, 511 HAL_MSIVEC_TX = 1, 512 HAL_MSIVEC_RXLP = 2, 513 HAL_MSIVEC_RXHP = 3, 514 } HAL_MSIVEC; 515 516 typedef enum { 517 HAL_INT_LINE = 0, 518 HAL_INT_MSI = 1, 519 } HAL_INT_TYPE; 520 521 /* For interrupt mitigation registers */ 522 typedef enum { 523 HAL_INT_RX_FIRSTPKT=0, 524 HAL_INT_RX_LASTPKT, 525 HAL_INT_TX_FIRSTPKT, 526 HAL_INT_TX_LASTPKT, 527 HAL_INT_THRESHOLD 528 } HAL_INT_MITIGATION; 529 530 /* XXX this is duplicate information! */ 531 typedef struct { 532 u_int32_t cyclecnt_diff; /* delta cycle count */ 533 u_int32_t rxclr_cnt; /* rx clear count */ 534 u_int32_t txframecnt_diff; /* delta tx frame count */ 535 u_int32_t rxframecnt_diff; /* delta rx frame count */ 536 u_int32_t listen_time; /* listen time in msec - time for which ch is free */ 537 u_int32_t ofdmphyerr_cnt; /* OFDM err count since last reset */ 538 u_int32_t cckphyerr_cnt; /* CCK err count since last reset */ 539 u_int32_t ofdmphyerrcnt_diff; /* delta OFDM Phy Error Count */ 540 HAL_BOOL valid; /* if the stats are valid*/ 541 } HAL_ANISTATS; 542 543 typedef struct { 544 u_int8_t txctl_offset; 545 u_int8_t txctl_numwords; 546 u_int8_t txstatus_offset; 547 u_int8_t txstatus_numwords; 548 549 u_int8_t rxctl_offset; 550 u_int8_t rxctl_numwords; 551 u_int8_t rxstatus_offset; 552 u_int8_t rxstatus_numwords; 553 554 u_int8_t macRevision; 555 } HAL_DESC_INFO; 556 557 typedef enum { 558 HAL_GPIO_OUTPUT_MUX_AS_OUTPUT = 0, 559 HAL_GPIO_OUTPUT_MUX_PCIE_ATTENTION_LED = 1, 560 HAL_GPIO_OUTPUT_MUX_PCIE_POWER_LED = 2, 561 HAL_GPIO_OUTPUT_MUX_MAC_NETWORK_LED = 3, 562 HAL_GPIO_OUTPUT_MUX_MAC_POWER_LED = 4, 563 HAL_GPIO_OUTPUT_MUX_AS_WLAN_ACTIVE = 5, 564 HAL_GPIO_OUTPUT_MUX_AS_TX_FRAME = 6 565 } HAL_GPIO_MUX_TYPE; 566 567 typedef enum { 568 HAL_GPIO_INTR_LOW = 0, 569 HAL_GPIO_INTR_HIGH = 1, 570 HAL_GPIO_INTR_DISABLE = 2 571 } HAL_GPIO_INTR_TYPE; 572 573 typedef struct halCounters { 574 u_int32_t tx_frame_count; 575 u_int32_t rx_frame_count; 576 u_int32_t rx_clear_count; 577 u_int32_t cycle_count; 578 u_int8_t is_rx_active; // true (1) or false (0) 579 u_int8_t is_tx_active; // true (1) or false (0) 580 } HAL_COUNTERS; 581 582 typedef enum { 583 HAL_RFGAIN_INACTIVE = 0, 584 HAL_RFGAIN_READ_REQUESTED = 1, 585 HAL_RFGAIN_NEED_CHANGE = 2 586 } HAL_RFGAIN; 587 588 typedef uint16_t HAL_CTRY_CODE; /* country code */ 589 typedef uint16_t HAL_REG_DOMAIN; /* regulatory domain code */ 590 591 #define HAL_ANTENNA_MIN_MODE 0 592 #define HAL_ANTENNA_FIXED_A 1 593 #define HAL_ANTENNA_FIXED_B 2 594 #define HAL_ANTENNA_MAX_MODE 3 595 596 typedef struct { 597 uint32_t ackrcv_bad; 598 uint32_t rts_bad; 599 uint32_t rts_good; 600 uint32_t fcs_bad; 601 uint32_t beacons; 602 } HAL_MIB_STATS; 603 604 /* 605 * These bits represent what's in ah_currentRDext. 606 */ 607 typedef enum { 608 REG_EXT_FCC_MIDBAND = 0, 609 REG_EXT_JAPAN_MIDBAND = 1, 610 REG_EXT_FCC_DFS_HT40 = 2, 611 REG_EXT_JAPAN_NONDFS_HT40 = 3, 612 REG_EXT_JAPAN_DFS_HT40 = 4 613 } REG_EXT_BITMAP; 614 615 enum { 616 HAL_MODE_11A = 0x001, /* 11a channels */ 617 HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */ 618 HAL_MODE_11B = 0x004, /* 11b channels */ 619 HAL_MODE_PUREG = 0x008, /* 11g channels (OFDM only) */ 620 #ifdef notdef 621 HAL_MODE_11G = 0x010, /* 11g channels (OFDM/CCK) */ 622 #else 623 HAL_MODE_11G = 0x008, /* XXX historical */ 624 #endif 625 HAL_MODE_108G = 0x020, /* 11g+Turbo channels */ 626 HAL_MODE_108A = 0x040, /* 11a+Turbo channels */ 627 HAL_MODE_11A_HALF_RATE = 0x200, /* 11a half width channels */ 628 HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11a quarter width channels */ 629 HAL_MODE_11G_HALF_RATE = 0x800, /* 11g half width channels */ 630 HAL_MODE_11G_QUARTER_RATE = 0x1000, /* 11g quarter width channels */ 631 HAL_MODE_11NG_HT20 = 0x008000, 632 HAL_MODE_11NA_HT20 = 0x010000, 633 HAL_MODE_11NG_HT40PLUS = 0x020000, 634 HAL_MODE_11NG_HT40MINUS = 0x040000, 635 HAL_MODE_11NA_HT40PLUS = 0x080000, 636 HAL_MODE_11NA_HT40MINUS = 0x100000, 637 HAL_MODE_ALL = 0xffffff 638 }; 639 640 typedef struct { 641 int rateCount; /* NB: for proper padding */ 642 uint8_t rateCodeToIndex[256]; /* back mapping */ 643 struct { 644 uint8_t valid; /* valid for rate control use */ 645 uint8_t phy; /* CCK/OFDM/XR */ 646 uint32_t rateKbps; /* transfer rate in kbs */ 647 uint8_t rateCode; /* rate for h/w descriptors */ 648 uint8_t shortPreamble; /* mask for enabling short 649 * preamble in CCK rate code */ 650 uint8_t dot11Rate; /* value for supported rates 651 * info element of MLME */ 652 uint8_t controlRate; /* index of next lower basic 653 * rate; used for dur. calcs */ 654 uint16_t lpAckDuration; /* long preamble ACK duration */ 655 uint16_t spAckDuration; /* short preamble ACK duration*/ 656 } info[64]; 657 } HAL_RATE_TABLE; 658 659 typedef struct { 660 u_int rs_count; /* number of valid entries */ 661 uint8_t rs_rates[64]; /* rates */ 662 } HAL_RATE_SET; 663 664 /* 665 * 802.11n specific structures and enums 666 */ 667 typedef enum { 668 HAL_CHAINTYPE_TX = 1, /* Tx chain type */ 669 HAL_CHAINTYPE_RX = 2, /* RX chain type */ 670 } HAL_CHAIN_TYPE; 671 672 typedef struct { 673 u_int Tries; 674 u_int Rate; /* hardware rate code */ 675 u_int RateIndex; /* rate series table index */ 676 u_int PktDuration; 677 u_int ChSel; 678 u_int RateFlags; 679 #define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */ 680 #define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */ 681 #define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */ 682 #define HAL_RATESERIES_STBC 0x0008 /* use STBC for series */ 683 u_int tx_power_cap; /* in 1/2 dBm units XXX TODO */ 684 } HAL_11N_RATE_SERIES; 685 686 typedef enum { 687 HAL_HT_MACMODE_20 = 0, /* 20 MHz operation */ 688 HAL_HT_MACMODE_2040 = 1, /* 20/40 MHz operation */ 689 } HAL_HT_MACMODE; 690 691 typedef enum { 692 HAL_HT_PHYMODE_20 = 0, /* 20 MHz operation */ 693 HAL_HT_PHYMODE_2040 = 1, /* 20/40 MHz operation */ 694 } HAL_HT_PHYMODE; 695 696 typedef enum { 697 HAL_HT_EXTPROTSPACING_20 = 0, /* 20 MHz spacing */ 698 HAL_HT_EXTPROTSPACING_25 = 1, /* 25 MHz spacing */ 699 } HAL_HT_EXTPROTSPACING; 700 701 702 typedef enum { 703 HAL_RX_CLEAR_CTL_LOW = 0x1, /* force control channel to appear busy */ 704 HAL_RX_CLEAR_EXT_LOW = 0x2, /* force extension channel to appear busy */ 705 } HAL_HT_RXCLEAR; 706 707 typedef enum { 708 HAL_FREQ_BAND_5GHZ = 0, 709 HAL_FREQ_BAND_2GHZ = 1, 710 } HAL_FREQ_BAND; 711 712 /* 713 * Antenna switch control. By default antenna selection 714 * enables multiple (2) antenna use. To force use of the 715 * A or B antenna only specify a fixed setting. Fixing 716 * the antenna will also disable any diversity support. 717 */ 718 typedef enum { 719 HAL_ANT_VARIABLE = 0, /* variable by programming */ 720 HAL_ANT_FIXED_A = 1, /* fixed antenna A */ 721 HAL_ANT_FIXED_B = 2, /* fixed antenna B */ 722 } HAL_ANT_SETTING; 723 724 typedef enum { 725 HAL_M_STA = 1, /* infrastructure station */ 726 HAL_M_IBSS = 0, /* IBSS (adhoc) station */ 727 HAL_M_HOSTAP = 6, /* Software Access Point */ 728 HAL_M_MONITOR = 8 /* Monitor mode */ 729 } HAL_OPMODE; 730 731 typedef struct { 732 uint8_t kv_type; /* one of HAL_CIPHER */ 733 uint8_t kv_apsd; /* Mask for APSD enabled ACs */ 734 uint16_t kv_len; /* length in bits */ 735 uint8_t kv_val[16]; /* enough for 128-bit keys */ 736 uint8_t kv_mic[8]; /* TKIP MIC key */ 737 uint8_t kv_txmic[8]; /* TKIP TX MIC key (optional) */ 738 } HAL_KEYVAL; 739 740 /* 741 * This is the TX descriptor field which marks the key padding requirement. 742 * The naming is unfortunately unclear. 743 */ 744 #define AH_KEYTYPE_MASK 0x0F 745 typedef enum { 746 HAL_KEY_TYPE_CLEAR, 747 HAL_KEY_TYPE_WEP, 748 HAL_KEY_TYPE_AES, 749 HAL_KEY_TYPE_TKIP, 750 } HAL_KEY_TYPE; 751 752 typedef enum { 753 HAL_CIPHER_WEP = 0, 754 HAL_CIPHER_AES_OCB = 1, 755 HAL_CIPHER_AES_CCM = 2, 756 HAL_CIPHER_CKIP = 3, 757 HAL_CIPHER_TKIP = 4, 758 HAL_CIPHER_CLR = 5, /* no encryption */ 759 760 HAL_CIPHER_MIC = 127 /* TKIP-MIC, not a cipher */ 761 } HAL_CIPHER; 762 763 enum { 764 HAL_SLOT_TIME_6 = 6, /* NB: for turbo mode */ 765 HAL_SLOT_TIME_9 = 9, 766 HAL_SLOT_TIME_20 = 20, 767 }; 768 769 /* 770 * Per-station beacon timer state. Note that the specified 771 * beacon interval (given in TU's) can also include flags 772 * to force a TSF reset and to enable the beacon xmit logic. 773 * If bs_cfpmaxduration is non-zero the hardware is setup to 774 * coexist with a PCF-capable AP. 775 */ 776 typedef struct { 777 uint32_t bs_nexttbtt; /* next beacon in TU */ 778 uint32_t bs_nextdtim; /* next DTIM in TU */ 779 uint32_t bs_intval; /* beacon interval+flags */ 780 #define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */ 781 #define HAL_BEACON_PERIOD_TU8 0x0007ffff /* beacon interval, tu/8 */ 782 #define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */ 783 #define HAL_BEACON_RESET_TSF 0x01000000 /* clear TSF */ 784 #define HAL_TSFOOR_THRESHOLD 0x00004240 /* TSF OOR thresh (16k uS) */ 785 uint32_t bs_dtimperiod; 786 uint16_t bs_cfpperiod; /* CFP period in TU */ 787 uint16_t bs_cfpmaxduration; /* max CFP duration in TU */ 788 uint32_t bs_cfpnext; /* next CFP in TU */ 789 uint16_t bs_timoffset; /* byte offset to TIM bitmap */ 790 uint16_t bs_bmissthreshold; /* beacon miss threshold */ 791 uint32_t bs_sleepduration; /* max sleep duration */ 792 uint32_t bs_tsfoor_threshold; /* TSF out of range threshold */ 793 } HAL_BEACON_STATE; 794 795 /* 796 * Like HAL_BEACON_STATE but for non-station mode setup. 797 * NB: see above flag definitions for bt_intval. 798 */ 799 typedef struct { 800 uint32_t bt_intval; /* beacon interval+flags */ 801 uint32_t bt_nexttbtt; /* next beacon in TU */ 802 uint32_t bt_nextatim; /* next ATIM in TU */ 803 uint32_t bt_nextdba; /* next DBA in 1/8th TU */ 804 uint32_t bt_nextswba; /* next SWBA in 1/8th TU */ 805 uint32_t bt_flags; /* timer enables */ 806 #define HAL_BEACON_TBTT_EN 0x00000001 807 #define HAL_BEACON_DBA_EN 0x00000002 808 #define HAL_BEACON_SWBA_EN 0x00000004 809 } HAL_BEACON_TIMERS; 810 811 /* 812 * Per-node statistics maintained by the driver for use in 813 * optimizing signal quality and other operational aspects. 814 */ 815 typedef struct { 816 uint32_t ns_avgbrssi; /* average beacon rssi */ 817 uint32_t ns_avgrssi; /* average data rssi */ 818 uint32_t ns_avgtxrssi; /* average tx rssi */ 819 } HAL_NODE_STATS; 820 821 #define HAL_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */ 822 823 824 struct ath_desc; 825 struct ath_tx_status; 826 struct ath_rx_status; 827 struct ieee80211_channel; 828 829 /* 830 * This is a channel survey sample entry. 831 * 832 * The AR5212 ANI routines fill these samples. The ANI code then uses it 833 * when calculating listen time; it is also exported via a diagnostic 834 * API. 835 */ 836 typedef struct { 837 uint32_t seq_num; 838 uint32_t tx_busy; 839 uint32_t rx_busy; 840 uint32_t chan_busy; 841 uint32_t ext_chan_busy; 842 uint32_t cycle_count; 843 /* XXX TODO */ 844 uint32_t ofdm_phyerr_count; 845 uint32_t cck_phyerr_count; 846 } HAL_SURVEY_SAMPLE; 847 848 /* 849 * This provides 3.2 seconds of sample space given an 850 * ANI time of 1/10th of a second. This may not be enough! 851 */ 852 #define CHANNEL_SURVEY_SAMPLE_COUNT 32 853 854 typedef struct { 855 HAL_SURVEY_SAMPLE samples[CHANNEL_SURVEY_SAMPLE_COUNT]; 856 uint32_t cur_sample; /* current sample in sequence */ 857 uint32_t cur_seq; /* current sequence number */ 858 } HAL_CHANNEL_SURVEY; 859 860 /* 861 * ANI commands. 862 * 863 * These are used both internally and externally via the diagnostic 864 * API. 865 * 866 * Note that this is NOT the ANI commands being used via the INTMIT 867 * capability - that has a different mapping for some reason. 868 */ 869 typedef enum { 870 HAL_ANI_PRESENT = 0, /* is ANI support present */ 871 HAL_ANI_NOISE_IMMUNITY_LEVEL = 1, /* set level */ 872 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION = 2, /* enable/disable */ 873 HAL_ANI_CCK_WEAK_SIGNAL_THR = 3, /* enable/disable */ 874 HAL_ANI_FIRSTEP_LEVEL = 4, /* set level */ 875 HAL_ANI_SPUR_IMMUNITY_LEVEL = 5, /* set level */ 876 HAL_ANI_MODE = 6, /* 0 => manual, 1 => auto (XXX do not change) */ 877 HAL_ANI_PHYERR_RESET = 7, /* reset phy error stats */ 878 HAL_ANI_MRC_CCK = 8, 879 } HAL_ANI_CMD; 880 881 #define HAL_ANI_ALL 0xffffffff 882 883 /* 884 * This is the layout of the ANI INTMIT capability. 885 * 886 * Notice that the command values differ to HAL_ANI_CMD. 887 */ 888 typedef enum { 889 HAL_CAP_INTMIT_PRESENT = 0, 890 HAL_CAP_INTMIT_ENABLE = 1, 891 HAL_CAP_INTMIT_NOISE_IMMUNITY_LEVEL = 2, 892 HAL_CAP_INTMIT_OFDM_WEAK_SIGNAL_LEVEL = 3, 893 HAL_CAP_INTMIT_CCK_WEAK_SIGNAL_THR = 4, 894 HAL_CAP_INTMIT_FIRSTEP_LEVEL = 5, 895 HAL_CAP_INTMIT_SPUR_IMMUNITY_LEVEL = 6 896 } HAL_CAP_INTMIT_CMD; 897 898 typedef struct { 899 int32_t pe_firpwr; /* FIR pwr out threshold */ 900 int32_t pe_rrssi; /* Radar rssi thresh */ 901 int32_t pe_height; /* Pulse height thresh */ 902 int32_t pe_prssi; /* Pulse rssi thresh */ 903 int32_t pe_inband; /* Inband thresh */ 904 905 /* The following params are only for AR5413 and later */ 906 u_int32_t pe_relpwr; /* Relative power threshold in 0.5dB steps */ 907 u_int32_t pe_relstep; /* Pulse Relative step threshold in 0.5dB steps */ 908 u_int32_t pe_maxlen; /* Max length of radar sign in 0.8us units */ 909 int32_t pe_usefir128; /* Use the average in-band power measured over 128 cycles */ 910 int32_t pe_blockradar; /* 911 * Enable to block radar check if pkt detect is done via OFDM 912 * weak signal detect or pkt is detected immediately after tx 913 * to rx transition 914 */ 915 int32_t pe_enmaxrssi; /* 916 * Enable to use the max rssi instead of the last rssi during 917 * fine gain changes for radar detection 918 */ 919 int32_t pe_extchannel; /* Enable DFS on ext channel */ 920 int32_t pe_enabled; /* Whether radar detection is enabled */ 921 int32_t pe_enrelpwr; 922 int32_t pe_en_relstep_check; 923 } HAL_PHYERR_PARAM; 924 925 #define HAL_PHYERR_PARAM_NOVAL 65535 926 927 /* 928 * DFS operating mode flags. 929 */ 930 typedef enum { 931 HAL_DFS_UNINIT_DOMAIN = 0, /* Uninitialized dfs domain */ 932 HAL_DFS_FCC_DOMAIN = 1, /* FCC3 dfs domain */ 933 HAL_DFS_ETSI_DOMAIN = 2, /* ETSI dfs domain */ 934 HAL_DFS_MKK4_DOMAIN = 3, /* Japan dfs domain */ 935 } HAL_DFS_DOMAIN; 936 937 938 /* 939 * MFP decryption options for initializing the MAC. 940 */ 941 typedef enum { 942 HAL_MFP_QOSDATA = 0, /* Decrypt MFP frames like QoS data frames. All chips before Merlin. */ 943 HAL_MFP_PASSTHRU, /* Don't decrypt MFP frames at all. Passthrough */ 944 HAL_MFP_HW_CRYPTO /* hardware decryption enabled. Merlin can do it. */ 945 } HAL_MFP_OPT_T; 946 947 /* LNA config supported */ 948 typedef enum { 949 HAL_ANT_DIV_COMB_LNA1_MINUS_LNA2 = 0, 950 HAL_ANT_DIV_COMB_LNA2 = 1, 951 HAL_ANT_DIV_COMB_LNA1 = 2, 952 HAL_ANT_DIV_COMB_LNA1_PLUS_LNA2 = 3, 953 } HAL_ANT_DIV_COMB_LNA_CONF; 954 955 typedef struct { 956 u_int8_t main_lna_conf; 957 u_int8_t alt_lna_conf; 958 u_int8_t fast_div_bias; 959 u_int8_t main_gaintb; 960 u_int8_t alt_gaintb; 961 u_int8_t antdiv_configgroup; 962 int8_t lna1_lna2_delta; 963 } HAL_ANT_COMB_CONFIG; 964 965 #define DEFAULT_ANTDIV_CONFIG_GROUP 0x00 966 #define HAL_ANTDIV_CONFIG_GROUP_1 0x01 967 #define HAL_ANTDIV_CONFIG_GROUP_2 0x02 968 #define HAL_ANTDIV_CONFIG_GROUP_3 0x03 969 970 /* 971 * Flag for setting QUIET period 972 */ 973 typedef enum { 974 HAL_QUIET_DISABLE = 0x0, 975 HAL_QUIET_ENABLE = 0x1, 976 HAL_QUIET_ADD_CURRENT_TSF = 0x2, /* add current TSF to next_start offset */ 977 HAL_QUIET_ADD_SWBA_RESP_TIME = 0x4, /* add beacon response time to next_start offset */ 978 } HAL_QUIET_FLAG; 979 980 #define HAL_DFS_EVENT_PRICH 0x0000001 981 #define HAL_DFS_EVENT_EXTCH 0x0000002 982 #define HAL_DFS_EVENT_EXTEARLY 0x0000004 983 #define HAL_DFS_EVENT_ISDC 0x0000008 984 985 struct hal_dfs_event { 986 uint64_t re_full_ts; /* 64-bit full timestamp from interrupt time */ 987 uint32_t re_ts; /* Original 15 bit recv timestamp */ 988 uint8_t re_rssi; /* rssi of radar event */ 989 uint8_t re_dur; /* duration of radar pulse */ 990 uint32_t re_flags; /* Flags (see above) */ 991 }; 992 typedef struct hal_dfs_event HAL_DFS_EVENT; 993 994 /* 995 * Generic Timer domain 996 */ 997 typedef enum { 998 HAL_GEN_TIMER_TSF = 0, 999 HAL_GEN_TIMER_TSF2, 1000 HAL_GEN_TIMER_TSF_ANY 1001 } HAL_GEN_TIMER_DOMAIN; 1002 1003 typedef enum { 1004 HAL_RESET_NONE = 0x0, 1005 HAL_RESET_BBPANIC = 0x1, 1006 } HAL_RESET_TYPE; 1007 1008 /* 1009 * BT Co-existence definitions 1010 */ 1011 typedef enum { 1012 HAL_BT_MODULE_CSR_BC4 = 0, /* CSR BlueCore v4 */ 1013 HAL_BT_MODULE_JANUS = 1, /* Kite + Valkyrie combo */ 1014 HAL_BT_MODULE_HELIUS = 2, /* Kiwi + Valkyrie combo */ 1015 HAL_MAX_BT_MODULES 1016 } HAL_BT_MODULE; 1017 1018 typedef struct { 1019 HAL_BT_MODULE bt_module; 1020 u_int8_t bt_coex_config; 1021 u_int8_t bt_gpio_bt_active; 1022 u_int8_t bt_gpio_bt_priority; 1023 u_int8_t bt_gpio_wlan_active; 1024 u_int8_t bt_active_polarity; 1025 HAL_BOOL bt_single_ant; 1026 u_int8_t bt_dutyCycle; 1027 u_int8_t bt_isolation; 1028 u_int8_t bt_period; 1029 } HAL_BT_COEX_INFO; 1030 1031 typedef enum { 1032 HAL_BT_COEX_MODE_LEGACY = 0, /* legacy rx_clear mode */ 1033 HAL_BT_COEX_MODE_UNSLOTTED = 1, /* untimed/unslotted mode */ 1034 HAL_BT_COEX_MODE_SLOTTED = 2, /* slotted mode */ 1035 HAL_BT_COEX_MODE_DISALBED = 3, /* coexistence disabled */ 1036 } HAL_BT_COEX_MODE; 1037 1038 typedef enum { 1039 HAL_BT_COEX_CFG_NONE, /* No bt coex enabled */ 1040 HAL_BT_COEX_CFG_2WIRE_2CH, /* 2-wire with 2 chains */ 1041 HAL_BT_COEX_CFG_2WIRE_CH1, /* 2-wire with ch1 */ 1042 HAL_BT_COEX_CFG_2WIRE_CH0, /* 2-wire with ch0 */ 1043 HAL_BT_COEX_CFG_3WIRE, /* 3-wire */ 1044 HAL_BT_COEX_CFG_MCI /* MCI */ 1045 } HAL_BT_COEX_CFG; 1046 1047 typedef enum { 1048 HAL_BT_COEX_SET_ACK_PWR = 0, /* Change ACK power setting */ 1049 HAL_BT_COEX_LOWER_TX_PWR, /* Change transmit power */ 1050 HAL_BT_COEX_ANTENNA_DIVERSITY, /* Enable RX diversity for Kite */ 1051 } HAL_BT_COEX_SET_PARAMETER; 1052 1053 #define HAL_BT_COEX_FLAG_LOW_ACK_PWR 0x00000001 1054 #define HAL_BT_COEX_FLAG_LOWER_TX_PWR 0x00000002 1055 /* Check Rx Diversity is allowed */ 1056 #define HAL_BT_COEX_FLAG_ANT_DIV_ALLOW 0x00000004 1057 /* Check Diversity is on or off */ 1058 #define HAL_BT_COEX_FLAG_ANT_DIV_ENABLE 0x00000008 1059 1060 #define HAL_BT_COEX_ANTDIV_CONTROL1_ENABLE 0x0b 1061 /* main: LNA1, alt: LNA2 */ 1062 #define HAL_BT_COEX_ANTDIV_CONTROL2_ENABLE 0x09 1063 #define HAL_BT_COEX_ANTDIV_CONTROL1_FIXED_A 0x04 1064 #define HAL_BT_COEX_ANTDIV_CONTROL2_FIXED_A 0x09 1065 #define HAL_BT_COEX_ANTDIV_CONTROL1_FIXED_B 0x02 1066 #define HAL_BT_COEX_ANTDIV_CONTROL2_FIXED_B 0x06 1067 1068 #define HAL_BT_COEX_ISOLATION_FOR_NO_COEX 30 1069 1070 #define HAL_BT_COEX_ANT_DIV_SWITCH_COM 0x66666666 1071 1072 #define HAL_BT_COEX_HELIUS_CHAINMASK 0x02 1073 1074 #define HAL_BT_COEX_LOW_ACK_POWER 0x0 1075 #define HAL_BT_COEX_HIGH_ACK_POWER 0x3f3f3f 1076 1077 typedef enum { 1078 HAL_BT_COEX_NO_STOMP = 0, 1079 HAL_BT_COEX_STOMP_ALL, 1080 HAL_BT_COEX_STOMP_LOW, 1081 HAL_BT_COEX_STOMP_NONE, 1082 HAL_BT_COEX_STOMP_ALL_FORCE, 1083 HAL_BT_COEX_STOMP_LOW_FORCE, 1084 } HAL_BT_COEX_STOMP_TYPE; 1085 1086 typedef struct { 1087 /* extend rx_clear after tx/rx to protect the burst (in usec). */ 1088 u_int8_t bt_time_extend; 1089 1090 /* 1091 * extend rx_clear as long as txsm is 1092 * transmitting or waiting for ack. 1093 */ 1094 HAL_BOOL bt_txstate_extend; 1095 1096 /* 1097 * extend rx_clear so that when tx_frame 1098 * is asserted, rx_clear will drop. 1099 */ 1100 HAL_BOOL bt_txframe_extend; 1101 1102 /* 1103 * coexistence mode 1104 */ 1105 HAL_BT_COEX_MODE bt_mode; 1106 1107 /* 1108 * treat BT high priority traffic as 1109 * a quiet collision 1110 */ 1111 HAL_BOOL bt_quiet_collision; 1112 1113 /* 1114 * invert rx_clear as WLAN_ACTIVE 1115 */ 1116 HAL_BOOL bt_rxclear_polarity; 1117 1118 /* 1119 * slotted mode only. indicate the time in usec 1120 * from the rising edge of BT_ACTIVE to the time 1121 * BT_PRIORITY can be sampled to indicate priority. 1122 */ 1123 u_int8_t bt_priority_time; 1124 1125 /* 1126 * slotted mode only. indicate the time in usec 1127 * from the rising edge of BT_ACTIVE to the time 1128 * BT_PRIORITY can be sampled to indicate tx/rx and 1129 * BT_FREQ is sampled. 1130 */ 1131 u_int8_t bt_first_slot_time; 1132 1133 /* 1134 * slotted mode only. rx_clear and bt_ant decision 1135 * will be held the entire time that BT_ACTIVE is asserted, 1136 * otherwise the decision is made before every slot boundry. 1137 */ 1138 HAL_BOOL bt_hold_rxclear; 1139 } HAL_BT_COEX_CONFIG; 1140 1141 struct hal_bb_panic_info { 1142 u_int32_t status; 1143 u_int32_t tsf; 1144 u_int32_t phy_panic_wd_ctl1; 1145 u_int32_t phy_panic_wd_ctl2; 1146 u_int32_t phy_gen_ctrl; 1147 u_int32_t rxc_pcnt; 1148 u_int32_t rxf_pcnt; 1149 u_int32_t txf_pcnt; 1150 u_int32_t cycles; 1151 u_int32_t wd; 1152 u_int32_t det; 1153 u_int32_t rdar; 1154 u_int32_t r_odfm; 1155 u_int32_t r_cck; 1156 u_int32_t t_odfm; 1157 u_int32_t t_cck; 1158 u_int32_t agc; 1159 u_int32_t src; 1160 }; 1161 1162 /* Serialize Register Access Mode */ 1163 typedef enum { 1164 SER_REG_MODE_OFF = 0, 1165 SER_REG_MODE_ON = 1, 1166 SER_REG_MODE_AUTO = 2, 1167 } SER_REG_MODE; 1168 1169 typedef struct 1170 { 1171 int ah_debug; /* only used if AH_DEBUG is defined */ 1172 int ah_ar5416_biasadj; /* enable AR2133 radio specific bias fiddling */ 1173 1174 /* NB: these are deprecated; they exist for now for compatibility */ 1175 int ah_dma_beacon_response_time;/* in TU's */ 1176 int ah_sw_beacon_response_time; /* in TU's */ 1177 int ah_additional_swba_backoff; /* in TU's */ 1178 int ah_force_full_reset; /* force full chip reset rather then warm reset */ 1179 int ah_serialise_reg_war; /* force serialisation of register IO */ 1180 1181 /* XXX these don't belong here, they're just for the ar9300 HAL port effort */ 1182 int ath_hal_desc_tpc; /* Per-packet TPC */ 1183 int ath_hal_sta_update_tx_pwr_enable; /* GreenTX */ 1184 int ath_hal_sta_update_tx_pwr_enable_S1; /* GreenTX */ 1185 int ath_hal_sta_update_tx_pwr_enable_S2; /* GreenTX */ 1186 int ath_hal_sta_update_tx_pwr_enable_S3; /* GreenTX */ 1187 1188 /* I'm not sure what the default values for these should be */ 1189 int ath_hal_pll_pwr_save; 1190 int ath_hal_pcie_power_save_enable; 1191 int ath_hal_intr_mitigation_rx; 1192 int ath_hal_intr_mitigation_tx; 1193 1194 int ath_hal_pcie_clock_req; 1195 #define AR_PCIE_PLL_PWRSAVE_CONTROL (1<<0) 1196 #define AR_PCIE_PLL_PWRSAVE_ON_D3 (1<<1) 1197 #define AR_PCIE_PLL_PWRSAVE_ON_D0 (1<<2) 1198 1199 int ath_hal_pcie_waen; 1200 int ath_hal_pcie_ser_des_write; 1201 1202 /* these are important for correct AR9300 behaviour */ 1203 int ath_hal_ht_enable; /* needs to be enabled for AR9300 HT */ 1204 int ath_hal_diversity_control; 1205 int ath_hal_antenna_switch_swap; 1206 int ath_hal_ext_lna_ctl_gpio; 1207 int ath_hal_spur_mode; 1208 int ath_hal_6mb_ack; /* should set this to 1 for 11a/11na? */ 1209 int ath_hal_enable_msi; /* enable MSI interrupts (needed?) */ 1210 int ath_hal_beacon_filter_interval; /* ok to be 0 for now? */ 1211 1212 /* For now, set this to 0 - net80211 needs to know about hardware MFP support */ 1213 int ath_hal_mfp_support; 1214 1215 int ath_hal_enable_ani; /* should set this.. */ 1216 int ath_hal_cwm_ignore_ext_cca; 1217 int ath_hal_show_bb_panic; 1218 } HAL_OPS_CONFIG; 1219 1220 /* 1221 * Hardware Access Layer (HAL) API. 1222 * 1223 * Clients of the HAL call ath_hal_attach to obtain a reference to an 1224 * ath_hal structure for use with the device. Hardware-related operations 1225 * that follow must call back into the HAL through interface, supplying 1226 * the reference as the first parameter. Note that before using the 1227 * reference returned by ath_hal_attach the caller should verify the 1228 * ABI version number. 1229 */ 1230 struct ath_hal { 1231 uint32_t ah_magic; /* consistency check magic number */ 1232 uint16_t ah_devid; /* PCI device ID */ 1233 uint16_t ah_subvendorid; /* PCI subvendor ID */ 1234 HAL_SOFTC ah_sc; /* back pointer to driver/os state */ 1235 HAL_BUS_TAG ah_st; /* params for register r+w */ 1236 HAL_BUS_HANDLE ah_sh; 1237 HAL_CTRY_CODE ah_countryCode; 1238 1239 uint32_t ah_macVersion; /* MAC version id */ 1240 uint16_t ah_macRev; /* MAC revision */ 1241 uint16_t ah_phyRev; /* PHY revision */ 1242 /* NB: when only one radio is present the rev is in 5Ghz */ 1243 uint16_t ah_analog5GhzRev;/* 5GHz radio revision */ 1244 uint16_t ah_analog2GhzRev;/* 2GHz radio revision */ 1245 1246 uint16_t *ah_eepromdata; /* eeprom buffer, if needed */ 1247 1248 uint32_t ah_intrstate[8]; /* last int state */ 1249 uint32_t ah_syncstate; /* last sync intr state */ 1250 1251 HAL_OPS_CONFIG ah_config; 1252 const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *, 1253 u_int mode); 1254 void __ahdecl(*ah_detach)(struct ath_hal*); 1255 1256 /* Reset functions */ 1257 HAL_BOOL __ahdecl(*ah_reset)(struct ath_hal *, HAL_OPMODE, 1258 struct ieee80211_channel *, 1259 HAL_BOOL bChannelChange, HAL_STATUS *status); 1260 HAL_BOOL __ahdecl(*ah_phyDisable)(struct ath_hal *); 1261 HAL_BOOL __ahdecl(*ah_disable)(struct ath_hal *); 1262 void __ahdecl(*ah_configPCIE)(struct ath_hal *, HAL_BOOL restore, 1263 HAL_BOOL power_off); 1264 void __ahdecl(*ah_disablePCIE)(struct ath_hal *); 1265 void __ahdecl(*ah_setPCUConfig)(struct ath_hal *); 1266 HAL_BOOL __ahdecl(*ah_perCalibration)(struct ath_hal*, 1267 struct ieee80211_channel *, HAL_BOOL *); 1268 HAL_BOOL __ahdecl(*ah_perCalibrationN)(struct ath_hal *, 1269 struct ieee80211_channel *, u_int chainMask, 1270 HAL_BOOL longCal, HAL_BOOL *isCalDone); 1271 HAL_BOOL __ahdecl(*ah_resetCalValid)(struct ath_hal *, 1272 const struct ieee80211_channel *); 1273 HAL_BOOL __ahdecl(*ah_setTxPower)(struct ath_hal *, 1274 const struct ieee80211_channel *, uint16_t *); 1275 HAL_BOOL __ahdecl(*ah_setTxPowerLimit)(struct ath_hal *, uint32_t); 1276 HAL_BOOL __ahdecl(*ah_setBoardValues)(struct ath_hal *, 1277 const struct ieee80211_channel *); 1278 1279 /* Transmit functions */ 1280 HAL_BOOL __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*, 1281 HAL_BOOL incTrigLevel); 1282 int __ahdecl(*ah_setupTxQueue)(struct ath_hal *, HAL_TX_QUEUE, 1283 const HAL_TXQ_INFO *qInfo); 1284 HAL_BOOL __ahdecl(*ah_setTxQueueProps)(struct ath_hal *, int q, 1285 const HAL_TXQ_INFO *qInfo); 1286 HAL_BOOL __ahdecl(*ah_getTxQueueProps)(struct ath_hal *, int q, 1287 HAL_TXQ_INFO *qInfo); 1288 HAL_BOOL __ahdecl(*ah_releaseTxQueue)(struct ath_hal *ah, u_int q); 1289 HAL_BOOL __ahdecl(*ah_resetTxQueue)(struct ath_hal *ah, u_int q); 1290 uint32_t __ahdecl(*ah_getTxDP)(struct ath_hal*, u_int); 1291 HAL_BOOL __ahdecl(*ah_setTxDP)(struct ath_hal*, u_int, uint32_t txdp); 1292 uint32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, u_int q); 1293 HAL_BOOL __ahdecl(*ah_startTxDma)(struct ath_hal*, u_int); 1294 HAL_BOOL __ahdecl(*ah_stopTxDma)(struct ath_hal*, u_int); 1295 HAL_BOOL __ahdecl(*ah_setupTxDesc)(struct ath_hal *, struct ath_desc *, 1296 u_int pktLen, u_int hdrLen, 1297 HAL_PKT_TYPE type, u_int txPower, 1298 u_int txRate0, u_int txTries0, 1299 u_int keyIx, u_int antMode, u_int flags, 1300 u_int rtsctsRate, u_int rtsctsDuration, 1301 u_int compicvLen, u_int compivLen, 1302 u_int comp); 1303 HAL_BOOL __ahdecl(*ah_setupXTxDesc)(struct ath_hal *, struct ath_desc*, 1304 u_int txRate1, u_int txTries1, 1305 u_int txRate2, u_int txTries2, 1306 u_int txRate3, u_int txTries3); 1307 HAL_BOOL __ahdecl(*ah_fillTxDesc)(struct ath_hal *, struct ath_desc *, 1308 HAL_DMA_ADDR *bufAddrList, uint32_t *segLenList, 1309 u_int descId, u_int qcuId, HAL_BOOL firstSeg, 1310 HAL_BOOL lastSeg, const struct ath_desc *); 1311 HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *, 1312 struct ath_desc *, struct ath_tx_status *); 1313 void __ahdecl(*ah_getTxIntrQueue)(struct ath_hal *, uint32_t *); 1314 void __ahdecl(*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc*); 1315 HAL_BOOL __ahdecl(*ah_getTxCompletionRates)(struct ath_hal *, 1316 const struct ath_desc *ds, int *rates, int *tries); 1317 void __ahdecl(*ah_setTxDescLink)(struct ath_hal *ah, void *ds, 1318 uint32_t link); 1319 void __ahdecl(*ah_getTxDescLink)(struct ath_hal *ah, void *ds, 1320 uint32_t *link); 1321 void __ahdecl(*ah_getTxDescLinkPtr)(struct ath_hal *ah, void *ds, 1322 uint32_t **linkptr); 1323 void __ahdecl(*ah_setupTxStatusRing)(struct ath_hal *, 1324 void *ts_start, uint32_t ts_paddr_start, 1325 uint16_t size); 1326 void __ahdecl(*ah_getTxRawTxDesc)(struct ath_hal *, u_int32_t *); 1327 1328 /* Receive Functions */ 1329 uint32_t __ahdecl(*ah_getRxDP)(struct ath_hal*, HAL_RX_QUEUE); 1330 void __ahdecl(*ah_setRxDP)(struct ath_hal*, uint32_t rxdp, HAL_RX_QUEUE); 1331 void __ahdecl(*ah_enableReceive)(struct ath_hal*); 1332 HAL_BOOL __ahdecl(*ah_stopDmaReceive)(struct ath_hal*); 1333 void __ahdecl(*ah_startPcuReceive)(struct ath_hal*); 1334 void __ahdecl(*ah_stopPcuReceive)(struct ath_hal*); 1335 void __ahdecl(*ah_setMulticastFilter)(struct ath_hal*, 1336 uint32_t filter0, uint32_t filter1); 1337 HAL_BOOL __ahdecl(*ah_setMulticastFilterIndex)(struct ath_hal*, 1338 uint32_t index); 1339 HAL_BOOL __ahdecl(*ah_clrMulticastFilterIndex)(struct ath_hal*, 1340 uint32_t index); 1341 uint32_t __ahdecl(*ah_getRxFilter)(struct ath_hal*); 1342 void __ahdecl(*ah_setRxFilter)(struct ath_hal*, uint32_t); 1343 HAL_BOOL __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_desc *, 1344 uint32_t size, u_int flags); 1345 HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *, 1346 struct ath_desc *, uint32_t phyAddr, 1347 struct ath_desc *next, uint64_t tsf, 1348 struct ath_rx_status *); 1349 void __ahdecl(*ah_rxMonitor)(struct ath_hal *, 1350 const HAL_NODE_STATS *, 1351 const struct ieee80211_channel *); 1352 void __ahdecl(*ah_aniPoll)(struct ath_hal *, 1353 const struct ieee80211_channel *); 1354 void __ahdecl(*ah_procMibEvent)(struct ath_hal *, 1355 const HAL_NODE_STATS *); 1356 void __ahdecl(*ah_rxAntCombDiversity)(struct ath_hal *, 1357 struct ath_rx_status *, 1358 unsigned long, int); 1359 1360 /* Misc Functions */ 1361 HAL_STATUS __ahdecl(*ah_getCapability)(struct ath_hal *, 1362 HAL_CAPABILITY_TYPE, uint32_t capability, 1363 uint32_t *result); 1364 HAL_BOOL __ahdecl(*ah_setCapability)(struct ath_hal *, 1365 HAL_CAPABILITY_TYPE, uint32_t capability, 1366 uint32_t setting, HAL_STATUS *); 1367 HAL_BOOL __ahdecl(*ah_getDiagState)(struct ath_hal *, int request, 1368 const void *args, uint32_t argsize, 1369 void **result, uint32_t *resultsize); 1370 void __ahdecl(*ah_getMacAddress)(struct ath_hal *, uint8_t *); 1371 HAL_BOOL __ahdecl(*ah_setMacAddress)(struct ath_hal *, const uint8_t*); 1372 void __ahdecl(*ah_getBssIdMask)(struct ath_hal *, uint8_t *); 1373 HAL_BOOL __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const uint8_t*); 1374 HAL_BOOL __ahdecl(*ah_setRegulatoryDomain)(struct ath_hal*, 1375 uint16_t, HAL_STATUS *); 1376 void __ahdecl(*ah_setLedState)(struct ath_hal*, HAL_LED_STATE); 1377 void __ahdecl(*ah_writeAssocid)(struct ath_hal*, 1378 const uint8_t *bssid, uint16_t assocId); 1379 HAL_BOOL __ahdecl(*ah_gpioCfgOutput)(struct ath_hal *, 1380 uint32_t gpio, HAL_GPIO_MUX_TYPE); 1381 HAL_BOOL __ahdecl(*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio); 1382 uint32_t __ahdecl(*ah_gpioGet)(struct ath_hal *, uint32_t gpio); 1383 HAL_BOOL __ahdecl(*ah_gpioSet)(struct ath_hal *, 1384 uint32_t gpio, uint32_t val); 1385 void __ahdecl(*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t); 1386 uint32_t __ahdecl(*ah_getTsf32)(struct ath_hal*); 1387 uint64_t __ahdecl(*ah_getTsf64)(struct ath_hal*); 1388 void __ahdecl(*ah_resetTsf)(struct ath_hal*); 1389 HAL_BOOL __ahdecl(*ah_detectCardPresent)(struct ath_hal*); 1390 void __ahdecl(*ah_updateMibCounters)(struct ath_hal*, 1391 HAL_MIB_STATS*); 1392 HAL_RFGAIN __ahdecl(*ah_getRfGain)(struct ath_hal*); 1393 u_int __ahdecl(*ah_getDefAntenna)(struct ath_hal*); 1394 void __ahdecl(*ah_setDefAntenna)(struct ath_hal*, u_int); 1395 HAL_ANT_SETTING __ahdecl(*ah_getAntennaSwitch)(struct ath_hal*); 1396 HAL_BOOL __ahdecl(*ah_setAntennaSwitch)(struct ath_hal*, 1397 HAL_ANT_SETTING); 1398 HAL_BOOL __ahdecl(*ah_setSifsTime)(struct ath_hal*, u_int); 1399 u_int __ahdecl(*ah_getSifsTime)(struct ath_hal*); 1400 HAL_BOOL __ahdecl(*ah_setSlotTime)(struct ath_hal*, u_int); 1401 u_int __ahdecl(*ah_getSlotTime)(struct ath_hal*); 1402 HAL_BOOL __ahdecl(*ah_setAckTimeout)(struct ath_hal*, u_int); 1403 u_int __ahdecl(*ah_getAckTimeout)(struct ath_hal*); 1404 HAL_BOOL __ahdecl(*ah_setAckCTSRate)(struct ath_hal*, u_int); 1405 u_int __ahdecl(*ah_getAckCTSRate)(struct ath_hal*); 1406 HAL_BOOL __ahdecl(*ah_setCTSTimeout)(struct ath_hal*, u_int); 1407 u_int __ahdecl(*ah_getCTSTimeout)(struct ath_hal*); 1408 HAL_BOOL __ahdecl(*ah_setDecompMask)(struct ath_hal*, uint16_t, int); 1409 void __ahdecl(*ah_setCoverageClass)(struct ath_hal*, uint8_t, int); 1410 HAL_STATUS __ahdecl(*ah_setQuiet)(struct ath_hal *ah, uint32_t period, 1411 uint32_t duration, uint32_t nextStart, 1412 HAL_QUIET_FLAG flag); 1413 1414 /* DFS functions */ 1415 void __ahdecl(*ah_enableDfs)(struct ath_hal *ah, 1416 HAL_PHYERR_PARAM *pe); 1417 void __ahdecl(*ah_getDfsThresh)(struct ath_hal *ah, 1418 HAL_PHYERR_PARAM *pe); 1419 HAL_BOOL __ahdecl(*ah_getDfsDefaultThresh)(struct ath_hal *ah, 1420 HAL_PHYERR_PARAM *pe); 1421 HAL_BOOL __ahdecl(*ah_procRadarEvent)(struct ath_hal *ah, 1422 struct ath_rx_status *rxs, uint64_t fulltsf, 1423 const char *buf, HAL_DFS_EVENT *event); 1424 HAL_BOOL __ahdecl(*ah_isFastClockEnabled)(struct ath_hal *ah); 1425 1426 /* Key Cache Functions */ 1427 uint32_t __ahdecl(*ah_getKeyCacheSize)(struct ath_hal*); 1428 HAL_BOOL __ahdecl(*ah_resetKeyCacheEntry)(struct ath_hal*, uint16_t); 1429 HAL_BOOL __ahdecl(*ah_isKeyCacheEntryValid)(struct ath_hal *, 1430 uint16_t); 1431 HAL_BOOL __ahdecl(*ah_setKeyCacheEntry)(struct ath_hal*, 1432 uint16_t, const HAL_KEYVAL *, 1433 const uint8_t *, int); 1434 HAL_BOOL __ahdecl(*ah_setKeyCacheEntryMac)(struct ath_hal*, 1435 uint16_t, const uint8_t *); 1436 1437 /* Power Management Functions */ 1438 HAL_BOOL __ahdecl(*ah_setPowerMode)(struct ath_hal*, 1439 HAL_POWER_MODE mode, int setChip); 1440 HAL_POWER_MODE __ahdecl(*ah_getPowerMode)(struct ath_hal*); 1441 int16_t __ahdecl(*ah_getChanNoise)(struct ath_hal *, 1442 const struct ieee80211_channel *); 1443 1444 /* Beacon Management Functions */ 1445 void __ahdecl(*ah_setBeaconTimers)(struct ath_hal*, 1446 const HAL_BEACON_TIMERS *); 1447 /* NB: deprecated, use ah_setBeaconTimers instead */ 1448 void __ahdecl(*ah_beaconInit)(struct ath_hal *, 1449 uint32_t nexttbtt, uint32_t intval); 1450 void __ahdecl(*ah_setStationBeaconTimers)(struct ath_hal*, 1451 const HAL_BEACON_STATE *); 1452 void __ahdecl(*ah_resetStationBeaconTimers)(struct ath_hal*); 1453 uint64_t __ahdecl(*ah_getNextTBTT)(struct ath_hal *); 1454 1455 /* 802.11n Functions */ 1456 HAL_BOOL __ahdecl(*ah_chainTxDesc)(struct ath_hal *, 1457 struct ath_desc *, 1458 HAL_DMA_ADDR *bufAddrList, 1459 uint32_t *segLenList, 1460 u_int, u_int, HAL_PKT_TYPE, 1461 u_int, HAL_CIPHER, uint8_t, HAL_BOOL, 1462 HAL_BOOL, HAL_BOOL); 1463 HAL_BOOL __ahdecl(*ah_setupFirstTxDesc)(struct ath_hal *, 1464 struct ath_desc *, u_int, u_int, u_int, 1465 u_int, u_int, u_int, u_int, u_int); 1466 HAL_BOOL __ahdecl(*ah_setupLastTxDesc)(struct ath_hal *, 1467 struct ath_desc *, const struct ath_desc *); 1468 void __ahdecl(*ah_set11nRateScenario)(struct ath_hal *, 1469 struct ath_desc *, u_int, u_int, 1470 HAL_11N_RATE_SERIES [], u_int, u_int); 1471 1472 /* 1473 * The next 4 (set11ntxdesc -> set11naggrlast) are specific 1474 * to the EDMA HAL. Descriptors are chained together by 1475 * using filltxdesc (not ChainTxDesc) and then setting the 1476 * aggregate flags appropriately using first/middle/last. 1477 */ 1478 void __ahdecl(*ah_set11nTxDesc)(struct ath_hal *, 1479 void *, u_int, HAL_PKT_TYPE, u_int, u_int, 1480 u_int); 1481 void __ahdecl(*ah_set11nAggrFirst)(struct ath_hal *, 1482 struct ath_desc *, u_int, u_int); 1483 void __ahdecl(*ah_set11nAggrMiddle)(struct ath_hal *, 1484 struct ath_desc *, u_int); 1485 void __ahdecl(*ah_set11nAggrLast)(struct ath_hal *, 1486 struct ath_desc *); 1487 1488 void __ahdecl(*ah_clr11nAggr)(struct ath_hal *, 1489 struct ath_desc *); 1490 void __ahdecl(*ah_set11nBurstDuration)(struct ath_hal *, 1491 struct ath_desc *, u_int); 1492 HAL_BOOL __ahdecl(*ah_getMibCycleCounts) (struct ath_hal *, 1493 HAL_SURVEY_SAMPLE *); 1494 1495 uint32_t __ahdecl(*ah_get11nExtBusy)(struct ath_hal *); 1496 void __ahdecl(*ah_set11nMac2040)(struct ath_hal *, 1497 HAL_HT_MACMODE); 1498 HAL_HT_RXCLEAR __ahdecl(*ah_get11nRxClear)(struct ath_hal *ah); 1499 void __ahdecl(*ah_set11nRxClear)(struct ath_hal *, 1500 HAL_HT_RXCLEAR); 1501 1502 /* Interrupt functions */ 1503 HAL_BOOL __ahdecl(*ah_isInterruptPending)(struct ath_hal*); 1504 HAL_BOOL __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT*); 1505 HAL_INT __ahdecl(*ah_getInterrupts)(struct ath_hal*); 1506 HAL_INT __ahdecl(*ah_setInterrupts)(struct ath_hal*, HAL_INT); 1507 }; 1508 1509 /* 1510 * Check the PCI vendor ID and device ID against Atheros' values 1511 * and return a printable description for any Atheros hardware. 1512 * AH_NULL is returned if the ID's do not describe Atheros hardware. 1513 */ 1514 extern const char *__ahdecl ath_hal_probe(uint16_t vendorid, uint16_t devid); 1515 1516 /* 1517 * Attach the HAL for use with the specified device. The device is 1518 * defined by the PCI device ID. The caller provides an opaque pointer 1519 * to an upper-layer data structure (HAL_SOFTC) that is stored in the 1520 * HAL state block for later use. Hardware register accesses are done 1521 * using the specified bus tag and handle. On successful return a 1522 * reference to a state block is returned that must be supplied in all 1523 * subsequent HAL calls. Storage associated with this reference is 1524 * dynamically allocated and must be freed by calling the ah_detach 1525 * method when the client is done. If the attach operation fails a 1526 * null (AH_NULL) reference will be returned and a status code will 1527 * be returned if the status parameter is non-zero. 1528 */ 1529 extern struct ath_hal * __ahdecl ath_hal_attach(uint16_t devid, HAL_SOFTC, 1530 HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, HAL_STATUS* status); 1531 1532 extern const char *ath_hal_mac_name(struct ath_hal *); 1533 extern const char *ath_hal_rf_name(struct ath_hal *); 1534 1535 /* 1536 * Regulatory interfaces. Drivers should use ath_hal_init_channels to 1537 * request a set of channels for a particular country code and/or 1538 * regulatory domain. If CTRY_DEFAULT and SKU_NONE are specified then 1539 * this list is constructed according to the contents of the EEPROM. 1540 * ath_hal_getchannels acts similarly but does not alter the operating 1541 * state; this can be used to collect information for a particular 1542 * regulatory configuration. Finally ath_hal_set_channels installs a 1543 * channel list constructed outside the driver. The HAL will adopt the 1544 * channel list and setup internal state according to the specified 1545 * regulatory configuration (e.g. conformance test limits). 1546 * 1547 * For all interfaces the channel list is returned in the supplied array. 1548 * maxchans defines the maximum size of this array. nchans contains the 1549 * actual number of channels returned. If a problem occurred then a 1550 * status code != HAL_OK is returned. 1551 */ 1552 struct ieee80211_channel; 1553 1554 /* 1555 * Return a list of channels according to the specified regulatory. 1556 */ 1557 extern HAL_STATUS __ahdecl ath_hal_getchannels(struct ath_hal *, 1558 struct ieee80211_channel *chans, u_int maxchans, int *nchans, 1559 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn, 1560 HAL_BOOL enableExtendedChannels); 1561 1562 /* 1563 * Return a list of channels and install it as the current operating 1564 * regulatory list. 1565 */ 1566 extern HAL_STATUS __ahdecl ath_hal_init_channels(struct ath_hal *, 1567 struct ieee80211_channel *chans, u_int maxchans, int *nchans, 1568 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN rd, 1569 HAL_BOOL enableExtendedChannels); 1570 1571 /* 1572 * Install the list of channels as the current operating regulatory 1573 * and setup related state according to the country code and sku. 1574 */ 1575 extern HAL_STATUS __ahdecl ath_hal_set_channels(struct ath_hal *, 1576 struct ieee80211_channel *chans, int nchans, 1577 HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn); 1578 1579 /* 1580 * Fetch the ctl/ext noise floor values reported by a MIMO 1581 * radio. Returns 1 for valid results, 0 for invalid channel. 1582 */ 1583 extern int __ahdecl ath_hal_get_mimo_chan_noise(struct ath_hal *ah, 1584 const struct ieee80211_channel *chan, int16_t *nf_ctl, 1585 int16_t *nf_ext); 1586 1587 /* 1588 * Calibrate noise floor data following a channel scan or similar. 1589 * This must be called prior retrieving noise floor data. 1590 */ 1591 extern void __ahdecl ath_hal_process_noisefloor(struct ath_hal *ah); 1592 1593 /* 1594 * Return bit mask of wireless modes supported by the hardware. 1595 */ 1596 extern u_int __ahdecl ath_hal_getwirelessmodes(struct ath_hal*); 1597 1598 /* 1599 * Get the HAL wireless mode for the given channel. 1600 */ 1601 extern int ath_hal_get_curmode(struct ath_hal *ah, 1602 const struct ieee80211_channel *chan); 1603 1604 /* 1605 * Calculate the packet TX time for a legacy or 11n frame 1606 */ 1607 extern uint32_t __ahdecl ath_hal_pkt_txtime(struct ath_hal *ah, 1608 const HAL_RATE_TABLE *rates, uint32_t frameLen, 1609 uint16_t rateix, HAL_BOOL isht40, HAL_BOOL shortPreamble); 1610 1611 /* 1612 * Calculate the duration of an 11n frame. 1613 */ 1614 extern uint32_t __ahdecl ath_computedur_ht(uint32_t frameLen, uint16_t rate, 1615 int streams, HAL_BOOL isht40, HAL_BOOL isShortGI); 1616 1617 /* 1618 * Calculate the transmit duration of a legacy frame. 1619 */ 1620 extern uint16_t __ahdecl ath_hal_computetxtime(struct ath_hal *, 1621 const HAL_RATE_TABLE *rates, uint32_t frameLen, 1622 uint16_t rateix, HAL_BOOL shortPreamble); 1623 1624 /* 1625 * Adjust the TSF. 1626 */ 1627 extern void __ahdecl ath_hal_adjusttsf(struct ath_hal *ah, int32_t tsfdelta); 1628 1629 /* 1630 * Enable or disable CCA. 1631 */ 1632 void __ahdecl ath_hal_setcca(struct ath_hal *ah, int ena); 1633 1634 /* 1635 * Get CCA setting. 1636 */ 1637 int __ahdecl ath_hal_getcca(struct ath_hal *ah); 1638 1639 /* 1640 * Read EEPROM data from ah_eepromdata 1641 */ 1642 HAL_BOOL __ahdecl ath_hal_EepromDataRead(struct ath_hal *ah, 1643 u_int off, uint16_t *data); 1644 1645 /* 1646 * For now, simply pass through MFP frames. 1647 */ 1648 static inline u_int32_t 1649 ath_hal_get_mfp_qos(struct ath_hal *ah) 1650 { 1651 //return AH_PRIVATE(ah)->ah_mfp_qos; 1652 return HAL_MFP_QOSDATA; 1653 } 1654 1655 #endif /* _ATH_AH_H_ */ 1656