1 /* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19 20 #ifndef _ATH_AH_H_ 21 #define _ATH_AH_H_ 22 /* 23 * Atheros Hardware Access Layer 24 * 25 * Clients of the HAL call ath_hal_attach to obtain a reference to an ath_hal 26 * structure for use with the device. Hardware-related operations that 27 * follow must call back into the HAL through interface, supplying the 28 * reference as the first parameter. 29 */ 30 31 #include "ah_osdep.h" 32 33 /* 34 * The maximum number of TX/RX chains supported. 35 * This is intended to be used by various statistics gathering operations 36 * (NF, RSSI, EVM). 37 */ 38 #define AH_MIMO_MAX_CHAINS 3 39 #define AH_MIMO_MAX_EVM_PILOTS 6 40 41 /* 42 * __ahdecl is analogous to _cdecl; it defines the calling 43 * convention used within the HAL. For most systems this 44 * can just default to be empty and the compiler will (should) 45 * use _cdecl. For systems where _cdecl is not compatible this 46 * must be defined. See linux/ah_osdep.h for an example. 47 */ 48 #ifndef __ahdecl 49 #define __ahdecl 50 #endif 51 52 /* 53 * Status codes that may be returned by the HAL. Note that 54 * interfaces that return a status code set it only when an 55 * error occurs--i.e. you cannot check it for success. 56 */ 57 typedef enum { 58 HAL_OK = 0, /* No error */ 59 HAL_ENXIO = 1, /* No hardware present */ 60 HAL_ENOMEM = 2, /* Memory allocation failed */ 61 HAL_EIO = 3, /* Hardware didn't respond as expected */ 62 HAL_EEMAGIC = 4, /* EEPROM magic number invalid */ 63 HAL_EEVERSION = 5, /* EEPROM version invalid */ 64 HAL_EELOCKED = 6, /* EEPROM unreadable */ 65 HAL_EEBADSUM = 7, /* EEPROM checksum invalid */ 66 HAL_EEREAD = 8, /* EEPROM read problem */ 67 HAL_EEBADMAC = 9, /* EEPROM mac address invalid */ 68 HAL_EESIZE = 10, /* EEPROM size not supported */ 69 HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */ 70 HAL_EINVAL = 12, /* Invalid parameter to function */ 71 HAL_ENOTSUPP = 13, /* Hardware revision not supported */ 72 HAL_ESELFTEST = 14, /* Hardware self-test failed */ 73 HAL_EINPROGRESS = 15, /* Operation incomplete */ 74 HAL_EEBADREG = 16, /* EEPROM invalid regulatory contents */ 75 HAL_EEBADCC = 17, /* EEPROM invalid country code */ 76 } HAL_STATUS; 77 78 typedef enum { 79 AH_FALSE = 0, /* NB: lots of code assumes false is zero */ 80 AH_TRUE = 1, 81 } HAL_BOOL; 82 83 typedef enum { 84 HAL_CAP_REG_DMN = 0, /* current regulatory domain */ 85 HAL_CAP_CIPHER = 1, /* hardware supports cipher */ 86 HAL_CAP_TKIP_MIC = 2, /* handle TKIP MIC in hardware */ 87 HAL_CAP_TKIP_SPLIT = 3, /* hardware TKIP uses split keys */ 88 HAL_CAP_PHYCOUNTERS = 4, /* hardware PHY error counters */ 89 HAL_CAP_DIVERSITY = 5, /* hardware supports fast diversity */ 90 HAL_CAP_KEYCACHE_SIZE = 6, /* number of entries in key cache */ 91 HAL_CAP_NUM_TXQUEUES = 7, /* number of hardware xmit queues */ 92 HAL_CAP_VEOL = 9, /* hardware supports virtual EOL */ 93 HAL_CAP_PSPOLL = 10, /* hardware has working PS-Poll support */ 94 HAL_CAP_DIAG = 11, /* hardware diagnostic support */ 95 HAL_CAP_COMPRESSION = 12, /* hardware supports compression */ 96 HAL_CAP_BURST = 13, /* hardware supports packet bursting */ 97 HAL_CAP_FASTFRAME = 14, /* hardware supoprts fast frames */ 98 HAL_CAP_TXPOW = 15, /* global tx power limit */ 99 HAL_CAP_TPC = 16, /* per-packet tx power control */ 100 HAL_CAP_PHYDIAG = 17, /* hardware phy error diagnostic */ 101 HAL_CAP_BSSIDMASK = 18, /* hardware supports bssid mask */ 102 HAL_CAP_MCAST_KEYSRCH = 19, /* hardware has multicast key search */ 103 HAL_CAP_TSF_ADJUST = 20, /* hardware has beacon tsf adjust */ 104 /* 21 was HAL_CAP_XR */ 105 HAL_CAP_WME_TKIPMIC = 22, /* hardware can support TKIP MIC when WMM is turned on */ 106 /* 23 was HAL_CAP_CHAN_HALFRATE */ 107 /* 24 was HAL_CAP_CHAN_QUARTERRATE */ 108 HAL_CAP_RFSILENT = 25, /* hardware has rfsilent support */ 109 HAL_CAP_TPC_ACK = 26, /* ack txpower with per-packet tpc */ 110 HAL_CAP_TPC_CTS = 27, /* cts txpower with per-packet tpc */ 111 HAL_CAP_11D = 28, /* 11d beacon support for changing cc */ 112 113 HAL_CAP_HT = 30, /* hardware can support HT */ 114 HAL_CAP_GTXTO = 31, /* hardware supports global tx timeout */ 115 HAL_CAP_FAST_CC = 32, /* hardware supports fast channel change */ 116 HAL_CAP_TX_CHAINMASK = 33, /* mask of TX chains supported */ 117 HAL_CAP_RX_CHAINMASK = 34, /* mask of RX chains supported */ 118 HAL_CAP_NUM_GPIO_PINS = 36, /* number of GPIO pins */ 119 120 HAL_CAP_CST = 38, /* hardware supports carrier sense timeout */ 121 122 HAL_CAP_RTS_AGGR_LIMIT = 42, /* aggregation limit with RTS */ 123 HAL_CAP_4ADDR_AGGR = 43, /* hardware is capable of 4addr aggregation */ 124 HAL_CAP_DFS_DMN = 44, /* current DFS domain */ 125 HAL_CAP_EXT_CHAN_DFS = 45, /* DFS support for extension channel */ 126 HAL_CAP_COMBINED_RADAR_RSSI = 46, /* Is combined RSSI for radar accurate */ 127 128 HAL_CAP_AUTO_SLEEP = 48, /* hardware can go to network sleep 129 automatically after waking up to receive TIM */ 130 HAL_CAP_MBSSID_AGGR_SUPPORT = 49, /* Support for mBSSID Aggregation */ 131 HAL_CAP_SPLIT_4KB_TRANS = 50, /* hardware supports descriptors straddling a 4k page boundary */ 132 HAL_CAP_REG_FLAG = 51, /* Regulatory domain flags */ 133 134 HAL_CAP_BT_COEX = 60, /* hardware is capable of bluetooth coexistence */ 135 136 HAL_CAP_HT20_SGI = 96, /* hardware supports HT20 short GI */ 137 138 HAL_CAP_RXTSTAMP_PREC = 100, /* rx desc tstamp precision (bits) */ 139 HAL_CAP_ENHANCED_DFS_SUPPORT = 117, /* hardware supports enhanced DFS */ 140 141 /* The following are private to the FreeBSD HAL (224 onward) */ 142 143 HAL_CAP_INTMIT = 229, /* interference mitigation */ 144 HAL_CAP_RXORN_FATAL = 230, /* HAL_INT_RXORN treated as fatal */ 145 HAL_CAP_BB_HANG = 235, /* can baseband hang */ 146 HAL_CAP_MAC_HANG = 236, /* can MAC hang */ 147 HAL_CAP_INTRMASK = 237, /* bitmask of supported interrupts */ 148 HAL_CAP_BSSIDMATCH = 238, /* hardware has disable bssid match */ 149 HAL_CAP_STREAMS = 239, /* how many 802.11n spatial streams are available */ 150 HAL_CAP_RXDESC_SELFLINK = 242, /* support a self-linked tail RX descriptor */ 151 HAL_CAP_LONG_RXDESC_TSF = 243, /* hardware supports 32bit TSF in RX descriptor */ 152 } HAL_CAPABILITY_TYPE; 153 154 /* 155 * "States" for setting the LED. These correspond to 156 * the possible 802.11 operational states and there may 157 * be a many-to-one mapping between these states and the 158 * actual hardware state for the LED's (i.e. the hardware 159 * may have fewer states). 160 */ 161 typedef enum { 162 HAL_LED_INIT = 0, 163 HAL_LED_SCAN = 1, 164 HAL_LED_AUTH = 2, 165 HAL_LED_ASSOC = 3, 166 HAL_LED_RUN = 4 167 } HAL_LED_STATE; 168 169 /* 170 * Transmit queue types/numbers. These are used to tag 171 * each transmit queue in the hardware and to identify a set 172 * of transmit queues for operations such as start/stop dma. 173 */ 174 typedef enum { 175 HAL_TX_QUEUE_INACTIVE = 0, /* queue is inactive/unused */ 176 HAL_TX_QUEUE_DATA = 1, /* data xmit q's */ 177 HAL_TX_QUEUE_BEACON = 2, /* beacon xmit q */ 178 HAL_TX_QUEUE_CAB = 3, /* "crap after beacon" xmit q */ 179 HAL_TX_QUEUE_UAPSD = 4, /* u-apsd power save xmit q */ 180 HAL_TX_QUEUE_PSPOLL = 5, /* power save poll xmit q */ 181 } HAL_TX_QUEUE; 182 183 #define HAL_NUM_TX_QUEUES 10 /* max possible # of queues */ 184 185 /* 186 * Transmit queue subtype. These map directly to 187 * WME Access Categories (except for UPSD). Refer 188 * to Table 5 of the WME spec. 189 */ 190 typedef enum { 191 HAL_WME_AC_BK = 0, /* background access category */ 192 HAL_WME_AC_BE = 1, /* best effort access category*/ 193 HAL_WME_AC_VI = 2, /* video access category */ 194 HAL_WME_AC_VO = 3, /* voice access category */ 195 HAL_WME_UPSD = 4, /* uplink power save */ 196 } HAL_TX_QUEUE_SUBTYPE; 197 198 /* 199 * Transmit queue flags that control various 200 * operational parameters. 201 */ 202 typedef enum { 203 /* 204 * Per queue interrupt enables. When set the associated 205 * interrupt may be delivered for packets sent through 206 * the queue. Without these enabled no interrupts will 207 * be delivered for transmits through the queue. 208 */ 209 HAL_TXQ_TXOKINT_ENABLE = 0x0001, /* enable TXOK interrupt */ 210 HAL_TXQ_TXERRINT_ENABLE = 0x0001, /* enable TXERR interrupt */ 211 HAL_TXQ_TXDESCINT_ENABLE = 0x0002, /* enable TXDESC interrupt */ 212 HAL_TXQ_TXEOLINT_ENABLE = 0x0004, /* enable TXEOL interrupt */ 213 HAL_TXQ_TXURNINT_ENABLE = 0x0008, /* enable TXURN interrupt */ 214 /* 215 * Enable hardware compression for packets sent through 216 * the queue. The compression buffer must be setup and 217 * packets must have a key entry marked in the tx descriptor. 218 */ 219 HAL_TXQ_COMPRESSION_ENABLE = 0x0010, /* enable h/w compression */ 220 /* 221 * Disable queue when veol is hit or ready time expires. 222 * By default the queue is disabled only on reaching the 223 * physical end of queue (i.e. a null link ptr in the 224 * descriptor chain). 225 */ 226 HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE = 0x0020, 227 /* 228 * Schedule frames on delivery of a DBA (DMA Beacon Alert) 229 * event. Frames will be transmitted only when this timer 230 * fires, e.g to transmit a beacon in ap or adhoc modes. 231 */ 232 HAL_TXQ_DBA_GATED = 0x0040, /* schedule based on DBA */ 233 /* 234 * Each transmit queue has a counter that is incremented 235 * each time the queue is enabled and decremented when 236 * the list of frames to transmit is traversed (or when 237 * the ready time for the queue expires). This counter 238 * must be non-zero for frames to be scheduled for 239 * transmission. The following controls disable bumping 240 * this counter under certain conditions. Typically this 241 * is used to gate frames based on the contents of another 242 * queue (e.g. CAB traffic may only follow a beacon frame). 243 * These are meaningful only when frames are scheduled 244 * with a non-ASAP policy (e.g. DBA-gated). 245 */ 246 HAL_TXQ_CBR_DIS_QEMPTY = 0x0080, /* disable on this q empty */ 247 HAL_TXQ_CBR_DIS_BEMPTY = 0x0100, /* disable on beacon q empty */ 248 249 /* 250 * Fragment burst backoff policy. Normally the no backoff 251 * is done after a successful transmission, the next fragment 252 * is sent at SIFS. If this flag is set backoff is done 253 * after each fragment, regardless whether it was ack'd or 254 * not, after the backoff count reaches zero a normal channel 255 * access procedure is done before the next transmit (i.e. 256 * wait AIFS instead of SIFS). 257 */ 258 HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE = 0x00800000, 259 /* 260 * Disable post-tx backoff following each frame. 261 */ 262 HAL_TXQ_BACKOFF_DISABLE = 0x00010000, /* disable post backoff */ 263 /* 264 * DCU arbiter lockout control. This controls how 265 * lower priority tx queues are handled with respect to 266 * to a specific queue when multiple queues have frames 267 * to send. No lockout means lower priority queues arbitrate 268 * concurrently with this queue. Intra-frame lockout 269 * means lower priority queues are locked out until the 270 * current frame transmits (e.g. including backoffs and bursting). 271 * Global lockout means nothing lower can arbitrary so 272 * long as there is traffic activity on this queue (frames, 273 * backoff, etc). 274 */ 275 HAL_TXQ_ARB_LOCKOUT_INTRA = 0x00020000, /* intra-frame lockout */ 276 HAL_TXQ_ARB_LOCKOUT_GLOBAL = 0x00040000, /* full lockout s */ 277 278 HAL_TXQ_IGNORE_VIRTCOL = 0x00080000, /* ignore virt collisions */ 279 HAL_TXQ_SEQNUM_INC_DIS = 0x00100000, /* disable seqnum increment */ 280 } HAL_TX_QUEUE_FLAGS; 281 282 typedef struct { 283 uint32_t tqi_ver; /* hal TXQ version */ 284 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* subtype if applicable */ 285 HAL_TX_QUEUE_FLAGS tqi_qflags; /* flags (see above) */ 286 uint32_t tqi_priority; /* (not used) */ 287 uint32_t tqi_aifs; /* aifs */ 288 uint32_t tqi_cwmin; /* cwMin */ 289 uint32_t tqi_cwmax; /* cwMax */ 290 uint16_t tqi_shretry; /* rts retry limit */ 291 uint16_t tqi_lgretry; /* long retry limit (not used)*/ 292 uint32_t tqi_cbrPeriod; /* CBR period (us) */ 293 uint32_t tqi_cbrOverflowLimit; /* threshold for CBROVF int */ 294 uint32_t tqi_burstTime; /* max burst duration (us) */ 295 uint32_t tqi_readyTime; /* frame schedule time (us) */ 296 uint32_t tqi_compBuf; /* comp buffer phys addr */ 297 } HAL_TXQ_INFO; 298 299 #define HAL_TQI_NONVAL 0xffff 300 301 /* token to use for aifs, cwmin, cwmax */ 302 #define HAL_TXQ_USEDEFAULT ((uint32_t) -1) 303 304 /* compression definitions */ 305 #define HAL_COMP_BUF_MAX_SIZE 9216 /* 9K */ 306 #define HAL_COMP_BUF_ALIGN_SIZE 512 307 308 /* 309 * Transmit packet types. This belongs in ah_desc.h, but 310 * is here so we can give a proper type to various parameters 311 * (and not require everyone include the file). 312 * 313 * NB: These values are intentionally assigned for 314 * direct use when setting up h/w descriptors. 315 */ 316 typedef enum { 317 HAL_PKT_TYPE_NORMAL = 0, 318 HAL_PKT_TYPE_ATIM = 1, 319 HAL_PKT_TYPE_PSPOLL = 2, 320 HAL_PKT_TYPE_BEACON = 3, 321 HAL_PKT_TYPE_PROBE_RESP = 4, 322 HAL_PKT_TYPE_CHIRP = 5, 323 HAL_PKT_TYPE_GRP_POLL = 6, 324 HAL_PKT_TYPE_AMPDU = 7, 325 } HAL_PKT_TYPE; 326 327 /* Rx Filter Frame Types */ 328 typedef enum { 329 /* 330 * These bits correspond to AR_RX_FILTER for all chips. 331 * Not all bits are supported by all chips. 332 */ 333 HAL_RX_FILTER_UCAST = 0x00000001, /* Allow unicast frames */ 334 HAL_RX_FILTER_MCAST = 0x00000002, /* Allow multicast frames */ 335 HAL_RX_FILTER_BCAST = 0x00000004, /* Allow broadcast frames */ 336 HAL_RX_FILTER_CONTROL = 0x00000008, /* Allow control frames */ 337 HAL_RX_FILTER_BEACON = 0x00000010, /* Allow beacon frames */ 338 HAL_RX_FILTER_PROM = 0x00000020, /* Promiscuous mode */ 339 HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */ 340 HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */ 341 HAL_RX_FILTER_COMPBAR = 0x00000400, /* Allow compressed BAR */ 342 HAL_RX_FILTER_COMP_BA = 0x00000800, /* Allow compressed blockack */ 343 HAL_RX_FILTER_PHYRADAR = 0x00002000, /* Allow phy radar errors */ 344 HAL_RX_FILTER_PSPOLL = 0x00004000, /* Allow PS-POLL frames */ 345 HAL_RX_FILTER_MCAST_BCAST_ALL = 0x00008000, 346 /* Allow all mcast/bcast frames */ 347 348 /* 349 * Magic RX filter flags that aren't targetting hardware bits 350 * but instead the HAL sets individual bits - eg PHYERR will result 351 * in OFDM/CCK timing error frames being received. 352 */ 353 HAL_RX_FILTER_BSSID = 0x40000000, /* Disable BSSID match */ 354 } HAL_RX_FILTER; 355 356 typedef enum { 357 HAL_PM_AWAKE = 0, 358 HAL_PM_FULL_SLEEP = 1, 359 HAL_PM_NETWORK_SLEEP = 2, 360 HAL_PM_UNDEFINED = 3 361 } HAL_POWER_MODE; 362 363 /* 364 * NOTE WELL: 365 * These are mapped to take advantage of the common locations for many of 366 * the bits on all of the currently supported MAC chips. This is to make 367 * the ISR as efficient as possible, while still abstracting HW differences. 368 * When new hardware breaks this commonality this enumerated type, as well 369 * as the HAL functions using it, must be modified. All values are directly 370 * mapped unless commented otherwise. 371 */ 372 typedef enum { 373 HAL_INT_RX = 0x00000001, /* Non-common mapping */ 374 HAL_INT_RXDESC = 0x00000002, 375 HAL_INT_RXNOFRM = 0x00000008, 376 HAL_INT_RXEOL = 0x00000010, 377 HAL_INT_RXORN = 0x00000020, 378 HAL_INT_TX = 0x00000040, /* Non-common mapping */ 379 HAL_INT_TXDESC = 0x00000080, 380 HAL_INT_TIM_TIMER= 0x00000100, 381 HAL_INT_TXURN = 0x00000800, 382 HAL_INT_MIB = 0x00001000, 383 HAL_INT_RXPHY = 0x00004000, 384 HAL_INT_RXKCM = 0x00008000, 385 HAL_INT_SWBA = 0x00010000, 386 HAL_INT_BMISS = 0x00040000, 387 HAL_INT_BNR = 0x00100000, 388 HAL_INT_TIM = 0x00200000, /* Non-common mapping */ 389 HAL_INT_DTIM = 0x00400000, /* Non-common mapping */ 390 HAL_INT_DTIMSYNC= 0x00800000, /* Non-common mapping */ 391 HAL_INT_GPIO = 0x01000000, 392 HAL_INT_CABEND = 0x02000000, /* Non-common mapping */ 393 HAL_INT_TSFOOR = 0x04000000, /* Non-common mapping */ 394 HAL_INT_TBTT = 0x08000000, /* Non-common mapping */ 395 HAL_INT_CST = 0x10000000, /* Non-common mapping */ 396 HAL_INT_GTT = 0x20000000, /* Non-common mapping */ 397 HAL_INT_FATAL = 0x40000000, /* Non-common mapping */ 398 #define HAL_INT_GLOBAL 0x80000000 /* Set/clear IER */ 399 HAL_INT_BMISC = HAL_INT_TIM 400 | HAL_INT_DTIM 401 | HAL_INT_DTIMSYNC 402 | HAL_INT_CABEND 403 | HAL_INT_TBTT, 404 405 /* Interrupt bits that map directly to ISR/IMR bits */ 406 HAL_INT_COMMON = HAL_INT_RXNOFRM 407 | HAL_INT_RXDESC 408 | HAL_INT_RXEOL 409 | HAL_INT_RXORN 410 | HAL_INT_TXDESC 411 | HAL_INT_TXURN 412 | HAL_INT_MIB 413 | HAL_INT_RXPHY 414 | HAL_INT_RXKCM 415 | HAL_INT_SWBA 416 | HAL_INT_BMISS 417 | HAL_INT_BNR 418 | HAL_INT_GPIO, 419 } HAL_INT; 420 421 typedef enum { 422 HAL_GPIO_MUX_OUTPUT = 0, 423 HAL_GPIO_MUX_PCIE_ATTENTION_LED = 1, 424 HAL_GPIO_MUX_PCIE_POWER_LED = 2, 425 HAL_GPIO_MUX_TX_FRAME = 3, 426 HAL_GPIO_MUX_RX_CLEAR_EXTERNAL = 4, 427 HAL_GPIO_MUX_MAC_NETWORK_LED = 5, 428 HAL_GPIO_MUX_MAC_POWER_LED = 6 429 } HAL_GPIO_MUX_TYPE; 430 431 typedef enum { 432 HAL_GPIO_INTR_LOW = 0, 433 HAL_GPIO_INTR_HIGH = 1, 434 HAL_GPIO_INTR_DISABLE = 2 435 } HAL_GPIO_INTR_TYPE; 436 437 typedef enum { 438 HAL_RFGAIN_INACTIVE = 0, 439 HAL_RFGAIN_READ_REQUESTED = 1, 440 HAL_RFGAIN_NEED_CHANGE = 2 441 } HAL_RFGAIN; 442 443 typedef uint16_t HAL_CTRY_CODE; /* country code */ 444 typedef uint16_t HAL_REG_DOMAIN; /* regulatory domain code */ 445 446 #define HAL_ANTENNA_MIN_MODE 0 447 #define HAL_ANTENNA_FIXED_A 1 448 #define HAL_ANTENNA_FIXED_B 2 449 #define HAL_ANTENNA_MAX_MODE 3 450 451 typedef struct { 452 uint32_t ackrcv_bad; 453 uint32_t rts_bad; 454 uint32_t rts_good; 455 uint32_t fcs_bad; 456 uint32_t beacons; 457 } HAL_MIB_STATS; 458 459 enum { 460 HAL_MODE_11A = 0x001, /* 11a channels */ 461 HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */ 462 HAL_MODE_11B = 0x004, /* 11b channels */ 463 HAL_MODE_PUREG = 0x008, /* 11g channels (OFDM only) */ 464 #ifdef notdef 465 HAL_MODE_11G = 0x010, /* 11g channels (OFDM/CCK) */ 466 #else 467 HAL_MODE_11G = 0x008, /* XXX historical */ 468 #endif 469 HAL_MODE_108G = 0x020, /* 11g+Turbo channels */ 470 HAL_MODE_108A = 0x040, /* 11a+Turbo channels */ 471 HAL_MODE_11A_HALF_RATE = 0x200, /* 11a half width channels */ 472 HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11a quarter width channels */ 473 HAL_MODE_11G_HALF_RATE = 0x800, /* 11g half width channels */ 474 HAL_MODE_11G_QUARTER_RATE = 0x1000, /* 11g quarter width channels */ 475 HAL_MODE_11NG_HT20 = 0x008000, 476 HAL_MODE_11NA_HT20 = 0x010000, 477 HAL_MODE_11NG_HT40PLUS = 0x020000, 478 HAL_MODE_11NG_HT40MINUS = 0x040000, 479 HAL_MODE_11NA_HT40PLUS = 0x080000, 480 HAL_MODE_11NA_HT40MINUS = 0x100000, 481 HAL_MODE_ALL = 0xffffff 482 }; 483 484 typedef struct { 485 int rateCount; /* NB: for proper padding */ 486 uint8_t rateCodeToIndex[144]; /* back mapping */ 487 struct { 488 uint8_t valid; /* valid for rate control use */ 489 uint8_t phy; /* CCK/OFDM/XR */ 490 uint32_t rateKbps; /* transfer rate in kbs */ 491 uint8_t rateCode; /* rate for h/w descriptors */ 492 uint8_t shortPreamble; /* mask for enabling short 493 * preamble in CCK rate code */ 494 uint8_t dot11Rate; /* value for supported rates 495 * info element of MLME */ 496 uint8_t controlRate; /* index of next lower basic 497 * rate; used for dur. calcs */ 498 uint16_t lpAckDuration; /* long preamble ACK duration */ 499 uint16_t spAckDuration; /* short preamble ACK duration*/ 500 } info[32]; 501 } HAL_RATE_TABLE; 502 503 typedef struct { 504 u_int rs_count; /* number of valid entries */ 505 uint8_t rs_rates[32]; /* rates */ 506 } HAL_RATE_SET; 507 508 /* 509 * 802.11n specific structures and enums 510 */ 511 typedef enum { 512 HAL_CHAINTYPE_TX = 1, /* Tx chain type */ 513 HAL_CHAINTYPE_RX = 2, /* RX chain type */ 514 } HAL_CHAIN_TYPE; 515 516 typedef struct { 517 u_int Tries; 518 u_int Rate; 519 u_int PktDuration; 520 u_int ChSel; 521 u_int RateFlags; 522 #define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */ 523 #define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */ 524 #define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */ 525 } HAL_11N_RATE_SERIES; 526 527 typedef enum { 528 HAL_HT_MACMODE_20 = 0, /* 20 MHz operation */ 529 HAL_HT_MACMODE_2040 = 1, /* 20/40 MHz operation */ 530 } HAL_HT_MACMODE; 531 532 typedef enum { 533 HAL_HT_PHYMODE_20 = 0, /* 20 MHz operation */ 534 HAL_HT_PHYMODE_2040 = 1, /* 20/40 MHz operation */ 535 } HAL_HT_PHYMODE; 536 537 typedef enum { 538 HAL_HT_EXTPROTSPACING_20 = 0, /* 20 MHz spacing */ 539 HAL_HT_EXTPROTSPACING_25 = 1, /* 25 MHz spacing */ 540 } HAL_HT_EXTPROTSPACING; 541 542 543 typedef enum { 544 HAL_RX_CLEAR_CTL_LOW = 0x1, /* force control channel to appear busy */ 545 HAL_RX_CLEAR_EXT_LOW = 0x2, /* force extension channel to appear busy */ 546 } HAL_HT_RXCLEAR; 547 548 /* 549 * Antenna switch control. By default antenna selection 550 * enables multiple (2) antenna use. To force use of the 551 * A or B antenna only specify a fixed setting. Fixing 552 * the antenna will also disable any diversity support. 553 */ 554 typedef enum { 555 HAL_ANT_VARIABLE = 0, /* variable by programming */ 556 HAL_ANT_FIXED_A = 1, /* fixed antenna A */ 557 HAL_ANT_FIXED_B = 2, /* fixed antenna B */ 558 } HAL_ANT_SETTING; 559 560 typedef enum { 561 HAL_M_STA = 1, /* infrastructure station */ 562 HAL_M_IBSS = 0, /* IBSS (adhoc) station */ 563 HAL_M_HOSTAP = 6, /* Software Access Point */ 564 HAL_M_MONITOR = 8 /* Monitor mode */ 565 } HAL_OPMODE; 566 567 typedef struct { 568 uint8_t kv_type; /* one of HAL_CIPHER */ 569 uint8_t kv_pad; 570 uint16_t kv_len; /* length in bits */ 571 uint8_t kv_val[16]; /* enough for 128-bit keys */ 572 uint8_t kv_mic[8]; /* TKIP MIC key */ 573 uint8_t kv_txmic[8]; /* TKIP TX MIC key (optional) */ 574 } HAL_KEYVAL; 575 576 typedef enum { 577 HAL_CIPHER_WEP = 0, 578 HAL_CIPHER_AES_OCB = 1, 579 HAL_CIPHER_AES_CCM = 2, 580 HAL_CIPHER_CKIP = 3, 581 HAL_CIPHER_TKIP = 4, 582 HAL_CIPHER_CLR = 5, /* no encryption */ 583 584 HAL_CIPHER_MIC = 127 /* TKIP-MIC, not a cipher */ 585 } HAL_CIPHER; 586 587 enum { 588 HAL_SLOT_TIME_6 = 6, /* NB: for turbo mode */ 589 HAL_SLOT_TIME_9 = 9, 590 HAL_SLOT_TIME_20 = 20, 591 }; 592 593 /* 594 * Per-station beacon timer state. Note that the specified 595 * beacon interval (given in TU's) can also include flags 596 * to force a TSF reset and to enable the beacon xmit logic. 597 * If bs_cfpmaxduration is non-zero the hardware is setup to 598 * coexist with a PCF-capable AP. 599 */ 600 typedef struct { 601 uint32_t bs_nexttbtt; /* next beacon in TU */ 602 uint32_t bs_nextdtim; /* next DTIM in TU */ 603 uint32_t bs_intval; /* beacon interval+flags */ 604 #define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */ 605 #define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */ 606 #define HAL_BEACON_RESET_TSF 0x01000000 /* clear TSF */ 607 uint32_t bs_dtimperiod; 608 uint16_t bs_cfpperiod; /* CFP period in TU */ 609 uint16_t bs_cfpmaxduration; /* max CFP duration in TU */ 610 uint32_t bs_cfpnext; /* next CFP in TU */ 611 uint16_t bs_timoffset; /* byte offset to TIM bitmap */ 612 uint16_t bs_bmissthreshold; /* beacon miss threshold */ 613 uint32_t bs_sleepduration; /* max sleep duration */ 614 } HAL_BEACON_STATE; 615 616 /* 617 * Like HAL_BEACON_STATE but for non-station mode setup. 618 * NB: see above flag definitions for bt_intval. 619 */ 620 typedef struct { 621 uint32_t bt_intval; /* beacon interval+flags */ 622 uint32_t bt_nexttbtt; /* next beacon in TU */ 623 uint32_t bt_nextatim; /* next ATIM in TU */ 624 uint32_t bt_nextdba; /* next DBA in 1/8th TU */ 625 uint32_t bt_nextswba; /* next SWBA in 1/8th TU */ 626 uint32_t bt_flags; /* timer enables */ 627 #define HAL_BEACON_TBTT_EN 0x00000001 628 #define HAL_BEACON_DBA_EN 0x00000002 629 #define HAL_BEACON_SWBA_EN 0x00000004 630 } HAL_BEACON_TIMERS; 631 632 /* 633 * Per-node statistics maintained by the driver for use in 634 * optimizing signal quality and other operational aspects. 635 */ 636 typedef struct { 637 uint32_t ns_avgbrssi; /* average beacon rssi */ 638 uint32_t ns_avgrssi; /* average data rssi */ 639 uint32_t ns_avgtxrssi; /* average tx rssi */ 640 } HAL_NODE_STATS; 641 642 #define HAL_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */ 643 644 struct ath_desc; 645 struct ath_tx_status; 646 struct ath_rx_status; 647 struct ieee80211_channel; 648 649 /* 650 * This is a channel survey sample entry. 651 * 652 * The AR5212 ANI routines fill these samples. The ANI code then uses it 653 * when calculating listen time; it is also exported via a diagnostic 654 * API. 655 */ 656 typedef struct { 657 uint32_t seq_num; 658 uint32_t tx_busy; 659 uint32_t rx_busy; 660 uint32_t chan_busy; 661 uint32_t cycle_count; 662 } HAL_SURVEY_SAMPLE; 663 664 /* 665 * This provides 3.2 seconds of sample space given an 666 * ANI time of 1/10th of a second. This may not be enough! 667 */ 668 #define CHANNEL_SURVEY_SAMPLE_COUNT 32 669 670 typedef struct { 671 HAL_SURVEY_SAMPLE samples[CHANNEL_SURVEY_SAMPLE_COUNT]; 672 uint32_t cur_sample; /* current sample in sequence */ 673 uint32_t cur_seq; /* current sequence number */ 674 } HAL_CHANNEL_SURVEY; 675 676 /* 677 * ANI commands. 678 * 679 * These are used both internally and externally via the diagnostic 680 * API. 681 * 682 * Note that this is NOT the ANI commands being used via the INTMIT 683 * capability - that has a different mapping for some reason. 684 */ 685 typedef enum { 686 HAL_ANI_PRESENT = 0, /* is ANI support present */ 687 HAL_ANI_NOISE_IMMUNITY_LEVEL = 1, /* set level */ 688 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION = 2, /* enable/disable */ 689 HAL_ANI_CCK_WEAK_SIGNAL_THR = 3, /* enable/disable */ 690 HAL_ANI_FIRSTEP_LEVEL = 4, /* set level */ 691 HAL_ANI_SPUR_IMMUNITY_LEVEL = 5, /* set level */ 692 HAL_ANI_MODE = 6, /* 0 => manual, 1 => auto (XXX do not change) */ 693 HAL_ANI_PHYERR_RESET = 7, /* reset phy error stats */ 694 } HAL_ANI_CMD; 695 696 /* 697 * This is the layout of the ANI INTMIT capability. 698 * 699 * Notice that the command values differ to HAL_ANI_CMD. 700 */ 701 typedef enum { 702 HAL_CAP_INTMIT_PRESENT = 0, 703 HAL_CAP_INTMIT_ENABLE = 1, 704 HAL_CAP_INTMIT_NOISE_IMMUNITY_LEVEL = 2, 705 HAL_CAP_INTMIT_OFDM_WEAK_SIGNAL_LEVEL = 3, 706 HAL_CAP_INTMIT_CCK_WEAK_SIGNAL_THR = 4, 707 HAL_CAP_INTMIT_FIRSTEP_LEVEL = 5, 708 HAL_CAP_INTMIT_SPUR_IMMUNITY_LEVEL = 6 709 } HAL_CAP_INTMIT_CMD; 710 711 typedef struct { 712 int32_t pe_firpwr; /* FIR pwr out threshold */ 713 int32_t pe_rrssi; /* Radar rssi thresh */ 714 int32_t pe_height; /* Pulse height thresh */ 715 int32_t pe_prssi; /* Pulse rssi thresh */ 716 int32_t pe_inband; /* Inband thresh */ 717 718 /* The following params are only for AR5413 and later */ 719 u_int32_t pe_relpwr; /* Relative power threshold in 0.5dB steps */ 720 u_int32_t pe_relstep; /* Pulse Relative step threshold in 0.5dB steps */ 721 u_int32_t pe_maxlen; /* Max length of radar sign in 0.8us units */ 722 int32_t pe_usefir128; /* Use the average in-band power measured over 128 cycles */ 723 int32_t pe_blockradar; /* 724 * Enable to block radar check if pkt detect is done via OFDM 725 * weak signal detect or pkt is detected immediately after tx 726 * to rx transition 727 */ 728 int32_t pe_enmaxrssi; /* 729 * Enable to use the max rssi instead of the last rssi during 730 * fine gain changes for radar detection 731 */ 732 int32_t pe_extchannel; /* Enable DFS on ext channel */ 733 int32_t pe_enabled; /* Whether radar detection is enabled */ 734 } HAL_PHYERR_PARAM; 735 736 #define HAL_PHYERR_PARAM_NOVAL 65535 737 #define HAL_PHYERR_PARAM_ENABLE 0x8000 /* Enable/Disable if applicable */ 738 739 /* 740 * DFS operating mode flags. 741 */ 742 typedef enum { 743 HAL_DFS_UNINIT_DOMAIN = 0, /* Uninitialized dfs domain */ 744 HAL_DFS_FCC_DOMAIN = 1, /* FCC3 dfs domain */ 745 HAL_DFS_ETSI_DOMAIN = 2, /* ETSI dfs domain */ 746 HAL_DFS_MKK4_DOMAIN = 3, /* Japan dfs domain */ 747 } HAL_DFS_DOMAIN; 748 749 /* 750 * Flag for setting QUIET period 751 */ 752 typedef enum { 753 HAL_QUIET_DISABLE = 0x0, 754 HAL_QUIET_ENABLE = 0x1, 755 HAL_QUIET_ADD_CURRENT_TSF = 0x2, /* add current TSF to next_start offset */ 756 HAL_QUIET_ADD_SWBA_RESP_TIME = 0x4, /* add beacon response time to next_start offset */ 757 } HAL_QUIET_FLAG; 758 759 #define HAL_DFS_EVENT_PRICH 0x0000001 760 #define HAL_DFS_EVENT_EXTCH 0x0000002 761 #define HAL_DFS_EVENT_EXTEARLY 0x0000004 762 #define HAL_DFS_EVENT_ISDC 0x0000008 763 764 struct hal_dfs_event { 765 uint64_t re_full_ts; /* 64-bit full timestamp from interrupt time */ 766 uint32_t re_ts; /* Original 15 bit recv timestamp */ 767 uint8_t re_rssi; /* rssi of radar event */ 768 uint8_t re_dur; /* duration of radar pulse */ 769 uint32_t re_flags; /* Flags (see above) */ 770 }; 771 typedef struct hal_dfs_event HAL_DFS_EVENT; 772 773 typedef struct 774 { 775 int ah_debug; /* only used if AH_DEBUG is defined */ 776 int ah_ar5416_biasadj; /* enable AR2133 radio specific bias fiddling */ 777 778 /* NB: these are deprecated; they exist for now for compatibility */ 779 int ah_dma_beacon_response_time;/* in TU's */ 780 int ah_sw_beacon_response_time; /* in TU's */ 781 int ah_additional_swba_backoff; /* in TU's */ 782 } HAL_OPS_CONFIG; 783 784 /* 785 * Hardware Access Layer (HAL) API. 786 * 787 * Clients of the HAL call ath_hal_attach to obtain a reference to an 788 * ath_hal structure for use with the device. Hardware-related operations 789 * that follow must call back into the HAL through interface, supplying 790 * the reference as the first parameter. Note that before using the 791 * reference returned by ath_hal_attach the caller should verify the 792 * ABI version number. 793 */ 794 struct ath_hal { 795 uint32_t ah_magic; /* consistency check magic number */ 796 uint16_t ah_devid; /* PCI device ID */ 797 uint16_t ah_subvendorid; /* PCI subvendor ID */ 798 HAL_SOFTC ah_sc; /* back pointer to driver/os state */ 799 HAL_BUS_TAG ah_st; /* params for register r+w */ 800 HAL_BUS_HANDLE ah_sh; 801 HAL_CTRY_CODE ah_countryCode; 802 803 uint32_t ah_macVersion; /* MAC version id */ 804 uint16_t ah_macRev; /* MAC revision */ 805 uint16_t ah_phyRev; /* PHY revision */ 806 /* NB: when only one radio is present the rev is in 5Ghz */ 807 uint16_t ah_analog5GhzRev;/* 5GHz radio revision */ 808 uint16_t ah_analog2GhzRev;/* 2GHz radio revision */ 809 810 uint16_t *ah_eepromdata; /* eeprom buffer, if needed */ 811 812 HAL_OPS_CONFIG ah_config; 813 const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *, 814 u_int mode); 815 void __ahdecl(*ah_detach)(struct ath_hal*); 816 817 /* Reset functions */ 818 HAL_BOOL __ahdecl(*ah_reset)(struct ath_hal *, HAL_OPMODE, 819 struct ieee80211_channel *, 820 HAL_BOOL bChannelChange, HAL_STATUS *status); 821 HAL_BOOL __ahdecl(*ah_phyDisable)(struct ath_hal *); 822 HAL_BOOL __ahdecl(*ah_disable)(struct ath_hal *); 823 void __ahdecl(*ah_configPCIE)(struct ath_hal *, HAL_BOOL restore); 824 void __ahdecl(*ah_disablePCIE)(struct ath_hal *); 825 void __ahdecl(*ah_setPCUConfig)(struct ath_hal *); 826 HAL_BOOL __ahdecl(*ah_perCalibration)(struct ath_hal*, 827 struct ieee80211_channel *, HAL_BOOL *); 828 HAL_BOOL __ahdecl(*ah_perCalibrationN)(struct ath_hal *, 829 struct ieee80211_channel *, u_int chainMask, 830 HAL_BOOL longCal, HAL_BOOL *isCalDone); 831 HAL_BOOL __ahdecl(*ah_resetCalValid)(struct ath_hal *, 832 const struct ieee80211_channel *); 833 HAL_BOOL __ahdecl(*ah_setTxPower)(struct ath_hal *, 834 const struct ieee80211_channel *, uint16_t *); 835 HAL_BOOL __ahdecl(*ah_setTxPowerLimit)(struct ath_hal *, uint32_t); 836 HAL_BOOL __ahdecl(*ah_setBoardValues)(struct ath_hal *, 837 const struct ieee80211_channel *); 838 839 /* Transmit functions */ 840 HAL_BOOL __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*, 841 HAL_BOOL incTrigLevel); 842 int __ahdecl(*ah_setupTxQueue)(struct ath_hal *, HAL_TX_QUEUE, 843 const HAL_TXQ_INFO *qInfo); 844 HAL_BOOL __ahdecl(*ah_setTxQueueProps)(struct ath_hal *, int q, 845 const HAL_TXQ_INFO *qInfo); 846 HAL_BOOL __ahdecl(*ah_getTxQueueProps)(struct ath_hal *, int q, 847 HAL_TXQ_INFO *qInfo); 848 HAL_BOOL __ahdecl(*ah_releaseTxQueue)(struct ath_hal *ah, u_int q); 849 HAL_BOOL __ahdecl(*ah_resetTxQueue)(struct ath_hal *ah, u_int q); 850 uint32_t __ahdecl(*ah_getTxDP)(struct ath_hal*, u_int); 851 HAL_BOOL __ahdecl(*ah_setTxDP)(struct ath_hal*, u_int, uint32_t txdp); 852 uint32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, u_int q); 853 HAL_BOOL __ahdecl(*ah_startTxDma)(struct ath_hal*, u_int); 854 HAL_BOOL __ahdecl(*ah_stopTxDma)(struct ath_hal*, u_int); 855 HAL_BOOL __ahdecl(*ah_setupTxDesc)(struct ath_hal *, struct ath_desc *, 856 u_int pktLen, u_int hdrLen, 857 HAL_PKT_TYPE type, u_int txPower, 858 u_int txRate0, u_int txTries0, 859 u_int keyIx, u_int antMode, u_int flags, 860 u_int rtsctsRate, u_int rtsctsDuration, 861 u_int compicvLen, u_int compivLen, 862 u_int comp); 863 HAL_BOOL __ahdecl(*ah_setupXTxDesc)(struct ath_hal *, struct ath_desc*, 864 u_int txRate1, u_int txTries1, 865 u_int txRate2, u_int txTries2, 866 u_int txRate3, u_int txTries3); 867 HAL_BOOL __ahdecl(*ah_fillTxDesc)(struct ath_hal *, struct ath_desc *, 868 u_int segLen, HAL_BOOL firstSeg, 869 HAL_BOOL lastSeg, const struct ath_desc *); 870 HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *, 871 struct ath_desc *, struct ath_tx_status *); 872 void __ahdecl(*ah_getTxIntrQueue)(struct ath_hal *, uint32_t *); 873 void __ahdecl(*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc*); 874 HAL_BOOL __ahdecl(*ah_getTxCompletionRates)(struct ath_hal *, 875 const struct ath_desc *ds, int *rates, int *tries); 876 877 /* Receive Functions */ 878 uint32_t __ahdecl(*ah_getRxDP)(struct ath_hal*); 879 void __ahdecl(*ah_setRxDP)(struct ath_hal*, uint32_t rxdp); 880 void __ahdecl(*ah_enableReceive)(struct ath_hal*); 881 HAL_BOOL __ahdecl(*ah_stopDmaReceive)(struct ath_hal*); 882 void __ahdecl(*ah_startPcuReceive)(struct ath_hal*); 883 void __ahdecl(*ah_stopPcuReceive)(struct ath_hal*); 884 void __ahdecl(*ah_setMulticastFilter)(struct ath_hal*, 885 uint32_t filter0, uint32_t filter1); 886 HAL_BOOL __ahdecl(*ah_setMulticastFilterIndex)(struct ath_hal*, 887 uint32_t index); 888 HAL_BOOL __ahdecl(*ah_clrMulticastFilterIndex)(struct ath_hal*, 889 uint32_t index); 890 uint32_t __ahdecl(*ah_getRxFilter)(struct ath_hal*); 891 void __ahdecl(*ah_setRxFilter)(struct ath_hal*, uint32_t); 892 HAL_BOOL __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_desc *, 893 uint32_t size, u_int flags); 894 HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *, 895 struct ath_desc *, uint32_t phyAddr, 896 struct ath_desc *next, uint64_t tsf, 897 struct ath_rx_status *); 898 void __ahdecl(*ah_rxMonitor)(struct ath_hal *, 899 const HAL_NODE_STATS *, 900 const struct ieee80211_channel *); 901 void __ahdecl(*ah_aniPoll)(struct ath_hal *, 902 const struct ieee80211_channel *); 903 void __ahdecl(*ah_procMibEvent)(struct ath_hal *, 904 const HAL_NODE_STATS *); 905 void __ahdecl(*ah_rxAntCombDiversity)(struct ath_hal *, 906 struct ath_rx_status *, 907 unsigned long, int); 908 909 /* Misc Functions */ 910 HAL_STATUS __ahdecl(*ah_getCapability)(struct ath_hal *, 911 HAL_CAPABILITY_TYPE, uint32_t capability, 912 uint32_t *result); 913 HAL_BOOL __ahdecl(*ah_setCapability)(struct ath_hal *, 914 HAL_CAPABILITY_TYPE, uint32_t capability, 915 uint32_t setting, HAL_STATUS *); 916 HAL_BOOL __ahdecl(*ah_getDiagState)(struct ath_hal *, int request, 917 const void *args, uint32_t argsize, 918 void **result, uint32_t *resultsize); 919 void __ahdecl(*ah_getMacAddress)(struct ath_hal *, uint8_t *); 920 HAL_BOOL __ahdecl(*ah_setMacAddress)(struct ath_hal *, const uint8_t*); 921 void __ahdecl(*ah_getBssIdMask)(struct ath_hal *, uint8_t *); 922 HAL_BOOL __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const uint8_t*); 923 HAL_BOOL __ahdecl(*ah_setRegulatoryDomain)(struct ath_hal*, 924 uint16_t, HAL_STATUS *); 925 void __ahdecl(*ah_setLedState)(struct ath_hal*, HAL_LED_STATE); 926 void __ahdecl(*ah_writeAssocid)(struct ath_hal*, 927 const uint8_t *bssid, uint16_t assocId); 928 HAL_BOOL __ahdecl(*ah_gpioCfgOutput)(struct ath_hal *, 929 uint32_t gpio, HAL_GPIO_MUX_TYPE); 930 HAL_BOOL __ahdecl(*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio); 931 uint32_t __ahdecl(*ah_gpioGet)(struct ath_hal *, uint32_t gpio); 932 HAL_BOOL __ahdecl(*ah_gpioSet)(struct ath_hal *, 933 uint32_t gpio, uint32_t val); 934 void __ahdecl(*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t); 935 uint32_t __ahdecl(*ah_getTsf32)(struct ath_hal*); 936 uint64_t __ahdecl(*ah_getTsf64)(struct ath_hal*); 937 void __ahdecl(*ah_resetTsf)(struct ath_hal*); 938 HAL_BOOL __ahdecl(*ah_detectCardPresent)(struct ath_hal*); 939 void __ahdecl(*ah_updateMibCounters)(struct ath_hal*, 940 HAL_MIB_STATS*); 941 HAL_RFGAIN __ahdecl(*ah_getRfGain)(struct ath_hal*); 942 u_int __ahdecl(*ah_getDefAntenna)(struct ath_hal*); 943 void __ahdecl(*ah_setDefAntenna)(struct ath_hal*, u_int); 944 HAL_ANT_SETTING __ahdecl(*ah_getAntennaSwitch)(struct ath_hal*); 945 HAL_BOOL __ahdecl(*ah_setAntennaSwitch)(struct ath_hal*, 946 HAL_ANT_SETTING); 947 HAL_BOOL __ahdecl(*ah_setSifsTime)(struct ath_hal*, u_int); 948 u_int __ahdecl(*ah_getSifsTime)(struct ath_hal*); 949 HAL_BOOL __ahdecl(*ah_setSlotTime)(struct ath_hal*, u_int); 950 u_int __ahdecl(*ah_getSlotTime)(struct ath_hal*); 951 HAL_BOOL __ahdecl(*ah_setAckTimeout)(struct ath_hal*, u_int); 952 u_int __ahdecl(*ah_getAckTimeout)(struct ath_hal*); 953 HAL_BOOL __ahdecl(*ah_setAckCTSRate)(struct ath_hal*, u_int); 954 u_int __ahdecl(*ah_getAckCTSRate)(struct ath_hal*); 955 HAL_BOOL __ahdecl(*ah_setCTSTimeout)(struct ath_hal*, u_int); 956 u_int __ahdecl(*ah_getCTSTimeout)(struct ath_hal*); 957 HAL_BOOL __ahdecl(*ah_setDecompMask)(struct ath_hal*, uint16_t, int); 958 void __ahdecl(*ah_setCoverageClass)(struct ath_hal*, uint8_t, int); 959 HAL_STATUS __ahdecl(*ah_setQuiet)(struct ath_hal *ah, uint32_t period, 960 uint32_t duration, uint32_t nextStart, 961 HAL_QUIET_FLAG flag); 962 963 /* DFS functions */ 964 void __ahdecl(*ah_enableDfs)(struct ath_hal *ah, 965 HAL_PHYERR_PARAM *pe); 966 void __ahdecl(*ah_getDfsThresh)(struct ath_hal *ah, 967 HAL_PHYERR_PARAM *pe); 968 HAL_BOOL __ahdecl(*ah_procRadarEvent)(struct ath_hal *ah, 969 struct ath_rx_status *rxs, uint64_t fulltsf, 970 const char *buf, HAL_DFS_EVENT *event); 971 HAL_BOOL __ahdecl(*ah_isFastClockEnabled)(struct ath_hal *ah); 972 973 /* Key Cache Functions */ 974 uint32_t __ahdecl(*ah_getKeyCacheSize)(struct ath_hal*); 975 HAL_BOOL __ahdecl(*ah_resetKeyCacheEntry)(struct ath_hal*, uint16_t); 976 HAL_BOOL __ahdecl(*ah_isKeyCacheEntryValid)(struct ath_hal *, 977 uint16_t); 978 HAL_BOOL __ahdecl(*ah_setKeyCacheEntry)(struct ath_hal*, 979 uint16_t, const HAL_KEYVAL *, 980 const uint8_t *, int); 981 HAL_BOOL __ahdecl(*ah_setKeyCacheEntryMac)(struct ath_hal*, 982 uint16_t, const uint8_t *); 983 984 /* Power Management Functions */ 985 HAL_BOOL __ahdecl(*ah_setPowerMode)(struct ath_hal*, 986 HAL_POWER_MODE mode, int setChip); 987 HAL_POWER_MODE __ahdecl(*ah_getPowerMode)(struct ath_hal*); 988 int16_t __ahdecl(*ah_getChanNoise)(struct ath_hal *, 989 const struct ieee80211_channel *); 990 991 /* Beacon Management Functions */ 992 void __ahdecl(*ah_setBeaconTimers)(struct ath_hal*, 993 const HAL_BEACON_TIMERS *); 994 /* NB: deprecated, use ah_setBeaconTimers instead */ 995 void __ahdecl(*ah_beaconInit)(struct ath_hal *, 996 uint32_t nexttbtt, uint32_t intval); 997 void __ahdecl(*ah_setStationBeaconTimers)(struct ath_hal*, 998 const HAL_BEACON_STATE *); 999 void __ahdecl(*ah_resetStationBeaconTimers)(struct ath_hal*); 1000 uint64_t __ahdecl(*ah_getNextTBTT)(struct ath_hal *); 1001 1002 /* 802.11n Functions */ 1003 HAL_BOOL __ahdecl(*ah_chainTxDesc)(struct ath_hal *, 1004 struct ath_desc *, u_int, u_int, HAL_PKT_TYPE, 1005 u_int, HAL_CIPHER, uint8_t, u_int, HAL_BOOL, 1006 HAL_BOOL); 1007 HAL_BOOL __ahdecl(*ah_setupFirstTxDesc)(struct ath_hal *, 1008 struct ath_desc *, u_int, u_int, u_int, 1009 u_int, u_int, u_int, u_int, u_int); 1010 HAL_BOOL __ahdecl(*ah_setupLastTxDesc)(struct ath_hal *, 1011 struct ath_desc *, const struct ath_desc *); 1012 void __ahdecl(*ah_set11nRateScenario)(struct ath_hal *, 1013 struct ath_desc *, u_int, u_int, 1014 HAL_11N_RATE_SERIES [], u_int, u_int); 1015 void __ahdecl(*ah_set11nAggrMiddle)(struct ath_hal *, 1016 struct ath_desc *, u_int); 1017 void __ahdecl(*ah_clr11nAggr)(struct ath_hal *, 1018 struct ath_desc *); 1019 void __ahdecl(*ah_set11nBurstDuration)(struct ath_hal *, 1020 struct ath_desc *, u_int); 1021 uint32_t __ahdecl(*ah_get11nExtBusy)(struct ath_hal *); 1022 void __ahdecl(*ah_set11nMac2040)(struct ath_hal *, 1023 HAL_HT_MACMODE); 1024 HAL_HT_RXCLEAR __ahdecl(*ah_get11nRxClear)(struct ath_hal *ah); 1025 void __ahdecl(*ah_set11nRxClear)(struct ath_hal *, 1026 HAL_HT_RXCLEAR); 1027 1028 /* Interrupt functions */ 1029 HAL_BOOL __ahdecl(*ah_isInterruptPending)(struct ath_hal*); 1030 HAL_BOOL __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT*); 1031 HAL_INT __ahdecl(*ah_getInterrupts)(struct ath_hal*); 1032 HAL_INT __ahdecl(*ah_setInterrupts)(struct ath_hal*, HAL_INT); 1033 }; 1034 1035 /* 1036 * Check the PCI vendor ID and device ID against Atheros' values 1037 * and return a printable description for any Atheros hardware. 1038 * AH_NULL is returned if the ID's do not describe Atheros hardware. 1039 */ 1040 extern const char *__ahdecl ath_hal_probe(uint16_t vendorid, uint16_t devid); 1041 1042 /* 1043 * Attach the HAL for use with the specified device. The device is 1044 * defined by the PCI device ID. The caller provides an opaque pointer 1045 * to an upper-layer data structure (HAL_SOFTC) that is stored in the 1046 * HAL state block for later use. Hardware register accesses are done 1047 * using the specified bus tag and handle. On successful return a 1048 * reference to a state block is returned that must be supplied in all 1049 * subsequent HAL calls. Storage associated with this reference is 1050 * dynamically allocated and must be freed by calling the ah_detach 1051 * method when the client is done. If the attach operation fails a 1052 * null (AH_NULL) reference will be returned and a status code will 1053 * be returned if the status parameter is non-zero. 1054 */ 1055 extern struct ath_hal * __ahdecl ath_hal_attach(uint16_t devid, HAL_SOFTC, 1056 HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, HAL_STATUS* status); 1057 1058 extern const char *ath_hal_mac_name(struct ath_hal *); 1059 extern const char *ath_hal_rf_name(struct ath_hal *); 1060 1061 /* 1062 * Regulatory interfaces. Drivers should use ath_hal_init_channels to 1063 * request a set of channels for a particular country code and/or 1064 * regulatory domain. If CTRY_DEFAULT and SKU_NONE are specified then 1065 * this list is constructed according to the contents of the EEPROM. 1066 * ath_hal_getchannels acts similarly but does not alter the operating 1067 * state; this can be used to collect information for a particular 1068 * regulatory configuration. Finally ath_hal_set_channels installs a 1069 * channel list constructed outside the driver. The HAL will adopt the 1070 * channel list and setup internal state according to the specified 1071 * regulatory configuration (e.g. conformance test limits). 1072 * 1073 * For all interfaces the channel list is returned in the supplied array. 1074 * maxchans defines the maximum size of this array. nchans contains the 1075 * actual number of channels returned. If a problem occurred then a 1076 * status code != HAL_OK is returned. 1077 */ 1078 struct ieee80211_channel; 1079 1080 /* 1081 * Return a list of channels according to the specified regulatory. 1082 */ 1083 extern HAL_STATUS __ahdecl ath_hal_getchannels(struct ath_hal *, 1084 struct ieee80211_channel *chans, u_int maxchans, int *nchans, 1085 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn, 1086 HAL_BOOL enableExtendedChannels); 1087 1088 /* 1089 * Return a list of channels and install it as the current operating 1090 * regulatory list. 1091 */ 1092 extern HAL_STATUS __ahdecl ath_hal_init_channels(struct ath_hal *, 1093 struct ieee80211_channel *chans, u_int maxchans, int *nchans, 1094 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN rd, 1095 HAL_BOOL enableExtendedChannels); 1096 1097 /* 1098 * Install the list of channels as the current operating regulatory 1099 * and setup related state according to the country code and sku. 1100 */ 1101 extern HAL_STATUS __ahdecl ath_hal_set_channels(struct ath_hal *, 1102 struct ieee80211_channel *chans, int nchans, 1103 HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn); 1104 1105 /* 1106 * Fetch the ctl/ext noise floor values reported by a MIMO 1107 * radio. Returns 1 for valid results, 0 for invalid channel. 1108 */ 1109 extern int __ahdecl ath_hal_get_mimo_chan_noise(struct ath_hal *ah, 1110 const struct ieee80211_channel *chan, int16_t *nf_ctl, 1111 int16_t *nf_ext); 1112 1113 /* 1114 * Calibrate noise floor data following a channel scan or similar. 1115 * This must be called prior retrieving noise floor data. 1116 */ 1117 extern void __ahdecl ath_hal_process_noisefloor(struct ath_hal *ah); 1118 1119 /* 1120 * Return bit mask of wireless modes supported by the hardware. 1121 */ 1122 extern u_int __ahdecl ath_hal_getwirelessmodes(struct ath_hal*); 1123 1124 /* 1125 * Calculate the packet TX time for a legacy or 11n frame 1126 */ 1127 extern uint32_t __ahdecl ath_hal_pkt_txtime(struct ath_hal *ah, 1128 const HAL_RATE_TABLE *rates, uint32_t frameLen, 1129 uint16_t rateix, HAL_BOOL isht40, HAL_BOOL shortPreamble); 1130 1131 /* 1132 * Calculate the duration of an 11n frame. 1133 */ 1134 extern uint32_t __ahdecl ath_computedur_ht(uint32_t frameLen, uint16_t rate, 1135 int streams, HAL_BOOL isht40, HAL_BOOL isShortGI); 1136 1137 /* 1138 * Calculate the transmit duration of a legacy frame. 1139 */ 1140 extern uint16_t __ahdecl ath_hal_computetxtime(struct ath_hal *, 1141 const HAL_RATE_TABLE *rates, uint32_t frameLen, 1142 uint16_t rateix, HAL_BOOL shortPreamble); 1143 1144 /* 1145 * Adjust the TSF. 1146 */ 1147 extern void __ahdecl ath_hal_adjusttsf(struct ath_hal *ah, int32_t tsfdelta); 1148 1149 /* 1150 * Enable or disable CCA. 1151 */ 1152 void __ahdecl ath_hal_setcca(struct ath_hal *ah, int ena); 1153 1154 /* 1155 * Get CCA setting. 1156 */ 1157 int __ahdecl ath_hal_getcca(struct ath_hal *ah); 1158 1159 #endif /* _ATH_AH_H_ */ 1160