1 /* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19 20 #ifndef _ATH_AH_H_ 21 #define _ATH_AH_H_ 22 /* 23 * Atheros Hardware Access Layer 24 * 25 * Clients of the HAL call ath_hal_attach to obtain a reference to an ath_hal 26 * structure for use with the device. Hardware-related operations that 27 * follow must call back into the HAL through interface, supplying the 28 * reference as the first parameter. 29 */ 30 31 #include "ah_osdep.h" 32 33 /* 34 * __ahdecl is analogous to _cdecl; it defines the calling 35 * convention used within the HAL. For most systems this 36 * can just default to be empty and the compiler will (should) 37 * use _cdecl. For systems where _cdecl is not compatible this 38 * must be defined. See linux/ah_osdep.h for an example. 39 */ 40 #ifndef __ahdecl 41 #define __ahdecl 42 #endif 43 44 /* 45 * Status codes that may be returned by the HAL. Note that 46 * interfaces that return a status code set it only when an 47 * error occurs--i.e. you cannot check it for success. 48 */ 49 typedef enum { 50 HAL_OK = 0, /* No error */ 51 HAL_ENXIO = 1, /* No hardware present */ 52 HAL_ENOMEM = 2, /* Memory allocation failed */ 53 HAL_EIO = 3, /* Hardware didn't respond as expected */ 54 HAL_EEMAGIC = 4, /* EEPROM magic number invalid */ 55 HAL_EEVERSION = 5, /* EEPROM version invalid */ 56 HAL_EELOCKED = 6, /* EEPROM unreadable */ 57 HAL_EEBADSUM = 7, /* EEPROM checksum invalid */ 58 HAL_EEREAD = 8, /* EEPROM read problem */ 59 HAL_EEBADMAC = 9, /* EEPROM mac address invalid */ 60 HAL_EESIZE = 10, /* EEPROM size not supported */ 61 HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */ 62 HAL_EINVAL = 12, /* Invalid parameter to function */ 63 HAL_ENOTSUPP = 13, /* Hardware revision not supported */ 64 HAL_ESELFTEST = 14, /* Hardware self-test failed */ 65 HAL_EINPROGRESS = 15, /* Operation incomplete */ 66 HAL_EEBADREG = 16, /* EEPROM invalid regulatory contents */ 67 HAL_EEBADCC = 17, /* EEPROM invalid country code */ 68 } HAL_STATUS; 69 70 typedef enum { 71 AH_FALSE = 0, /* NB: lots of code assumes false is zero */ 72 AH_TRUE = 1, 73 } HAL_BOOL; 74 75 typedef enum { 76 HAL_CAP_REG_DMN = 0, /* current regulatory domain */ 77 HAL_CAP_CIPHER = 1, /* hardware supports cipher */ 78 HAL_CAP_TKIP_MIC = 2, /* handle TKIP MIC in hardware */ 79 HAL_CAP_TKIP_SPLIT = 3, /* hardware TKIP uses split keys */ 80 HAL_CAP_PHYCOUNTERS = 4, /* hardware PHY error counters */ 81 HAL_CAP_DIVERSITY = 5, /* hardware supports fast diversity */ 82 HAL_CAP_KEYCACHE_SIZE = 6, /* number of entries in key cache */ 83 HAL_CAP_NUM_TXQUEUES = 7, /* number of hardware xmit queues */ 84 HAL_CAP_VEOL = 9, /* hardware supports virtual EOL */ 85 HAL_CAP_PSPOLL = 10, /* hardware has working PS-Poll support */ 86 HAL_CAP_DIAG = 11, /* hardware diagnostic support */ 87 HAL_CAP_COMPRESSION = 12, /* hardware supports compression */ 88 HAL_CAP_BURST = 13, /* hardware supports packet bursting */ 89 HAL_CAP_FASTFRAME = 14, /* hardware supoprts fast frames */ 90 HAL_CAP_TXPOW = 15, /* global tx power limit */ 91 HAL_CAP_TPC = 16, /* per-packet tx power control */ 92 HAL_CAP_PHYDIAG = 17, /* hardware phy error diagnostic */ 93 HAL_CAP_BSSIDMASK = 18, /* hardware supports bssid mask */ 94 HAL_CAP_MCAST_KEYSRCH = 19, /* hardware has multicast key search */ 95 HAL_CAP_TSF_ADJUST = 20, /* hardware has beacon tsf adjust */ 96 /* 21 was HAL_CAP_XR */ 97 HAL_CAP_WME_TKIPMIC = 22, /* hardware can support TKIP MIC when WMM is turned on */ 98 /* 23 was HAL_CAP_CHAN_HALFRATE */ 99 /* 24 was HAL_CAP_CHAN_QUARTERRATE */ 100 HAL_CAP_RFSILENT = 25, /* hardware has rfsilent support */ 101 HAL_CAP_TPC_ACK = 26, /* ack txpower with per-packet tpc */ 102 HAL_CAP_TPC_CTS = 27, /* cts txpower with per-packet tpc */ 103 HAL_CAP_11D = 28, /* 11d beacon support for changing cc */ 104 HAL_CAP_INTMIT = 29, /* interference mitigation */ 105 HAL_CAP_RXORN_FATAL = 30, /* HAL_INT_RXORN treated as fatal */ 106 HAL_CAP_HT = 31, /* hardware can support HT */ 107 HAL_CAP_TX_CHAINMASK = 32, /* mask of TX chains supported */ 108 HAL_CAP_RX_CHAINMASK = 33, /* mask of RX chains supported */ 109 HAL_CAP_RXTSTAMP_PREC = 34, /* rx desc tstamp precision (bits) */ 110 HAL_CAP_BB_HANG = 35, /* can baseband hang */ 111 HAL_CAP_MAC_HANG = 36, /* can MAC hang */ 112 HAL_CAP_INTRMASK = 37, /* bitmask of supported interrupts */ 113 } HAL_CAPABILITY_TYPE; 114 115 /* 116 * "States" for setting the LED. These correspond to 117 * the possible 802.11 operational states and there may 118 * be a many-to-one mapping between these states and the 119 * actual hardware state for the LED's (i.e. the hardware 120 * may have fewer states). 121 */ 122 typedef enum { 123 HAL_LED_INIT = 0, 124 HAL_LED_SCAN = 1, 125 HAL_LED_AUTH = 2, 126 HAL_LED_ASSOC = 3, 127 HAL_LED_RUN = 4 128 } HAL_LED_STATE; 129 130 /* 131 * Transmit queue types/numbers. These are used to tag 132 * each transmit queue in the hardware and to identify a set 133 * of transmit queues for operations such as start/stop dma. 134 */ 135 typedef enum { 136 HAL_TX_QUEUE_INACTIVE = 0, /* queue is inactive/unused */ 137 HAL_TX_QUEUE_DATA = 1, /* data xmit q's */ 138 HAL_TX_QUEUE_BEACON = 2, /* beacon xmit q */ 139 HAL_TX_QUEUE_CAB = 3, /* "crap after beacon" xmit q */ 140 HAL_TX_QUEUE_UAPSD = 4, /* u-apsd power save xmit q */ 141 } HAL_TX_QUEUE; 142 143 #define HAL_NUM_TX_QUEUES 10 /* max possible # of queues */ 144 145 /* 146 * Transmit queue subtype. These map directly to 147 * WME Access Categories (except for UPSD). Refer 148 * to Table 5 of the WME spec. 149 */ 150 typedef enum { 151 HAL_WME_AC_BK = 0, /* background access category */ 152 HAL_WME_AC_BE = 1, /* best effort access category*/ 153 HAL_WME_AC_VI = 2, /* video access category */ 154 HAL_WME_AC_VO = 3, /* voice access category */ 155 HAL_WME_UPSD = 4, /* uplink power save */ 156 } HAL_TX_QUEUE_SUBTYPE; 157 158 /* 159 * Transmit queue flags that control various 160 * operational parameters. 161 */ 162 typedef enum { 163 /* 164 * Per queue interrupt enables. When set the associated 165 * interrupt may be delivered for packets sent through 166 * the queue. Without these enabled no interrupts will 167 * be delivered for transmits through the queue. 168 */ 169 HAL_TXQ_TXOKINT_ENABLE = 0x0001, /* enable TXOK interrupt */ 170 HAL_TXQ_TXERRINT_ENABLE = 0x0001, /* enable TXERR interrupt */ 171 HAL_TXQ_TXDESCINT_ENABLE = 0x0002, /* enable TXDESC interrupt */ 172 HAL_TXQ_TXEOLINT_ENABLE = 0x0004, /* enable TXEOL interrupt */ 173 HAL_TXQ_TXURNINT_ENABLE = 0x0008, /* enable TXURN interrupt */ 174 /* 175 * Enable hardware compression for packets sent through 176 * the queue. The compression buffer must be setup and 177 * packets must have a key entry marked in the tx descriptor. 178 */ 179 HAL_TXQ_COMPRESSION_ENABLE = 0x0010, /* enable h/w compression */ 180 /* 181 * Disable queue when veol is hit or ready time expires. 182 * By default the queue is disabled only on reaching the 183 * physical end of queue (i.e. a null link ptr in the 184 * descriptor chain). 185 */ 186 HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE = 0x0020, 187 /* 188 * Schedule frames on delivery of a DBA (DMA Beacon Alert) 189 * event. Frames will be transmitted only when this timer 190 * fires, e.g to transmit a beacon in ap or adhoc modes. 191 */ 192 HAL_TXQ_DBA_GATED = 0x0040, /* schedule based on DBA */ 193 /* 194 * Each transmit queue has a counter that is incremented 195 * each time the queue is enabled and decremented when 196 * the list of frames to transmit is traversed (or when 197 * the ready time for the queue expires). This counter 198 * must be non-zero for frames to be scheduled for 199 * transmission. The following controls disable bumping 200 * this counter under certain conditions. Typically this 201 * is used to gate frames based on the contents of another 202 * queue (e.g. CAB traffic may only follow a beacon frame). 203 * These are meaningful only when frames are scheduled 204 * with a non-ASAP policy (e.g. DBA-gated). 205 */ 206 HAL_TXQ_CBR_DIS_QEMPTY = 0x0080, /* disable on this q empty */ 207 HAL_TXQ_CBR_DIS_BEMPTY = 0x0100, /* disable on beacon q empty */ 208 209 /* 210 * Fragment burst backoff policy. Normally the no backoff 211 * is done after a successful transmission, the next fragment 212 * is sent at SIFS. If this flag is set backoff is done 213 * after each fragment, regardless whether it was ack'd or 214 * not, after the backoff count reaches zero a normal channel 215 * access procedure is done before the next transmit (i.e. 216 * wait AIFS instead of SIFS). 217 */ 218 HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE = 0x00800000, 219 /* 220 * Disable post-tx backoff following each frame. 221 */ 222 HAL_TXQ_BACKOFF_DISABLE = 0x00010000, /* disable post backoff */ 223 /* 224 * DCU arbiter lockout control. This controls how 225 * lower priority tx queues are handled with respect to 226 * to a specific queue when multiple queues have frames 227 * to send. No lockout means lower priority queues arbitrate 228 * concurrently with this queue. Intra-frame lockout 229 * means lower priority queues are locked out until the 230 * current frame transmits (e.g. including backoffs and bursting). 231 * Global lockout means nothing lower can arbitrary so 232 * long as there is traffic activity on this queue (frames, 233 * backoff, etc). 234 */ 235 HAL_TXQ_ARB_LOCKOUT_INTRA = 0x00020000, /* intra-frame lockout */ 236 HAL_TXQ_ARB_LOCKOUT_GLOBAL = 0x00040000, /* full lockout s */ 237 238 HAL_TXQ_IGNORE_VIRTCOL = 0x00080000, /* ignore virt collisions */ 239 HAL_TXQ_SEQNUM_INC_DIS = 0x00100000, /* disable seqnum increment */ 240 } HAL_TX_QUEUE_FLAGS; 241 242 typedef struct { 243 uint32_t tqi_ver; /* hal TXQ version */ 244 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* subtype if applicable */ 245 HAL_TX_QUEUE_FLAGS tqi_qflags; /* flags (see above) */ 246 uint32_t tqi_priority; /* (not used) */ 247 uint32_t tqi_aifs; /* aifs */ 248 uint32_t tqi_cwmin; /* cwMin */ 249 uint32_t tqi_cwmax; /* cwMax */ 250 uint16_t tqi_shretry; /* rts retry limit */ 251 uint16_t tqi_lgretry; /* long retry limit (not used)*/ 252 uint32_t tqi_cbrPeriod; /* CBR period (us) */ 253 uint32_t tqi_cbrOverflowLimit; /* threshold for CBROVF int */ 254 uint32_t tqi_burstTime; /* max burst duration (us) */ 255 uint32_t tqi_readyTime; /* frame schedule time (us) */ 256 uint32_t tqi_compBuf; /* comp buffer phys addr */ 257 } HAL_TXQ_INFO; 258 259 #define HAL_TQI_NONVAL 0xffff 260 261 /* token to use for aifs, cwmin, cwmax */ 262 #define HAL_TXQ_USEDEFAULT ((uint32_t) -1) 263 264 /* compression definitions */ 265 #define HAL_COMP_BUF_MAX_SIZE 9216 /* 9K */ 266 #define HAL_COMP_BUF_ALIGN_SIZE 512 267 268 /* 269 * Transmit packet types. This belongs in ah_desc.h, but 270 * is here so we can give a proper type to various parameters 271 * (and not require everyone include the file). 272 * 273 * NB: These values are intentionally assigned for 274 * direct use when setting up h/w descriptors. 275 */ 276 typedef enum { 277 HAL_PKT_TYPE_NORMAL = 0, 278 HAL_PKT_TYPE_ATIM = 1, 279 HAL_PKT_TYPE_PSPOLL = 2, 280 HAL_PKT_TYPE_BEACON = 3, 281 HAL_PKT_TYPE_PROBE_RESP = 4, 282 HAL_PKT_TYPE_CHIRP = 5, 283 HAL_PKT_TYPE_GRP_POLL = 6, 284 HAL_PKT_TYPE_AMPDU = 7, 285 } HAL_PKT_TYPE; 286 287 /* Rx Filter Frame Types */ 288 typedef enum { 289 HAL_RX_FILTER_UCAST = 0x00000001, /* Allow unicast frames */ 290 HAL_RX_FILTER_MCAST = 0x00000002, /* Allow multicast frames */ 291 HAL_RX_FILTER_BCAST = 0x00000004, /* Allow broadcast frames */ 292 HAL_RX_FILTER_CONTROL = 0x00000008, /* Allow control frames */ 293 HAL_RX_FILTER_BEACON = 0x00000010, /* Allow beacon frames */ 294 HAL_RX_FILTER_PROM = 0x00000020, /* Promiscuous mode */ 295 HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */ 296 HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */ 297 HAL_RX_FILTER_PHYRADAR = 0x00000200, /* Allow phy radar errors */ 298 HAL_RX_FILTER_COMPBAR = 0x00000400, /* Allow compressed BAR */ 299 } HAL_RX_FILTER; 300 301 typedef enum { 302 HAL_PM_AWAKE = 0, 303 HAL_PM_FULL_SLEEP = 1, 304 HAL_PM_NETWORK_SLEEP = 2, 305 HAL_PM_UNDEFINED = 3 306 } HAL_POWER_MODE; 307 308 /* 309 * NOTE WELL: 310 * These are mapped to take advantage of the common locations for many of 311 * the bits on all of the currently supported MAC chips. This is to make 312 * the ISR as efficient as possible, while still abstracting HW differences. 313 * When new hardware breaks this commonality this enumerated type, as well 314 * as the HAL functions using it, must be modified. All values are directly 315 * mapped unless commented otherwise. 316 */ 317 typedef enum { 318 HAL_INT_RX = 0x00000001, /* Non-common mapping */ 319 HAL_INT_RXDESC = 0x00000002, 320 HAL_INT_RXNOFRM = 0x00000008, 321 HAL_INT_RXEOL = 0x00000010, 322 HAL_INT_RXORN = 0x00000020, 323 HAL_INT_TX = 0x00000040, /* Non-common mapping */ 324 HAL_INT_TXDESC = 0x00000080, 325 HAL_INT_TXURN = 0x00000800, 326 HAL_INT_MIB = 0x00001000, 327 HAL_INT_RXPHY = 0x00004000, 328 HAL_INT_RXKCM = 0x00008000, 329 HAL_INT_SWBA = 0x00010000, 330 HAL_INT_BMISS = 0x00040000, 331 HAL_INT_BNR = 0x00100000, 332 HAL_INT_TIM = 0x00200000, /* Non-common mapping */ 333 HAL_INT_DTIM = 0x00400000, /* Non-common mapping */ 334 HAL_INT_DTIMSYNC= 0x00800000, /* Non-common mapping */ 335 HAL_INT_GPIO = 0x01000000, 336 HAL_INT_CABEND = 0x02000000, /* Non-common mapping */ 337 HAL_INT_TSFOOR = 0x04000000, /* Non-common mapping */ 338 HAL_INT_TBTT = 0x08000000, /* Non-common mapping */ 339 HAL_INT_CST = 0x10000000, /* Non-common mapping */ 340 HAL_INT_GTT = 0x20000000, /* Non-common mapping */ 341 HAL_INT_FATAL = 0x40000000, /* Non-common mapping */ 342 #define HAL_INT_GLOBAL 0x80000000 /* Set/clear IER */ 343 HAL_INT_BMISC = HAL_INT_TIM 344 | HAL_INT_DTIM 345 | HAL_INT_DTIMSYNC 346 | HAL_INT_CABEND 347 | HAL_INT_TBTT, 348 349 /* Interrupt bits that map directly to ISR/IMR bits */ 350 HAL_INT_COMMON = HAL_INT_RXNOFRM 351 | HAL_INT_RXDESC 352 | HAL_INT_RXEOL 353 | HAL_INT_RXORN 354 | HAL_INT_TXDESC 355 | HAL_INT_TXURN 356 | HAL_INT_MIB 357 | HAL_INT_RXPHY 358 | HAL_INT_RXKCM 359 | HAL_INT_SWBA 360 | HAL_INT_BMISS 361 | HAL_INT_BNR 362 | HAL_INT_GPIO, 363 } HAL_INT; 364 365 typedef enum { 366 HAL_GPIO_MUX_OUTPUT = 0, 367 HAL_GPIO_MUX_PCIE_ATTENTION_LED = 1, 368 HAL_GPIO_MUX_PCIE_POWER_LED = 2, 369 HAL_GPIO_MUX_TX_FRAME = 3, 370 HAL_GPIO_MUX_RX_CLEAR_EXTERNAL = 4, 371 HAL_GPIO_MUX_MAC_NETWORK_LED = 5, 372 HAL_GPIO_MUX_MAC_POWER_LED = 6 373 } HAL_GPIO_MUX_TYPE; 374 375 typedef enum { 376 HAL_GPIO_INTR_LOW = 0, 377 HAL_GPIO_INTR_HIGH = 1, 378 HAL_GPIO_INTR_DISABLE = 2 379 } HAL_GPIO_INTR_TYPE; 380 381 typedef enum { 382 HAL_RFGAIN_INACTIVE = 0, 383 HAL_RFGAIN_READ_REQUESTED = 1, 384 HAL_RFGAIN_NEED_CHANGE = 2 385 } HAL_RFGAIN; 386 387 typedef uint16_t HAL_CTRY_CODE; /* country code */ 388 typedef uint16_t HAL_REG_DOMAIN; /* regulatory domain code */ 389 390 #define HAL_ANTENNA_MIN_MODE 0 391 #define HAL_ANTENNA_FIXED_A 1 392 #define HAL_ANTENNA_FIXED_B 2 393 #define HAL_ANTENNA_MAX_MODE 3 394 395 typedef struct { 396 uint32_t ackrcv_bad; 397 uint32_t rts_bad; 398 uint32_t rts_good; 399 uint32_t fcs_bad; 400 uint32_t beacons; 401 } HAL_MIB_STATS; 402 403 enum { 404 HAL_MODE_11A = 0x001, /* 11a channels */ 405 HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */ 406 HAL_MODE_11B = 0x004, /* 11b channels */ 407 HAL_MODE_PUREG = 0x008, /* 11g channels (OFDM only) */ 408 #ifdef notdef 409 HAL_MODE_11G = 0x010, /* 11g channels (OFDM/CCK) */ 410 #else 411 HAL_MODE_11G = 0x008, /* XXX historical */ 412 #endif 413 HAL_MODE_108G = 0x020, /* 11g+Turbo channels */ 414 HAL_MODE_108A = 0x040, /* 11a+Turbo channels */ 415 HAL_MODE_11A_HALF_RATE = 0x200, /* 11a half width channels */ 416 HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11a quarter width channels */ 417 HAL_MODE_11G_HALF_RATE = 0x800, /* 11g half width channels */ 418 HAL_MODE_11G_QUARTER_RATE = 0x1000, /* 11g quarter width channels */ 419 HAL_MODE_11NG_HT20 = 0x008000, 420 HAL_MODE_11NA_HT20 = 0x010000, 421 HAL_MODE_11NG_HT40PLUS = 0x020000, 422 HAL_MODE_11NG_HT40MINUS = 0x040000, 423 HAL_MODE_11NA_HT40PLUS = 0x080000, 424 HAL_MODE_11NA_HT40MINUS = 0x100000, 425 HAL_MODE_ALL = 0xffffff 426 }; 427 428 typedef struct { 429 int rateCount; /* NB: for proper padding */ 430 uint8_t rateCodeToIndex[144]; /* back mapping */ 431 struct { 432 uint8_t valid; /* valid for rate control use */ 433 uint8_t phy; /* CCK/OFDM/XR */ 434 uint32_t rateKbps; /* transfer rate in kbs */ 435 uint8_t rateCode; /* rate for h/w descriptors */ 436 uint8_t shortPreamble; /* mask for enabling short 437 * preamble in CCK rate code */ 438 uint8_t dot11Rate; /* value for supported rates 439 * info element of MLME */ 440 uint8_t controlRate; /* index of next lower basic 441 * rate; used for dur. calcs */ 442 uint16_t lpAckDuration; /* long preamble ACK duration */ 443 uint16_t spAckDuration; /* short preamble ACK duration*/ 444 } info[32]; 445 } HAL_RATE_TABLE; 446 447 typedef struct { 448 u_int rs_count; /* number of valid entries */ 449 uint8_t rs_rates[32]; /* rates */ 450 } HAL_RATE_SET; 451 452 /* 453 * 802.11n specific structures and enums 454 */ 455 typedef enum { 456 HAL_CHAINTYPE_TX = 1, /* Tx chain type */ 457 HAL_CHAINTYPE_RX = 2, /* RX chain type */ 458 } HAL_CHAIN_TYPE; 459 460 typedef struct { 461 u_int Tries; 462 u_int Rate; 463 u_int PktDuration; 464 u_int ChSel; 465 u_int RateFlags; 466 #define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */ 467 #define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */ 468 #define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */ 469 } HAL_11N_RATE_SERIES; 470 471 typedef enum { 472 HAL_HT_MACMODE_20 = 0, /* 20 MHz operation */ 473 HAL_HT_MACMODE_2040 = 1, /* 20/40 MHz operation */ 474 } HAL_HT_MACMODE; 475 476 typedef enum { 477 HAL_HT_PHYMODE_20 = 0, /* 20 MHz operation */ 478 HAL_HT_PHYMODE_2040 = 1, /* 20/40 MHz operation */ 479 } HAL_HT_PHYMODE; 480 481 typedef enum { 482 HAL_HT_EXTPROTSPACING_20 = 0, /* 20 MHz spacing */ 483 HAL_HT_EXTPROTSPACING_25 = 1, /* 25 MHz spacing */ 484 } HAL_HT_EXTPROTSPACING; 485 486 487 typedef enum { 488 HAL_RX_CLEAR_CTL_LOW = 0x1, /* force control channel to appear busy */ 489 HAL_RX_CLEAR_EXT_LOW = 0x2, /* force extension channel to appear busy */ 490 } HAL_HT_RXCLEAR; 491 492 /* 493 * Antenna switch control. By default antenna selection 494 * enables multiple (2) antenna use. To force use of the 495 * A or B antenna only specify a fixed setting. Fixing 496 * the antenna will also disable any diversity support. 497 */ 498 typedef enum { 499 HAL_ANT_VARIABLE = 0, /* variable by programming */ 500 HAL_ANT_FIXED_A = 1, /* fixed antenna A */ 501 HAL_ANT_FIXED_B = 2, /* fixed antenna B */ 502 } HAL_ANT_SETTING; 503 504 typedef enum { 505 HAL_M_STA = 1, /* infrastructure station */ 506 HAL_M_IBSS = 0, /* IBSS (adhoc) station */ 507 HAL_M_HOSTAP = 6, /* Software Access Point */ 508 HAL_M_MONITOR = 8 /* Monitor mode */ 509 } HAL_OPMODE; 510 511 typedef struct { 512 uint8_t kv_type; /* one of HAL_CIPHER */ 513 uint8_t kv_pad; 514 uint16_t kv_len; /* length in bits */ 515 uint8_t kv_val[16]; /* enough for 128-bit keys */ 516 uint8_t kv_mic[8]; /* TKIP MIC key */ 517 uint8_t kv_txmic[8]; /* TKIP TX MIC key (optional) */ 518 } HAL_KEYVAL; 519 520 typedef enum { 521 HAL_CIPHER_WEP = 0, 522 HAL_CIPHER_AES_OCB = 1, 523 HAL_CIPHER_AES_CCM = 2, 524 HAL_CIPHER_CKIP = 3, 525 HAL_CIPHER_TKIP = 4, 526 HAL_CIPHER_CLR = 5, /* no encryption */ 527 528 HAL_CIPHER_MIC = 127 /* TKIP-MIC, not a cipher */ 529 } HAL_CIPHER; 530 531 enum { 532 HAL_SLOT_TIME_6 = 6, /* NB: for turbo mode */ 533 HAL_SLOT_TIME_9 = 9, 534 HAL_SLOT_TIME_20 = 20, 535 }; 536 537 /* 538 * Per-station beacon timer state. Note that the specified 539 * beacon interval (given in TU's) can also include flags 540 * to force a TSF reset and to enable the beacon xmit logic. 541 * If bs_cfpmaxduration is non-zero the hardware is setup to 542 * coexist with a PCF-capable AP. 543 */ 544 typedef struct { 545 uint32_t bs_nexttbtt; /* next beacon in TU */ 546 uint32_t bs_nextdtim; /* next DTIM in TU */ 547 uint32_t bs_intval; /* beacon interval+flags */ 548 #define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */ 549 #define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */ 550 #define HAL_BEACON_RESET_TSF 0x01000000 /* clear TSF */ 551 uint32_t bs_dtimperiod; 552 uint16_t bs_cfpperiod; /* CFP period in TU */ 553 uint16_t bs_cfpmaxduration; /* max CFP duration in TU */ 554 uint32_t bs_cfpnext; /* next CFP in TU */ 555 uint16_t bs_timoffset; /* byte offset to TIM bitmap */ 556 uint16_t bs_bmissthreshold; /* beacon miss threshold */ 557 uint32_t bs_sleepduration; /* max sleep duration */ 558 } HAL_BEACON_STATE; 559 560 /* 561 * Like HAL_BEACON_STATE but for non-station mode setup. 562 * NB: see above flag definitions for bt_intval. 563 */ 564 typedef struct { 565 uint32_t bt_intval; /* beacon interval+flags */ 566 uint32_t bt_nexttbtt; /* next beacon in TU */ 567 uint32_t bt_nextatim; /* next ATIM in TU */ 568 uint32_t bt_nextdba; /* next DBA in 1/8th TU */ 569 uint32_t bt_nextswba; /* next SWBA in 1/8th TU */ 570 uint32_t bt_flags; /* timer enables */ 571 #define HAL_BEACON_TBTT_EN 0x00000001 572 #define HAL_BEACON_DBA_EN 0x00000002 573 #define HAL_BEACON_SWBA_EN 0x00000004 574 } HAL_BEACON_TIMERS; 575 576 /* 577 * Per-node statistics maintained by the driver for use in 578 * optimizing signal quality and other operational aspects. 579 */ 580 typedef struct { 581 uint32_t ns_avgbrssi; /* average beacon rssi */ 582 uint32_t ns_avgrssi; /* average data rssi */ 583 uint32_t ns_avgtxrssi; /* average tx rssi */ 584 } HAL_NODE_STATS; 585 586 #define HAL_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */ 587 588 struct ath_desc; 589 struct ath_tx_status; 590 struct ath_rx_status; 591 struct ieee80211_channel; 592 593 /* 594 * Hardware Access Layer (HAL) API. 595 * 596 * Clients of the HAL call ath_hal_attach to obtain a reference to an 597 * ath_hal structure for use with the device. Hardware-related operations 598 * that follow must call back into the HAL through interface, supplying 599 * the reference as the first parameter. Note that before using the 600 * reference returned by ath_hal_attach the caller should verify the 601 * ABI version number. 602 */ 603 struct ath_hal { 604 uint32_t ah_magic; /* consistency check magic number */ 605 uint16_t ah_devid; /* PCI device ID */ 606 uint16_t ah_subvendorid; /* PCI subvendor ID */ 607 HAL_SOFTC ah_sc; /* back pointer to driver/os state */ 608 HAL_BUS_TAG ah_st; /* params for register r+w */ 609 HAL_BUS_HANDLE ah_sh; 610 HAL_CTRY_CODE ah_countryCode; 611 612 uint32_t ah_macVersion; /* MAC version id */ 613 uint16_t ah_macRev; /* MAC revision */ 614 uint16_t ah_phyRev; /* PHY revision */ 615 /* NB: when only one radio is present the rev is in 5Ghz */ 616 uint16_t ah_analog5GhzRev;/* 5GHz radio revision */ 617 uint16_t ah_analog2GhzRev;/* 2GHz radio revision */ 618 619 const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *, 620 u_int mode); 621 void __ahdecl(*ah_detach)(struct ath_hal*); 622 623 /* Reset functions */ 624 HAL_BOOL __ahdecl(*ah_reset)(struct ath_hal *, HAL_OPMODE, 625 struct ieee80211_channel *, 626 HAL_BOOL bChannelChange, HAL_STATUS *status); 627 HAL_BOOL __ahdecl(*ah_phyDisable)(struct ath_hal *); 628 HAL_BOOL __ahdecl(*ah_disable)(struct ath_hal *); 629 void __ahdecl(*ah_configPCIE)(struct ath_hal *, HAL_BOOL restore); 630 void __ahdecl(*ah_disablePCIE)(struct ath_hal *); 631 void __ahdecl(*ah_setPCUConfig)(struct ath_hal *); 632 HAL_BOOL __ahdecl(*ah_perCalibration)(struct ath_hal*, 633 struct ieee80211_channel *, HAL_BOOL *); 634 HAL_BOOL __ahdecl(*ah_perCalibrationN)(struct ath_hal *, 635 struct ieee80211_channel *, u_int chainMask, 636 HAL_BOOL longCal, HAL_BOOL *isCalDone); 637 HAL_BOOL __ahdecl(*ah_resetCalValid)(struct ath_hal *, 638 const struct ieee80211_channel *); 639 HAL_BOOL __ahdecl(*ah_setTxPowerLimit)(struct ath_hal *, uint32_t); 640 641 /* Transmit functions */ 642 HAL_BOOL __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*, 643 HAL_BOOL incTrigLevel); 644 int __ahdecl(*ah_setupTxQueue)(struct ath_hal *, HAL_TX_QUEUE, 645 const HAL_TXQ_INFO *qInfo); 646 HAL_BOOL __ahdecl(*ah_setTxQueueProps)(struct ath_hal *, int q, 647 const HAL_TXQ_INFO *qInfo); 648 HAL_BOOL __ahdecl(*ah_getTxQueueProps)(struct ath_hal *, int q, 649 HAL_TXQ_INFO *qInfo); 650 HAL_BOOL __ahdecl(*ah_releaseTxQueue)(struct ath_hal *ah, u_int q); 651 HAL_BOOL __ahdecl(*ah_resetTxQueue)(struct ath_hal *ah, u_int q); 652 uint32_t __ahdecl(*ah_getTxDP)(struct ath_hal*, u_int); 653 HAL_BOOL __ahdecl(*ah_setTxDP)(struct ath_hal*, u_int, uint32_t txdp); 654 uint32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, u_int q); 655 HAL_BOOL __ahdecl(*ah_startTxDma)(struct ath_hal*, u_int); 656 HAL_BOOL __ahdecl(*ah_stopTxDma)(struct ath_hal*, u_int); 657 HAL_BOOL __ahdecl(*ah_setupTxDesc)(struct ath_hal *, struct ath_desc *, 658 u_int pktLen, u_int hdrLen, 659 HAL_PKT_TYPE type, u_int txPower, 660 u_int txRate0, u_int txTries0, 661 u_int keyIx, u_int antMode, u_int flags, 662 u_int rtsctsRate, u_int rtsctsDuration, 663 u_int compicvLen, u_int compivLen, 664 u_int comp); 665 HAL_BOOL __ahdecl(*ah_setupXTxDesc)(struct ath_hal *, struct ath_desc*, 666 u_int txRate1, u_int txTries1, 667 u_int txRate2, u_int txTries2, 668 u_int txRate3, u_int txTries3); 669 HAL_BOOL __ahdecl(*ah_fillTxDesc)(struct ath_hal *, struct ath_desc *, 670 u_int segLen, HAL_BOOL firstSeg, 671 HAL_BOOL lastSeg, const struct ath_desc *); 672 HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *, 673 struct ath_desc *, struct ath_tx_status *); 674 void __ahdecl(*ah_getTxIntrQueue)(struct ath_hal *, uint32_t *); 675 void __ahdecl(*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc*); 676 677 /* Receive Functions */ 678 uint32_t __ahdecl(*ah_getRxDP)(struct ath_hal*); 679 void __ahdecl(*ah_setRxDP)(struct ath_hal*, uint32_t rxdp); 680 void __ahdecl(*ah_enableReceive)(struct ath_hal*); 681 HAL_BOOL __ahdecl(*ah_stopDmaReceive)(struct ath_hal*); 682 void __ahdecl(*ah_startPcuReceive)(struct ath_hal*); 683 void __ahdecl(*ah_stopPcuReceive)(struct ath_hal*); 684 void __ahdecl(*ah_setMulticastFilter)(struct ath_hal*, 685 uint32_t filter0, uint32_t filter1); 686 HAL_BOOL __ahdecl(*ah_setMulticastFilterIndex)(struct ath_hal*, 687 uint32_t index); 688 HAL_BOOL __ahdecl(*ah_clrMulticastFilterIndex)(struct ath_hal*, 689 uint32_t index); 690 uint32_t __ahdecl(*ah_getRxFilter)(struct ath_hal*); 691 void __ahdecl(*ah_setRxFilter)(struct ath_hal*, uint32_t); 692 HAL_BOOL __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_desc *, 693 uint32_t size, u_int flags); 694 HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *, 695 struct ath_desc *, uint32_t phyAddr, 696 struct ath_desc *next, uint64_t tsf, 697 struct ath_rx_status *); 698 void __ahdecl(*ah_rxMonitor)(struct ath_hal *, 699 const HAL_NODE_STATS *, 700 const struct ieee80211_channel *); 701 void __ahdecl(*ah_procMibEvent)(struct ath_hal *, 702 const HAL_NODE_STATS *); 703 704 /* Misc Functions */ 705 HAL_STATUS __ahdecl(*ah_getCapability)(struct ath_hal *, 706 HAL_CAPABILITY_TYPE, uint32_t capability, 707 uint32_t *result); 708 HAL_BOOL __ahdecl(*ah_setCapability)(struct ath_hal *, 709 HAL_CAPABILITY_TYPE, uint32_t capability, 710 uint32_t setting, HAL_STATUS *); 711 HAL_BOOL __ahdecl(*ah_getDiagState)(struct ath_hal *, int request, 712 const void *args, uint32_t argsize, 713 void **result, uint32_t *resultsize); 714 void __ahdecl(*ah_getMacAddress)(struct ath_hal *, uint8_t *); 715 HAL_BOOL __ahdecl(*ah_setMacAddress)(struct ath_hal *, const uint8_t*); 716 void __ahdecl(*ah_getBssIdMask)(struct ath_hal *, uint8_t *); 717 HAL_BOOL __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const uint8_t*); 718 HAL_BOOL __ahdecl(*ah_setRegulatoryDomain)(struct ath_hal*, 719 uint16_t, HAL_STATUS *); 720 void __ahdecl(*ah_setLedState)(struct ath_hal*, HAL_LED_STATE); 721 void __ahdecl(*ah_writeAssocid)(struct ath_hal*, 722 const uint8_t *bssid, uint16_t assocId); 723 HAL_BOOL __ahdecl(*ah_gpioCfgOutput)(struct ath_hal *, 724 uint32_t gpio, HAL_GPIO_MUX_TYPE); 725 HAL_BOOL __ahdecl(*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio); 726 uint32_t __ahdecl(*ah_gpioGet)(struct ath_hal *, uint32_t gpio); 727 HAL_BOOL __ahdecl(*ah_gpioSet)(struct ath_hal *, 728 uint32_t gpio, uint32_t val); 729 void __ahdecl(*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t); 730 uint32_t __ahdecl(*ah_getTsf32)(struct ath_hal*); 731 uint64_t __ahdecl(*ah_getTsf64)(struct ath_hal*); 732 void __ahdecl(*ah_resetTsf)(struct ath_hal*); 733 HAL_BOOL __ahdecl(*ah_detectCardPresent)(struct ath_hal*); 734 void __ahdecl(*ah_updateMibCounters)(struct ath_hal*, 735 HAL_MIB_STATS*); 736 HAL_RFGAIN __ahdecl(*ah_getRfGain)(struct ath_hal*); 737 u_int __ahdecl(*ah_getDefAntenna)(struct ath_hal*); 738 void __ahdecl(*ah_setDefAntenna)(struct ath_hal*, u_int); 739 HAL_ANT_SETTING __ahdecl(*ah_getAntennaSwitch)(struct ath_hal*); 740 HAL_BOOL __ahdecl(*ah_setAntennaSwitch)(struct ath_hal*, 741 HAL_ANT_SETTING); 742 HAL_BOOL __ahdecl(*ah_setSifsTime)(struct ath_hal*, u_int); 743 u_int __ahdecl(*ah_getSifsTime)(struct ath_hal*); 744 HAL_BOOL __ahdecl(*ah_setSlotTime)(struct ath_hal*, u_int); 745 u_int __ahdecl(*ah_getSlotTime)(struct ath_hal*); 746 HAL_BOOL __ahdecl(*ah_setAckTimeout)(struct ath_hal*, u_int); 747 u_int __ahdecl(*ah_getAckTimeout)(struct ath_hal*); 748 HAL_BOOL __ahdecl(*ah_setAckCTSRate)(struct ath_hal*, u_int); 749 u_int __ahdecl(*ah_getAckCTSRate)(struct ath_hal*); 750 HAL_BOOL __ahdecl(*ah_setCTSTimeout)(struct ath_hal*, u_int); 751 u_int __ahdecl(*ah_getCTSTimeout)(struct ath_hal*); 752 HAL_BOOL __ahdecl(*ah_setDecompMask)(struct ath_hal*, uint16_t, int); 753 void __ahdecl(*ah_setCoverageClass)(struct ath_hal*, uint8_t, int); 754 755 /* Key Cache Functions */ 756 uint32_t __ahdecl(*ah_getKeyCacheSize)(struct ath_hal*); 757 HAL_BOOL __ahdecl(*ah_resetKeyCacheEntry)(struct ath_hal*, uint16_t); 758 HAL_BOOL __ahdecl(*ah_isKeyCacheEntryValid)(struct ath_hal *, 759 uint16_t); 760 HAL_BOOL __ahdecl(*ah_setKeyCacheEntry)(struct ath_hal*, 761 uint16_t, const HAL_KEYVAL *, 762 const uint8_t *, int); 763 HAL_BOOL __ahdecl(*ah_setKeyCacheEntryMac)(struct ath_hal*, 764 uint16_t, const uint8_t *); 765 766 /* Power Management Functions */ 767 HAL_BOOL __ahdecl(*ah_setPowerMode)(struct ath_hal*, 768 HAL_POWER_MODE mode, int setChip); 769 HAL_POWER_MODE __ahdecl(*ah_getPowerMode)(struct ath_hal*); 770 int16_t __ahdecl(*ah_getChanNoise)(struct ath_hal *, 771 const struct ieee80211_channel *); 772 773 /* Beacon Management Functions */ 774 void __ahdecl(*ah_setBeaconTimers)(struct ath_hal*, 775 const HAL_BEACON_TIMERS *); 776 /* NB: deprecated, use ah_setBeaconTimers instead */ 777 void __ahdecl(*ah_beaconInit)(struct ath_hal *, 778 uint32_t nexttbtt, uint32_t intval); 779 void __ahdecl(*ah_setStationBeaconTimers)(struct ath_hal*, 780 const HAL_BEACON_STATE *); 781 void __ahdecl(*ah_resetStationBeaconTimers)(struct ath_hal*); 782 783 /* Interrupt functions */ 784 HAL_BOOL __ahdecl(*ah_isInterruptPending)(struct ath_hal*); 785 HAL_BOOL __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT*); 786 HAL_INT __ahdecl(*ah_getInterrupts)(struct ath_hal*); 787 HAL_INT __ahdecl(*ah_setInterrupts)(struct ath_hal*, HAL_INT); 788 }; 789 790 /* 791 * Check the PCI vendor ID and device ID against Atheros' values 792 * and return a printable description for any Atheros hardware. 793 * AH_NULL is returned if the ID's do not describe Atheros hardware. 794 */ 795 extern const char *__ahdecl ath_hal_probe(uint16_t vendorid, uint16_t devid); 796 797 /* 798 * Attach the HAL for use with the specified device. The device is 799 * defined by the PCI device ID. The caller provides an opaque pointer 800 * to an upper-layer data structure (HAL_SOFTC) that is stored in the 801 * HAL state block for later use. Hardware register accesses are done 802 * using the specified bus tag and handle. On successful return a 803 * reference to a state block is returned that must be supplied in all 804 * subsequent HAL calls. Storage associated with this reference is 805 * dynamically allocated and must be freed by calling the ah_detach 806 * method when the client is done. If the attach operation fails a 807 * null (AH_NULL) reference will be returned and a status code will 808 * be returned if the status parameter is non-zero. 809 */ 810 extern struct ath_hal * __ahdecl ath_hal_attach(uint16_t devid, HAL_SOFTC, 811 HAL_BUS_TAG, HAL_BUS_HANDLE, HAL_STATUS* status); 812 813 extern const char *ath_hal_mac_name(struct ath_hal *); 814 extern const char *ath_hal_rf_name(struct ath_hal *); 815 816 /* 817 * Regulatory interfaces. Drivers should use ath_hal_init_channels to 818 * request a set of channels for a particular country code and/or 819 * regulatory domain. If CTRY_DEFAULT and SKU_NONE are specified then 820 * this list is constructed according to the contents of the EEPROM. 821 * ath_hal_getchannels acts similarly but does not alter the operating 822 * state; this can be used to collect information for a particular 823 * regulatory configuration. Finally ath_hal_set_channels installs a 824 * channel list constructed outside the driver. The HAL will adopt the 825 * channel list and setup internal state according to the specified 826 * regulatory configuration (e.g. conformance test limits). 827 * 828 * For all interfaces the channel list is returned in the supplied array. 829 * maxchans defines the maximum size of this array. nchans contains the 830 * actual number of channels returned. If a problem occurred then a 831 * status code != HAL_OK is returned. 832 */ 833 struct ieee80211_channel; 834 835 /* 836 * Return a list of channels according to the specified regulatory. 837 */ 838 extern HAL_STATUS __ahdecl ath_hal_getchannels(struct ath_hal *, 839 struct ieee80211_channel *chans, u_int maxchans, int *nchans, 840 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn, 841 HAL_BOOL enableExtendedChannels); 842 843 /* 844 * Return a list of channels and install it as the current operating 845 * regulatory list. 846 */ 847 extern HAL_STATUS __ahdecl ath_hal_init_channels(struct ath_hal *, 848 struct ieee80211_channel *chans, u_int maxchans, int *nchans, 849 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN rd, 850 HAL_BOOL enableExtendedChannels); 851 852 /* 853 * Install the list of channels as the current operating regulatory 854 * and setup related state according to the country code and sku. 855 */ 856 extern HAL_STATUS __ahdecl ath_hal_set_channels(struct ath_hal *, 857 struct ieee80211_channel *chans, int nchans, 858 HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn); 859 860 /* 861 * Calibrate noise floor data following a channel scan or similar. 862 * This must be called prior retrieving noise floor data. 863 */ 864 extern void __ahdecl ath_hal_process_noisefloor(struct ath_hal *ah); 865 866 /* 867 * Return bit mask of wireless modes supported by the hardware. 868 */ 869 extern u_int __ahdecl ath_hal_getwirelessmodes(struct ath_hal*); 870 871 /* 872 * Calculate the transmit duration of a frame. 873 */ 874 extern uint16_t __ahdecl ath_hal_computetxtime(struct ath_hal *, 875 const HAL_RATE_TABLE *rates, uint32_t frameLen, 876 uint16_t rateix, HAL_BOOL shortPreamble); 877 #endif /* _ATH_AH_H_ */ 878