1 /*- 2 * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 3. Neither the names of the above-listed copyright holders nor the names 16 * of any contributors may be used to endorse or promote products derived 17 * from this software without specific prior written permission. 18 * 19 * Alternatively, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") version 2 as published by the Free 21 * Software Foundation. 22 * 23 * NO WARRANTY 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 27 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 28 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 29 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 34 * THE POSSIBILITY OF SUCH DAMAGES. 35 * 36 * $FreeBSD$ 37 */ 38 #ifndef _ATH_AH_OSDEP_H_ 39 #define _ATH_AH_OSDEP_H_ 40 /* 41 * Atheros Hardware Access Layer (HAL) OS Dependent Definitions. 42 */ 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/endian.h> 46 47 #include <machine/bus.h> 48 49 /* 50 * Delay n microseconds. 51 */ 52 extern void ath_hal_delay(int); 53 #define OS_DELAY(_n) ath_hal_delay(_n) 54 55 #define OS_INLINE __inline 56 #define OS_MEMZERO(_a, _n) ath_hal_memzero((_a), (_n)) 57 extern void ath_hal_memzero(void *, size_t); 58 #define OS_MEMCPY(_d, _s, _n) ath_hal_memcpy(_d,_s,_n) 59 extern void *ath_hal_memcpy(void *, const void *, size_t); 60 61 #define abs(_a) __builtin_abs(_a) 62 63 struct ath_hal; 64 extern u_int32_t ath_hal_getuptime(struct ath_hal *); 65 #define OS_GETUPTIME(_ah) ath_hal_getuptime(_ah) 66 67 /* 68 * Register read/write operations are either handled through 69 * platform-dependent routines (or when debugging is enabled 70 * with AH_DEBUG); or they are inline expanded using the macros 71 * defined below. For public builds we inline expand only for 72 * platforms where it is certain what the requirements are to 73 * read/write registers--typically they are memory-mapped and 74 * no explicit synchronization or memory invalidation operations 75 * are required (e.g. i386). 76 */ 77 #if defined(AH_DEBUG) || defined(AH_REGOPS_FUNC) || defined(AH_DEBUG_ALQ) 78 #define OS_REG_WRITE(_ah, _reg, _val) ath_hal_reg_write(_ah, _reg, _val) 79 #define OS_REG_READ(_ah, _reg) ath_hal_reg_read(_ah, _reg) 80 81 extern void ath_hal_reg_write(struct ath_hal *ah, u_int reg, u_int32_t val); 82 extern u_int32_t ath_hal_reg_read(struct ath_hal *ah, u_int reg); 83 #else 84 /* 85 * The hardware registers are native little-endian byte order. 86 * Big-endian hosts are handled by enabling hardware byte-swap 87 * of register reads and writes at reset. But the PCI clock 88 * domain registers are not byte swapped! Thus, on big-endian 89 * platforms we have to explicitly byte-swap those registers. 90 * Most of this code is collapsed at compile time because the 91 * register values are constants. 92 */ 93 #define AH_LITTLE_ENDIAN 1234 94 #define AH_BIG_ENDIAN 4321 95 96 #if _BYTE_ORDER == _BIG_ENDIAN 97 #define OS_REG_WRITE(_ah, _reg, _val) do { \ 98 if ( (_reg) >= 0x4000 && (_reg) < 0x5000) \ 99 bus_space_write_4((bus_space_tag_t)(_ah)->ah_st, \ 100 (bus_space_handle_t)(_ah)->ah_sh, (_reg), (_val)); \ 101 else \ 102 bus_space_write_stream_4((bus_space_tag_t)(_ah)->ah_st, \ 103 (bus_space_handle_t)(_ah)->ah_sh, (_reg), (_val)); \ 104 } while (0) 105 #define OS_REG_READ(_ah, _reg) \ 106 (((_reg) >= 0x4000 && (_reg) < 0x5000) ? \ 107 bus_space_read_4((bus_space_tag_t)(_ah)->ah_st, \ 108 (bus_space_handle_t)(_ah)->ah_sh, (_reg)) : \ 109 bus_space_read_stream_4((bus_space_tag_t)(_ah)->ah_st, \ 110 (bus_space_handle_t)(_ah)->ah_sh, (_reg))) 111 #else /* _BYTE_ORDER == _LITTLE_ENDIAN */ 112 #define OS_REG_WRITE(_ah, _reg, _val) \ 113 bus_space_write_4((bus_space_tag_t)(_ah)->ah_st, \ 114 (bus_space_handle_t)(_ah)->ah_sh, (_reg), (_val)) 115 #define OS_REG_READ(_ah, _reg) \ 116 bus_space_read_4((bus_space_tag_t)(_ah)->ah_st, \ 117 (bus_space_handle_t)(_ah)->ah_sh, (_reg)) 118 #endif /* _BYTE_ORDER */ 119 #endif /* AH_DEBUG || AH_REGFUNC || AH_DEBUG_ALQ */ 120 121 #ifdef AH_DEBUG_ALQ 122 extern void OS_MARK(struct ath_hal *, u_int id, u_int32_t value); 123 #else 124 #define OS_MARK(_ah, _id, _v) 125 #endif 126 127 #endif /* _ATH_AH_OSDEP_H_ */ 128