1 /*- 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 * 29 * $FreeBSD$ 30 */ 31 #ifndef _ATH_AH_OSDEP_H_ 32 #define _ATH_AH_OSDEP_H_ 33 /* 34 * Atheros Hardware Access Layer (HAL) OS Dependent Definitions. 35 */ 36 #include <sys/cdefs.h> 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/endian.h> 40 #include <sys/linker_set.h> 41 42 #include <machine/bus.h> 43 44 /* 45 * Bus i/o type definitions. 46 */ 47 typedef void *HAL_SOFTC; 48 typedef bus_space_tag_t HAL_BUS_TAG; 49 typedef bus_space_handle_t HAL_BUS_HANDLE; 50 51 /* 52 * Linker set writearounds for chip and RF backend registration. 53 */ 54 #define OS_DATA_SET(set, item) DATA_SET(set, item) 55 #define OS_SET_DECLARE(set, ptype) SET_DECLARE(set, ptype) 56 #define OS_SET_FOREACH(pvar, set) SET_FOREACH(pvar, set) 57 58 /* 59 * Delay n microseconds. 60 */ 61 #define OS_DELAY(_n) DELAY(_n) 62 63 #define OS_INLINE __inline 64 #define OS_MEMZERO(_a, _n) bzero((_a), (_n)) 65 #define OS_MEMCPY(_d, _s, _n) memcpy(_d,_s,_n) 66 67 #define abs(_a) __builtin_abs(_a) 68 69 struct ath_hal; 70 71 /* 72 * Register read/write operations are either handled through 73 * platform-dependent routines (or when debugging is enabled 74 * with AH_DEBUG); or they are inline expanded using the macros 75 * defined below. For public builds we inline expand only for 76 * platforms where it is certain what the requirements are to 77 * read/write registers--typically they are memory-mapped and 78 * no explicit synchronization or memory invalidation operations 79 * are required (e.g. i386). 80 */ 81 #if defined(AH_DEBUG) || defined(AH_REGOPS_FUNC) || defined(AH_DEBUG_ALQ) 82 #define OS_REG_WRITE(_ah, _reg, _val) ath_hal_reg_write(_ah, _reg, _val) 83 #define OS_REG_READ(_ah, _reg) ath_hal_reg_read(_ah, _reg) 84 85 extern void ath_hal_reg_write(struct ath_hal *ah, u_int reg, u_int32_t val); 86 extern u_int32_t ath_hal_reg_read(struct ath_hal *ah, u_int reg); 87 #else 88 /* 89 * The hardware registers are native little-endian byte order. 90 * Big-endian hosts are handled by enabling hardware byte-swap 91 * of register reads and writes at reset. But the PCI clock 92 * domain registers are not byte swapped! Thus, on big-endian 93 * platforms we have to explicitly byte-swap those registers. 94 * Most of this code is collapsed at compile time because the 95 * register values are constants. 96 */ 97 #define AH_LITTLE_ENDIAN 1234 98 #define AH_BIG_ENDIAN 4321 99 100 #if _BYTE_ORDER == _BIG_ENDIAN 101 #define OS_REG_UNSWAPPED(_reg) \ 102 (((_reg) >= 0x4000 && (_reg) < 0x5000) || \ 103 ((_reg) >= 0x7000 && (_reg) < 0x8000)) 104 #define OS_REG_WRITE(_ah, _reg, _val) do { \ 105 if (OS_REG_UNSWAPPED(_reg)) \ 106 bus_space_write_4((bus_space_tag_t)(_ah)->ah_st, \ 107 (bus_space_handle_t)(_ah)->ah_sh, (_reg), (_val)); \ 108 else \ 109 bus_space_write_stream_4((bus_space_tag_t)(_ah)->ah_st, \ 110 (bus_space_handle_t)(_ah)->ah_sh, (_reg), (_val)); \ 111 } while (0) 112 #define OS_REG_READ(_ah, _reg) \ 113 (OS_REG_UNSWAPPED(_reg) ? \ 114 bus_space_read_4((bus_space_tag_t)(_ah)->ah_st, \ 115 (bus_space_handle_t)(_ah)->ah_sh, (_reg)) : \ 116 bus_space_read_stream_4((bus_space_tag_t)(_ah)->ah_st, \ 117 (bus_space_handle_t)(_ah)->ah_sh, (_reg))) 118 #else /* _BYTE_ORDER == _LITTLE_ENDIAN */ 119 #define OS_REG_UNSWAPPED(_reg) (0) 120 #define OS_REG_WRITE(_ah, _reg, _val) \ 121 bus_space_write_4((bus_space_tag_t)(_ah)->ah_st, \ 122 (bus_space_handle_t)(_ah)->ah_sh, (_reg), (_val)) 123 #define OS_REG_READ(_ah, _reg) \ 124 bus_space_read_4((bus_space_tag_t)(_ah)->ah_st, \ 125 (bus_space_handle_t)(_ah)->ah_sh, (_reg)) 126 #endif /* _BYTE_ORDER */ 127 #endif /* AH_DEBUG || AH_REGFUNC || AH_DEBUG_ALQ */ 128 129 #ifdef AH_DEBUG_ALQ 130 extern void OS_MARK(struct ath_hal *, u_int id, u_int32_t value); 131 #else 132 #define OS_MARK(_ah, _id, _v) 133 #endif 134 135 #endif /* _ATH_AH_OSDEP_H_ */ 136