1 /*- 2 * Copyright (c) 2002-2007 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 * 29 * $FreeBSD$ 30 */ 31 #ifndef _ATH_AH_OSDEP_H_ 32 #define _ATH_AH_OSDEP_H_ 33 /* 34 * Atheros Hardware Access Layer (HAL) OS Dependent Definitions. 35 */ 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/endian.h> 39 40 #include <machine/bus.h> 41 42 /* 43 * Delay n microseconds. 44 */ 45 extern void ath_hal_delay(int); 46 #define OS_DELAY(_n) ath_hal_delay(_n) 47 48 #define OS_INLINE __inline 49 #define OS_MEMZERO(_a, _n) ath_hal_memzero((_a), (_n)) 50 extern void ath_hal_memzero(void *, size_t); 51 #define OS_MEMCPY(_d, _s, _n) ath_hal_memcpy(_d,_s,_n) 52 extern void *ath_hal_memcpy(void *, const void *, size_t); 53 54 #define abs(_a) __builtin_abs(_a) 55 56 struct ath_hal; 57 extern u_int32_t ath_hal_getuptime(struct ath_hal *); 58 #define OS_GETUPTIME(_ah) ath_hal_getuptime(_ah) 59 60 /* 61 * Register read/write operations are either handled through 62 * platform-dependent routines (or when debugging is enabled 63 * with AH_DEBUG); or they are inline expanded using the macros 64 * defined below. For public builds we inline expand only for 65 * platforms where it is certain what the requirements are to 66 * read/write registers--typically they are memory-mapped and 67 * no explicit synchronization or memory invalidation operations 68 * are required (e.g. i386). 69 */ 70 #if defined(AH_DEBUG) || defined(AH_REGOPS_FUNC) || defined(AH_DEBUG_ALQ) 71 #define OS_REG_WRITE(_ah, _reg, _val) ath_hal_reg_write(_ah, _reg, _val) 72 #define OS_REG_READ(_ah, _reg) ath_hal_reg_read(_ah, _reg) 73 74 extern void ath_hal_reg_write(struct ath_hal *ah, u_int reg, u_int32_t val); 75 extern u_int32_t ath_hal_reg_read(struct ath_hal *ah, u_int reg); 76 #else 77 /* 78 * The hardware registers are native little-endian byte order. 79 * Big-endian hosts are handled by enabling hardware byte-swap 80 * of register reads and writes at reset. But the PCI clock 81 * domain registers are not byte swapped! Thus, on big-endian 82 * platforms we have to explicitly byte-swap those registers. 83 * Most of this code is collapsed at compile time because the 84 * register values are constants. 85 */ 86 #define AH_LITTLE_ENDIAN 1234 87 #define AH_BIG_ENDIAN 4321 88 89 #if _BYTE_ORDER == _BIG_ENDIAN 90 #define OS_REG_WRITE(_ah, _reg, _val) do { \ 91 if ( (_reg) >= 0x4000 && (_reg) < 0x5000) \ 92 bus_space_write_4((bus_space_tag_t)(_ah)->ah_st, \ 93 (bus_space_handle_t)(_ah)->ah_sh, (_reg), (_val)); \ 94 else \ 95 bus_space_write_stream_4((bus_space_tag_t)(_ah)->ah_st, \ 96 (bus_space_handle_t)(_ah)->ah_sh, (_reg), (_val)); \ 97 } while (0) 98 #define OS_REG_READ(_ah, _reg) \ 99 (((_reg) >= 0x4000 && (_reg) < 0x5000) ? \ 100 bus_space_read_4((bus_space_tag_t)(_ah)->ah_st, \ 101 (bus_space_handle_t)(_ah)->ah_sh, (_reg)) : \ 102 bus_space_read_stream_4((bus_space_tag_t)(_ah)->ah_st, \ 103 (bus_space_handle_t)(_ah)->ah_sh, (_reg))) 104 #else /* _BYTE_ORDER == _LITTLE_ENDIAN */ 105 #define OS_REG_WRITE(_ah, _reg, _val) \ 106 bus_space_write_4((bus_space_tag_t)(_ah)->ah_st, \ 107 (bus_space_handle_t)(_ah)->ah_sh, (_reg), (_val)) 108 #define OS_REG_READ(_ah, _reg) \ 109 bus_space_read_4((bus_space_tag_t)(_ah)->ah_st, \ 110 (bus_space_handle_t)(_ah)->ah_sh, (_reg)) 111 #endif /* _BYTE_ORDER */ 112 #endif /* AH_DEBUG || AH_REGFUNC || AH_DEBUG_ALQ */ 113 114 #ifdef AH_DEBUG_ALQ 115 extern void OS_MARK(struct ath_hal *, u_int id, u_int32_t value); 116 #else 117 #define OS_MARK(_ah, _id, _v) 118 #endif 119 120 #endif /* _ATH_AH_OSDEP_H_ */ 121