xref: /freebsd/sys/dev/ath/ah_osdep.c (revision 9162f64b58d01ec01481d60b6cdc06ffd8e8c7fc)
1 /*-
2  * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer,
10  *    without modification.
11  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13  *    redistribution must be conditioned upon including a substantially
14  *    similar Disclaimer requirement for further binary redistribution.
15  *
16  * NO WARRANTY
17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27  * THE POSSIBILITY OF SUCH DAMAGES.
28  *
29  * $FreeBSD$
30  */
31 #include "opt_ah.h"
32 
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/module.h>
37 #include <sys/sysctl.h>
38 #include <sys/bus.h>
39 #include <sys/malloc.h>
40 #include <sys/proc.h>
41 
42 #include <machine/stdarg.h>
43 
44 #include <net/ethernet.h>		/* XXX for ether_sprintf */
45 
46 #include <dev/ath/ath_hal/ah.h>
47 
48 /*
49  * WiSoC boards overload the bus tag with information about the
50  * board layout.  We must extract the bus space tag from that
51  * indirect structure.  For everyone else the tag is passed in
52  * directly.
53  * XXX cache indirect ref privately
54  */
55 #ifdef AH_SUPPORT_AR5312
56 #define	BUSTAG(ah) \
57 	((bus_space_tag_t) ((struct ar531x_config *)((ah)->ah_st))->tag)
58 #else
59 #define	BUSTAG(ah)	((ah)->ah_st)
60 #endif
61 
62 extern	void ath_hal_printf(struct ath_hal *, const char*, ...)
63 		__printflike(2,3);
64 extern	void ath_hal_vprintf(struct ath_hal *, const char*, __va_list)
65 		__printflike(2, 0);
66 extern	const char* ath_hal_ether_sprintf(const u_int8_t *mac);
67 extern	void *ath_hal_malloc(size_t);
68 extern	void ath_hal_free(void *);
69 #ifdef AH_ASSERT
70 extern	void ath_hal_assert_failed(const char* filename,
71 		int lineno, const char* msg);
72 #endif
73 #ifdef AH_DEBUG
74 #if HAL_ABI_VERSION >= 0x08090101
75 extern	void HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...);
76 #else
77 extern	void HALDEBUG(struct ath_hal *ah, const char* fmt, ...);
78 extern	void HALDEBUGn(struct ath_hal *ah, u_int level, const char* fmt, ...);
79 #endif
80 #endif /* AH_DEBUG */
81 
82 /* NB: put this here instead of the driver to avoid circular references */
83 SYSCTL_NODE(_hw, OID_AUTO, ath, CTLFLAG_RD, 0, "Atheros driver parameters");
84 SYSCTL_NODE(_hw_ath, OID_AUTO, hal, CTLFLAG_RD, 0, "Atheros HAL parameters");
85 
86 #ifdef AH_DEBUG
87 static	int ath_hal_debug = 0;
88 SYSCTL_INT(_hw_ath_hal, OID_AUTO, debug, CTLFLAG_RW, &ath_hal_debug,
89 	    0, "Atheros HAL debugging printfs");
90 TUNABLE_INT("hw.ath.hal.debug", &ath_hal_debug);
91 #endif /* AH_DEBUG */
92 
93 /* NB: these are deprecated; they exist for now for compatibility */
94 int	ath_hal_dma_beacon_response_time = 2;	/* in TU's */
95 SYSCTL_INT(_hw_ath_hal, OID_AUTO, dma_brt, CTLFLAG_RW,
96 	   &ath_hal_dma_beacon_response_time, 0,
97 	   "Atheros HAL DMA beacon response time");
98 int	ath_hal_sw_beacon_response_time = 10;	/* in TU's */
99 SYSCTL_INT(_hw_ath_hal, OID_AUTO, sw_brt, CTLFLAG_RW,
100 	   &ath_hal_sw_beacon_response_time, 0,
101 	   "Atheros HAL software beacon response time");
102 int	ath_hal_additional_swba_backoff = 0;	/* in TU's */
103 SYSCTL_INT(_hw_ath_hal, OID_AUTO, swba_backoff, CTLFLAG_RW,
104 	   &ath_hal_additional_swba_backoff, 0,
105 	   "Atheros HAL additional SWBA backoff time");
106 
107 MALLOC_DEFINE(M_ATH_HAL, "ath_hal", "ath hal data");
108 
109 void*
110 ath_hal_malloc(size_t size)
111 {
112 	return malloc(size, M_ATH_HAL, M_NOWAIT | M_ZERO);
113 }
114 
115 void
116 ath_hal_free(void* p)
117 {
118 	return free(p, M_ATH_HAL);
119 }
120 
121 void
122 ath_hal_vprintf(struct ath_hal *ah, const char* fmt, va_list ap)
123 {
124 	vprintf(fmt, ap);
125 }
126 
127 void
128 ath_hal_printf(struct ath_hal *ah, const char* fmt, ...)
129 {
130 	va_list ap;
131 	va_start(ap, fmt);
132 	ath_hal_vprintf(ah, fmt, ap);
133 	va_end(ap);
134 }
135 
136 const char*
137 ath_hal_ether_sprintf(const u_int8_t *mac)
138 {
139 	return ether_sprintf(mac);
140 }
141 
142 #ifdef AH_DEBUG
143 #if HAL_ABI_VERSION >= 0x08090101
144 void
145 HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...)
146 {
147 	if (ath_hal_debug & mask) {
148 		__va_list ap;
149 		va_start(ap, fmt);
150 		ath_hal_vprintf(ah, fmt, ap);
151 		va_end(ap);
152 	}
153 }
154 #else
155 void
156 HALDEBUG(struct ath_hal *ah, const char* fmt, ...)
157 {
158 	if (ath_hal_debug) {
159 		__va_list ap;
160 		va_start(ap, fmt);
161 		ath_hal_vprintf(ah, fmt, ap);
162 		va_end(ap);
163 	}
164 }
165 
166 void
167 HALDEBUGn(struct ath_hal *ah, u_int level, const char* fmt, ...)
168 {
169 	if (ath_hal_debug >= level) {
170 		__va_list ap;
171 		va_start(ap, fmt);
172 		ath_hal_vprintf(ah, fmt, ap);
173 		va_end(ap);
174 	}
175 }
176 #endif
177 #endif /* AH_DEBUG */
178 
179 #ifdef AH_DEBUG_ALQ
180 /*
181  * ALQ register tracing support.
182  *
183  * Setting hw.ath.hal.alq=1 enables tracing of all register reads and
184  * writes to the file /tmp/ath_hal.log.  The file format is a simple
185  * fixed-size array of records.  When done logging set hw.ath.hal.alq=0
186  * and then decode the file with the arcode program (that is part of the
187  * HAL).  If you start+stop tracing the data will be appended to an
188  * existing file.
189  *
190  * NB: doesn't handle multiple devices properly; only one DEVICE record
191  *     is emitted and the different devices are not identified.
192  */
193 #include <sys/alq.h>
194 #include <sys/pcpu.h>
195 #include <dev/ath/ath_hal/ah_decode.h>
196 
197 static	struct alq *ath_hal_alq;
198 static	int ath_hal_alq_emitdev;	/* need to emit DEVICE record */
199 static	u_int ath_hal_alq_lost;		/* count of lost records */
200 static	const char *ath_hal_logfile = "/tmp/ath_hal.log";
201 static	u_int ath_hal_alq_qsize = 64*1024;
202 
203 static int
204 ath_hal_setlogging(int enable)
205 {
206 	int error;
207 
208 	if (enable) {
209 		error = alq_open(&ath_hal_alq, ath_hal_logfile,
210 			curthread->td_ucred, ALQ_DEFAULT_CMODE,
211 			sizeof (struct athregrec), ath_hal_alq_qsize);
212 		ath_hal_alq_lost = 0;
213 		ath_hal_alq_emitdev = 1;
214 		printf("ath_hal: logging to %s enabled\n",
215 			ath_hal_logfile);
216 	} else {
217 		if (ath_hal_alq)
218 			alq_close(ath_hal_alq);
219 		ath_hal_alq = NULL;
220 		printf("ath_hal: logging disabled\n");
221 		error = 0;
222 	}
223 	return (error);
224 }
225 
226 static int
227 sysctl_hw_ath_hal_log(SYSCTL_HANDLER_ARGS)
228 {
229 	int error, enable;
230 
231 	enable = (ath_hal_alq != NULL);
232         error = sysctl_handle_int(oidp, &enable, 0, req);
233         if (error || !req->newptr)
234                 return (error);
235 	else
236 		return (ath_hal_setlogging(enable));
237 }
238 SYSCTL_PROC(_hw_ath_hal, OID_AUTO, alq, CTLTYPE_INT|CTLFLAG_RW,
239 	0, 0, sysctl_hw_ath_hal_log, "I", "Enable HAL register logging");
240 SYSCTL_INT(_hw_ath_hal, OID_AUTO, alq_size, CTLFLAG_RW,
241 	&ath_hal_alq_qsize, 0, "In-memory log size (#records)");
242 SYSCTL_INT(_hw_ath_hal, OID_AUTO, alq_lost, CTLFLAG_RW,
243 	&ath_hal_alq_lost, 0, "Register operations not logged");
244 
245 static struct ale *
246 ath_hal_alq_get(struct ath_hal *ah)
247 {
248 	struct ale *ale;
249 
250 	if (ath_hal_alq_emitdev) {
251 		ale = alq_get(ath_hal_alq, ALQ_NOWAIT);
252 		if (ale) {
253 			struct athregrec *r =
254 				(struct athregrec *) ale->ae_data;
255 			r->op = OP_DEVICE;
256 			r->reg = 0;
257 			r->val = ah->ah_devid;
258 			alq_post(ath_hal_alq, ale);
259 			ath_hal_alq_emitdev = 0;
260 		} else
261 			ath_hal_alq_lost++;
262 	}
263 	ale = alq_get(ath_hal_alq, ALQ_NOWAIT);
264 	if (!ale)
265 		ath_hal_alq_lost++;
266 	return ale;
267 }
268 
269 void
270 ath_hal_reg_write(struct ath_hal *ah, u_int32_t reg, u_int32_t val)
271 {
272 	bus_space_tag_t tag = BUSTAG(ah);
273 	bus_space_handle_t h = ah->ah_sh;
274 
275 	if (ath_hal_alq) {
276 		struct ale *ale = ath_hal_alq_get(ah);
277 		if (ale) {
278 			struct athregrec *r = (struct athregrec *) ale->ae_data;
279 			r->op = OP_WRITE;
280 			r->reg = reg;
281 			r->val = val;
282 			alq_post(ath_hal_alq, ale);
283 		}
284 	}
285 #if _BYTE_ORDER == _BIG_ENDIAN
286 	if (reg >= 0x4000 && reg < 0x5000)
287 		bus_space_write_4(tag, h, reg, val);
288 	else
289 #endif
290 		bus_space_write_stream_4(tag, h, reg, val);
291 }
292 
293 u_int32_t
294 ath_hal_reg_read(struct ath_hal *ah, u_int32_t reg)
295 {
296 	bus_space_tag_t tag = BUSTAG(ah);
297 	bus_space_handle_t h = ah->ah_sh;
298 	u_int32_t val;
299 
300 #if _BYTE_ORDER == _BIG_ENDIAN
301 	if (reg >= 0x4000 && reg < 0x5000)
302 		val = bus_space_read_4(tag, h, reg);
303 	else
304 #endif
305 		val = bus_space_read_stream_4(tag, h, reg);
306 	if (ath_hal_alq) {
307 		struct ale *ale = ath_hal_alq_get(ah);
308 		if (ale) {
309 			struct athregrec *r = (struct athregrec *) ale->ae_data;
310 			r->op = OP_READ;
311 			r->reg = reg;
312 			r->val = val;
313 			alq_post(ath_hal_alq, ale);
314 		}
315 	}
316 	return val;
317 }
318 
319 void
320 OS_MARK(struct ath_hal *ah, u_int id, u_int32_t v)
321 {
322 	if (ath_hal_alq) {
323 		struct ale *ale = ath_hal_alq_get(ah);
324 		if (ale) {
325 			struct athregrec *r = (struct athregrec *) ale->ae_data;
326 			r->op = OP_MARK;
327 			r->reg = id;
328 			r->val = v;
329 			alq_post(ath_hal_alq, ale);
330 		}
331 	}
332 }
333 #elif defined(AH_DEBUG) || defined(AH_REGOPS_FUNC)
334 /*
335  * Memory-mapped device register read/write.  These are here
336  * as routines when debugging support is enabled and/or when
337  * explicitly configured to use function calls.  The latter is
338  * for architectures that might need to do something before
339  * referencing memory (e.g. remap an i/o window).
340  *
341  * NB: see the comments in ah_osdep.h about byte-swapping register
342  *     reads and writes to understand what's going on below.
343  */
344 
345 void
346 ath_hal_reg_write(struct ath_hal *ah, u_int32_t reg, u_int32_t val)
347 {
348 	bus_space_tag_t tag = BUSTAG(ah);
349 	bus_space_handle_t h = ah->ah_sh;
350 
351 #if _BYTE_ORDER == _BIG_ENDIAN
352 	if (reg >= 0x4000 && reg < 0x5000)
353 		bus_space_write_4(tag, h, reg, val);
354 	else
355 #endif
356 		bus_space_write_stream_4(tag, h, reg, val);
357 }
358 
359 u_int32_t
360 ath_hal_reg_read(struct ath_hal *ah, u_int32_t reg)
361 {
362 	bus_space_tag_t tag = BUSTAG(ah);
363 	bus_space_handle_t h = ah->ah_sh;
364 	u_int32_t val;
365 
366 #if _BYTE_ORDER == _BIG_ENDIAN
367 	if (reg >= 0x4000 && reg < 0x5000)
368 		val = bus_space_read_4(tag, h, reg);
369 	else
370 #endif
371 		val = bus_space_read_stream_4(tag, h, reg);
372 	return val;
373 }
374 #endif /* AH_DEBUG || AH_REGOPS_FUNC */
375 
376 #ifdef AH_ASSERT
377 void
378 ath_hal_assert_failed(const char* filename, int lineno, const char *msg)
379 {
380 	printf("Atheros HAL assertion failure: %s: line %u: %s\n",
381 		filename, lineno, msg);
382 	panic("ath_hal_assert");
383 }
384 #endif /* AH_ASSERT */
385 
386 /*
387  * Delay n microseconds.
388  */
389 void
390 ath_hal_delay(int n)
391 {
392 	DELAY(n);
393 }
394 
395 u_int32_t
396 ath_hal_getuptime(struct ath_hal *ah)
397 {
398 	struct bintime bt;
399 	getbinuptime(&bt);
400 	return (bt.sec * 1000) +
401 		(((uint64_t)1000 * (uint32_t)(bt.frac >> 32)) >> 32);
402 }
403 
404 void
405 ath_hal_memzero(void *dst, size_t n)
406 {
407 	bzero(dst, n);
408 }
409 
410 void *
411 ath_hal_memcpy(void *dst, const void *src, size_t n)
412 {
413 	return memcpy(dst, src, n);
414 }
415