1 /*- 2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/module.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/ata.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/malloc.h> 38 #include <sys/lock.h> 39 #include <sys/mutex.h> 40 #include <sys/sema.h> 41 #include <sys/taskqueue.h> 42 #include <vm/uma.h> 43 #include <machine/stdarg.h> 44 #include <machine/resource.h> 45 #include <machine/bus.h> 46 #include <sys/rman.h> 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pcireg.h> 49 #include <dev/ata/ata-all.h> 50 #include <dev/ata/ata-pci.h> 51 #include <ata_if.h> 52 53 /* local prototypes */ 54 static int ata_via_chipinit(device_t dev); 55 static int ata_via_ch_attach(device_t dev); 56 static int ata_via_ch_detach(device_t dev); 57 static void ata_via_reset(device_t dev); 58 static int ata_via_status(device_t dev); 59 static int ata_via_old_setmode(device_t dev, int target, int mode); 60 static void ata_via_southbridge_fixup(device_t dev); 61 static int ata_via_new_setmode(device_t dev, int target, int mode); 62 static int ata_via_sata_ch_attach(device_t dev); 63 static int ata_via_sata_getrev(device_t dev, int target); 64 static int ata_via_sata_setmode(device_t dev, int target, int mode); 65 static void ata_via_sata_reset(device_t dev); 66 static int ata_via_sata_scr_read(device_t dev, int port, int reg, 67 u_int32_t *result); 68 static int ata_via_sata_scr_write(device_t dev, int port, int reg, 69 u_int32_t value); 70 static int ata_via_sata_status(device_t dev); 71 72 /* misc defines */ 73 #define VIA33 0 74 #define VIA66 1 75 #define VIA100 2 76 #define VIA133 3 77 78 #define VIACLK 0x01 79 #define VIABUG 0x02 80 #define VIABAR 0x04 81 #define VIAAHCI 0x08 82 #define VIASATA 0x10 83 84 /* 85 * VIA Technologies Inc. chipset support functions 86 */ 87 static int 88 ata_via_probe(device_t dev) 89 { 90 struct ata_pci_controller *ctlr = device_get_softc(dev); 91 static const struct ata_chip_id ids[] = 92 {{ ATA_VIA82C586, 0x02, VIA33, 0x00, ATA_UDMA2, "82C586B" }, 93 { ATA_VIA82C586, 0x00, VIA33, 0x00, ATA_WDMA2, "82C586" }, 94 { ATA_VIA82C596, 0x12, VIA66, VIACLK, ATA_UDMA4, "82C596B" }, 95 { ATA_VIA82C596, 0x00, VIA33, 0x00, ATA_UDMA2, "82C596" }, 96 { ATA_VIA82C686, 0x40, VIA100, VIABUG, ATA_UDMA5, "82C686B"}, 97 { ATA_VIA82C686, 0x10, VIA66, VIACLK, ATA_UDMA4, "82C686A" }, 98 { ATA_VIA82C686, 0x00, VIA33, 0x00, ATA_UDMA2, "82C686" }, 99 { ATA_VIA8231, 0x00, VIA100, VIABUG, ATA_UDMA5, "8231" }, 100 { ATA_VIA8233, 0x00, VIA100, 0x00, ATA_UDMA5, "8233" }, 101 { ATA_VIA8233C, 0x00, VIA100, 0x00, ATA_UDMA5, "8233C" }, 102 { ATA_VIA8233A, 0x00, VIA133, 0x00, ATA_UDMA6, "8233A" }, 103 { ATA_VIA8235, 0x00, VIA133, 0x00, ATA_UDMA6, "8235" }, 104 { ATA_VIA8237, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" }, 105 { ATA_VIA8237A, 0x00, VIA133, 0x00, ATA_UDMA6, "8237A" }, 106 { ATA_VIA8237S, 0x00, VIA133, 0x00, ATA_UDMA6, "8237S" }, 107 { ATA_VIA8237_5372, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" }, 108 { ATA_VIA8237_7372, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" }, 109 { ATA_VIA8251, 0x00, VIA133, 0x00, ATA_UDMA6, "8251" }, 110 { ATA_VIACX700, 0x00, VIA133, VIASATA, ATA_SA150, "CX700" }, 111 { ATA_VIAVX800, 0x00, VIA133, VIASATA, ATA_SA150, "VX800" }, 112 { ATA_VIAVX855, 0x00, VIA133, 0x00, ATA_UDMA6, "VX855" }, 113 { ATA_VIAVX900, 0x00, VIA133, VIASATA, ATA_SA300, "VX900" }, 114 { 0, 0, 0, 0, 0, 0 }}; 115 static const struct ata_chip_id new_ids[] = 116 {{ ATA_VIA6410, 0x00, 0, 0x00, ATA_UDMA6, "6410" }, 117 { ATA_VIA6420, 0x00, 7, 0x00, ATA_SA150, "6420" }, 118 { ATA_VIA6421, 0x00, 6, VIABAR, ATA_SA150, "6421" }, 119 { ATA_VIA8237A, 0x00, 7, 0x00, ATA_SA150, "8237A" }, 120 { ATA_VIA8237S, 0x00, 7, 0x00, ATA_SA150, "8237S" }, 121 { ATA_VIA8237_5372, 0x00, 7, 0x00, ATA_SA300, "8237" }, 122 { ATA_VIA8237_7372, 0x00, 7, 0x00, ATA_SA300, "8237" }, 123 { ATA_VIA8251, 0x00, 0, VIAAHCI, ATA_SA300, "8251" }, 124 { 0, 0, 0, 0, 0, 0 }}; 125 126 if (pci_get_vendor(dev) != ATA_VIA_ID) 127 return ENXIO; 128 129 if (pci_get_devid(dev) == ATA_VIA82C571 || 130 pci_get_devid(dev) == ATA_VIACX700IDE || 131 pci_get_devid(dev) == ATA_VIASATAIDE || 132 pci_get_devid(dev) == ATA_VIASATAIDE2 || 133 pci_get_devid(dev) == ATA_VIASATAIDE3) { 134 if (!(ctlr->chip = ata_find_chip(dev, ids, -99))) 135 return ENXIO; 136 } 137 else { 138 if (!(ctlr->chip = ata_match_chip(dev, new_ids))) 139 return ENXIO; 140 } 141 142 ata_set_desc(dev); 143 ctlr->chipinit = ata_via_chipinit; 144 return (BUS_PROBE_DEFAULT); 145 } 146 147 static int 148 ata_via_chipinit(device_t dev) 149 { 150 struct ata_pci_controller *ctlr = device_get_softc(dev); 151 152 if (ata_setup_interrupt(dev, ata_generic_intr)) 153 return ENXIO; 154 155 /* AHCI SATA */ 156 if (ctlr->chip->cfg2 & VIAAHCI) { 157 if (ata_ahci_chipinit(dev) != ENXIO) 158 return (0); 159 } 160 /* 2 SATA with "SATA registers" at PCI config space + PATA on secondary */ 161 if (ctlr->chip->cfg2 & VIASATA) { 162 ctlr->ch_attach = ata_via_sata_ch_attach; 163 ctlr->setmode = ata_via_sata_setmode; 164 ctlr->getrev = ata_via_sata_getrev; 165 ctlr->reset = ata_via_sata_reset; 166 return 0; 167 } 168 /* Legacy SATA/SATA+PATA with SATA registers in BAR(5). */ 169 if (ctlr->chip->max_dma >= ATA_SA150) { 170 ctlr->r_type2 = SYS_RES_IOPORT; 171 ctlr->r_rid2 = PCIR_BAR(5); 172 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 173 &ctlr->r_rid2, RF_ACTIVE))) { 174 ctlr->ch_attach = ata_via_ch_attach; 175 ctlr->ch_detach = ata_via_ch_detach; 176 ctlr->reset = ata_via_reset; 177 } 178 if (ctlr->chip->cfg2 & VIABAR) { 179 ctlr->channels = 3; 180 ctlr->setmode = ata_via_new_setmode; 181 } else 182 ctlr->setmode = ata_sata_setmode; 183 ctlr->getrev = ata_sata_getrev; 184 return 0; 185 } 186 187 /* prepare for ATA-66 on the 82C686a and 82C596b */ 188 if (ctlr->chip->cfg2 & VIACLK) 189 pci_write_config(dev, 0x50, 0x030b030b, 4); 190 191 /* the southbridge might need the data corruption fix */ 192 if (ctlr->chip->cfg2 & VIABUG) 193 ata_via_southbridge_fixup(dev); 194 195 /* set fifo configuration half'n'half */ 196 pci_write_config(dev, 0x43, 197 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1); 198 199 /* set status register read retry */ 200 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1); 201 202 /* set DMA read & end-of-sector fifo flush */ 203 pci_write_config(dev, 0x46, 204 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1); 205 206 /* set sector size */ 207 pci_write_config(dev, 0x60, DEV_BSIZE, 2); 208 pci_write_config(dev, 0x68, DEV_BSIZE, 2); 209 210 ctlr->setmode = ata_via_old_setmode; 211 return 0; 212 } 213 214 static int 215 ata_via_ch_attach(device_t dev) 216 { 217 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 218 struct ata_channel *ch = device_get_softc(dev); 219 220 /* newer SATA chips has resources in one BAR for each channel */ 221 if (ctlr->chip->cfg2 & VIABAR) { 222 struct resource *r_io; 223 int i, rid; 224 225 ata_pci_dmainit(dev); 226 227 rid = PCIR_BAR(ch->unit); 228 if (!(r_io = bus_alloc_resource_any(device_get_parent(dev), 229 SYS_RES_IOPORT, 230 &rid, RF_ACTIVE))) 231 return ENXIO; 232 233 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) { 234 ch->r_io[i].res = r_io; 235 ch->r_io[i].offset = i; 236 } 237 ch->r_io[ATA_CONTROL].res = r_io; 238 ch->r_io[ATA_CONTROL].offset = 2 + ATA_IOSIZE; 239 ch->r_io[ATA_IDX_ADDR].res = r_io; 240 ata_default_registers(dev); 241 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) { 242 ch->r_io[i].res = ctlr->r_res1; 243 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE); 244 } 245 ata_pci_hw(dev); 246 if (ch->unit >= 2) 247 return 0; 248 } 249 else { 250 /* setup the usual register normal pci style */ 251 if (ata_pci_ch_attach(dev)) 252 return ENXIO; 253 } 254 255 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 256 ch->r_io[ATA_SSTATUS].offset = (ch->unit << ctlr->chip->cfg1); 257 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 258 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << ctlr->chip->cfg1); 259 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 260 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << ctlr->chip->cfg1); 261 ch->hw.status = ata_via_status; 262 ch->flags |= ATA_NO_SLAVE; 263 ch->flags |= ATA_SATA; 264 ch->flags |= ATA_PERIODIC_POLL; 265 266 ata_sata_scr_write(ch, -1, ATA_SERROR, 0xffffffff); 267 268 return 0; 269 } 270 271 static int 272 ata_via_ch_detach(device_t dev) 273 { 274 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 275 struct ata_channel *ch = device_get_softc(dev); 276 277 /* newer SATA chips has resources in one BAR for each channel */ 278 if (ctlr->chip->cfg2 & VIABAR) { 279 int rid; 280 281 rid = PCIR_BAR(ch->unit); 282 bus_release_resource(device_get_parent(dev), 283 SYS_RES_IOPORT, rid, ch->r_io[ATA_CONTROL].res); 284 285 ata_pci_dmafini(dev); 286 } 287 else { 288 /* setup the usual register normal pci style */ 289 if (ata_pci_ch_detach(dev)) 290 return ENXIO; 291 } 292 293 return 0; 294 } 295 296 static void 297 ata_via_reset(device_t dev) 298 { 299 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 300 struct ata_channel *ch = device_get_softc(dev); 301 302 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1)) 303 ata_generic_reset(dev); 304 else { 305 if (ata_sata_phy_reset(dev, -1, 1)) 306 ata_generic_reset(dev); 307 else 308 ch->devices = 0; 309 } 310 } 311 312 static int 313 ata_via_status(device_t dev) 314 { 315 316 ata_sata_phy_check_events(dev, -1); 317 return (ata_pci_status(dev)); 318 } 319 320 static int 321 ata_via_new_setmode(device_t dev, int target, int mode) 322 { 323 device_t parent = device_get_parent(dev); 324 struct ata_pci_controller *ctlr = device_get_softc(parent); 325 struct ata_channel *ch = device_get_softc(dev); 326 327 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1)) { 328 int piomode; 329 static const uint8_t pio_timings[] = 330 { 0xa8, 0x65, 0x65, 0x32, 0x20 }; 331 static const uint8_t dma_timings[] = 332 { 0xee, 0xe8, 0xe6, 0xe4, 0xe2, 0xe1, 0xe0 }; 333 334 /* This chip can't do WDMA. */ 335 if (mode >= ATA_WDMA0 && mode < ATA_UDMA0) 336 mode = ATA_PIO4; 337 if (mode >= ATA_UDMA0) { 338 pci_write_config(parent, 0xb3, 339 dma_timings[mode & ATA_MODE_MASK], 1); 340 piomode = ATA_PIO4; 341 } else 342 piomode = mode; 343 pci_write_config(parent, 0xab, pio_timings[ata_mode2idx(piomode)], 1); 344 } else 345 mode = ata_sata_setmode(dev, target, mode); 346 return (mode); 347 } 348 349 static int 350 ata_via_old_setmode(device_t dev, int target, int mode) 351 { 352 device_t parent = device_get_parent(dev); 353 struct ata_pci_controller *ctlr = device_get_softc(parent); 354 struct ata_channel *ch = device_get_softc(dev); 355 int devno = (ch->unit << 1) + target; 356 int reg = 0x53 - devno; 357 int piomode; 358 static const uint8_t timings[] = 359 { 0xa8, 0x65, 0x42, 0x22, 0x20, 0xa8, 0x22, 0x20 }; 360 static const uint8_t modes[][7] = { 361 { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */ 362 { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */ 363 { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */ 364 { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 } }; /* VIA ATA133 */ 365 366 mode = min(mode, ctlr->chip->max_dma); 367 /* Set UDMA timings */ 368 if (mode >= ATA_UDMA0) { 369 pci_write_config(parent, reg, 370 modes[ctlr->chip->cfg1][mode & ATA_MODE_MASK], 1); 371 piomode = ATA_PIO4; 372 } else { 373 pci_write_config(parent, reg, 0x8b, 1); 374 piomode = mode; 375 } 376 /* Set WDMA/PIO timings */ 377 pci_write_config(parent, reg - 0x08,timings[ata_mode2idx(piomode)], 1); 378 return (mode); 379 } 380 381 static void 382 ata_via_southbridge_fixup(device_t dev) 383 { 384 device_t *children; 385 int nchildren, i; 386 387 if (device_get_children(device_get_parent(dev), &children, &nchildren)) 388 return; 389 390 for (i = 0; i < nchildren; i++) { 391 if (pci_get_devid(children[i]) == ATA_VIA8363 || 392 pci_get_devid(children[i]) == ATA_VIA8371 || 393 pci_get_devid(children[i]) == ATA_VIA8662 || 394 pci_get_devid(children[i]) == ATA_VIA8361) { 395 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1); 396 397 if ((reg76 & 0xf0) != 0xd0) { 398 device_printf(dev, 399 "Correcting VIA config for southbridge data corruption bug\n"); 400 pci_write_config(children[i], 0x75, 0x80, 1); 401 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1); 402 } 403 break; 404 } 405 } 406 free(children, M_TEMP); 407 } 408 409 static int 410 ata_via_sata_ch_attach(device_t dev) 411 { 412 struct ata_channel *ch = device_get_softc(dev); 413 414 if (ata_pci_ch_attach(dev)) 415 return ENXIO; 416 if (ch->unit == 0) { 417 ch->hw.status = ata_via_sata_status; 418 ch->hw.pm_read = ata_via_sata_scr_read; 419 ch->hw.pm_write = ata_via_sata_scr_write; 420 ch->flags |= ATA_PERIODIC_POLL; 421 ch->flags |= ATA_SATA; 422 ata_sata_scr_write(ch, 0, ATA_SERROR, 0xffffffff); 423 ata_sata_scr_write(ch, 1, ATA_SERROR, 0xffffffff); 424 } 425 return (0); 426 } 427 428 static int 429 ata_via_sata_getrev(device_t dev, int target) 430 { 431 device_t parent = device_get_parent(dev); 432 struct ata_channel *ch = device_get_softc(dev); 433 434 if (ch->unit == 0) { 435 if (pci_read_config(parent, 0xa0 + target, 1) & 0x10) 436 return (2); 437 else 438 return (1); 439 } 440 return (0); 441 } 442 443 static int 444 ata_via_sata_setmode(device_t dev, int target, int mode) 445 { 446 struct ata_channel *ch = device_get_softc(dev); 447 448 if (ch->unit == 0) 449 return (mode); 450 return (ata_via_old_setmode(dev, target, mode)); 451 } 452 453 static void 454 ata_via_sata_reset(device_t dev) 455 { 456 struct ata_channel *ch = device_get_softc(dev); 457 int devs; 458 459 if (ch->unit == 0) { 460 devs = ata_sata_phy_reset(dev, 0, 0); 461 DELAY(10000); 462 devs += ata_sata_phy_reset(dev, 1, 0); 463 } else 464 devs = 1; 465 if (devs) 466 ata_generic_reset(dev); 467 else 468 ch->devices = 0; 469 } 470 471 static int 472 ata_via_sata_scr_read(device_t dev, int port, int reg, u_int32_t *result) 473 { 474 device_t parent; 475 uint32_t val; 476 477 parent = device_get_parent(dev); 478 port = (port == 1) ? 1 : 0; 479 switch (reg) { 480 case ATA_SSTATUS: 481 val = pci_read_config(parent, 0xa0 + port, 1); 482 *result = val & 0x03; 483 if (*result != ATA_SS_DET_NO_DEVICE) { 484 if (val & 0x04) 485 *result |= ATA_SS_IPM_PARTIAL; 486 else if (val & 0x08) 487 *result |= ATA_SS_IPM_SLUMBER; 488 else 489 *result |= ATA_SS_IPM_ACTIVE; 490 if (val & 0x10) 491 *result |= ATA_SS_SPD_GEN2; 492 else 493 *result |= ATA_SS_SPD_GEN1; 494 } 495 break; 496 case ATA_SERROR: 497 *result = pci_read_config(parent, 0xa8 + port * 4, 4); 498 break; 499 case ATA_SCONTROL: 500 val = pci_read_config(parent, 0xa4 + port, 1); 501 *result = 0; 502 if (val & 0x01) 503 *result |= ATA_SC_DET_RESET; 504 if (val & 0x02) 505 *result |= ATA_SC_DET_DISABLE; 506 if (val & 0x04) 507 *result |= ATA_SC_IPM_DIS_PARTIAL; 508 if (val & 0x08) 509 *result |= ATA_SC_IPM_DIS_SLUMBER; 510 break; 511 default: 512 return (EINVAL); 513 } 514 return (0); 515 } 516 517 static int 518 ata_via_sata_scr_write(device_t dev, int port, int reg, u_int32_t value) 519 { 520 device_t parent; 521 uint32_t val; 522 523 parent = device_get_parent(dev); 524 port = (port == 1) ? 1 : 0; 525 switch (reg) { 526 case ATA_SERROR: 527 pci_write_config(parent, 0xa8 + port * 4, value, 4); 528 break; 529 case ATA_SCONTROL: 530 val = 0; 531 if (value & ATA_SC_DET_RESET) 532 val |= 0x01; 533 if (value & ATA_SC_DET_DISABLE) 534 val |= 0x02; 535 if (value & ATA_SC_IPM_DIS_PARTIAL) 536 val |= 0x04; 537 if (value & ATA_SC_IPM_DIS_SLUMBER) 538 val |= 0x08; 539 pci_write_config(parent, 0xa4 + port, val, 1); 540 break; 541 default: 542 return (EINVAL); 543 } 544 return (0); 545 } 546 547 static int 548 ata_via_sata_status(device_t dev) 549 { 550 551 ata_sata_phy_check_events(dev, 0); 552 ata_sata_phy_check_events(dev, 1); 553 return (ata_pci_status(dev)); 554 } 555 556 ATA_DECLARE_DRIVER(ata_via); 557 MODULE_DEPEND(ata_via, ata_ahci, 1, 1, 1); 558